JPH09321551A - Voltage divider circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a voltage divider circuit that has a high input impedance, is small in the circuit scale and has a small output voltage error. SOLUTION: The voltage divider circuit is configured by an input terminal 1, an output terminal 2, a 1st voltage-current conversion circuit 3 whose input terminal connects to the input terminal 1 and having one output terminal, a 1st current mirror circuit 4 whose input terminal connects to the output terminal of the 1st voltage-current conversion circuit 3 and whose output terminal connects to the output terminal 2 respectively, and a resistor R1 connected between the output terminal 2 and ground. Then the 1st voltage-current conversion circuit 3 is configured by using a plurality of transistors(TRs) of the same polarity so that its output current is proportional to the input voltage by cancelling each emitter-base voltage of each TR.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage dividing circuit for dividing an input voltage by a resistance ratio and outputting the divided voltage.

[0002]

2. Description of the Related Art Various types of voltage dividing circuits have been proposed for dividing an input voltage by a resistance ratio and outputting the divided voltage. A typical example is shown in FIG. This voltage divider consists of resistor 102 and resistor 10.
3 is connected in series, the output terminal 104 is connected to the connection point of the resistor 102 and the resistor 103, the input terminal 101 is connected to the other end of the resistor 102, and the other end of the resistor 103 is grounded. The input voltage V _IN applied to the input terminal 101 is the resistance 10
Divided by the resistance value R ₂ of the second resistance value R ₁ and the resistor 103, the output terminal 104 (R ₁ + R ₂₎ and the ratio between the input voltage of the R ₂ V _IN
Outputs a voltage proportional to. This output voltage V _O is expressed by the following equation (1). V _O = [R ₂ / (R ₁ + R ₂ )] ・ V _IN・ ・ ・ ・ (1)

Another voltage dividing circuit has a structure shown in FIG. This voltage dividing circuit is obtained by connecting the buffer 105 to the input terminal 101 of the voltage dividing circuit shown in FIG.
The buffer 105 is connected to perform impedance conversion, and if this voltage dividing circuit is used, the input impedance becomes high. The output voltage V _O is represented by the equation (1) as in the voltage dividing circuit shown in FIG.

Further, in the voltage dividing circuit shown in FIG. 13, when the output voltage is changed, the resistor 103 is connected in parallel with the resistor 103.
6 is connected via a switch 107, and the switch 107 is turned on / off to change the output voltage V _O.
A transistor is usually used as the switch 107.

On the other hand, for example, FIG. 16 shows Japanese Patent Publication No. 6-18304.
It is a voltage dividing circuit composed of a current mirror circuit and a resistor disclosed in Japanese Patent Laid-Open Publication No. HEI. This voltage dividing circuit supplies a start-up circuit 201 which supplies a current required for operating the transistors Q201 and Q202, and a collector current of the transistor Q202 which is converted from the input voltage V _IN by the transistors Q201 and Q202 and the resistor Ra. It is composed of a current mirror circuit 202 which inputs, inverts the polarity, and outputs from one output terminal to the output resistor Rb. In the voltage dividing circuit configured in this way, the input voltage V _IN
When There is applied, the voltage V _R across the resistor Ra,
It is expressed by the following equation (2). V _R = V _IN + V _BEQ201 −V _{BEQ202 ...} (2) Note that V _BEQ201 and V _BEQ202 in the equation (2) are the base-emitter voltages of the transistors Q201 and Q202, respectively. . Here, when V _BEQ201 = V _BEQ202, voltage V _R
Is represented by the following equation (3). V _R = V _IN (3) Therefore, the collector current of the transistor Q202 is V
It becomes _IN / Ra. This current is returned by the current mirror circuit 202 and flows to the resistor Rb, so that the output voltage V
_OUT is represented by the following equation (4). V _OUT = (Rb / Ra) · V _IN (4) Therefore, the input voltage V _IN is divided by the ratio of the resistors Ra and Rb.

[0006]

By the way, the voltage divider circuit shown in FIG. 13 can easily realize a voltage divider circuit.
If the output of a circuit with a low output impedance is connected to the input terminal of the voltage divider circuit of this configuration, the error increases as the output current increases. is there.

The voltage dividing circuit shown in FIG. 14 improves the drawbacks of the voltage dividing circuit shown in FIG. In this voltage dividing circuit, a buffer is connected to the input terminal of the voltage dividing circuit shown in FIG. 13, and the input impedance is high. Therefore, it is not affected by the previous circuit. However, since the buffer is used, when the buffer is composed of an operational amplifier, a capacitor for phase compensation is required, which has a drawback that the circuit scale becomes large.

The voltage dividing circuit shown in FIG. 16 solves the above problems. However, the above formula (3) is V _BEQ201
= V _BEQ202 , and the transistors Q ₂₀₁ and Q ₂₀₂ are respectively
Since it is a pnp transistor and an npn transistor, V _BEQ201
And V _BEQ202 are different values. Therefore, the above equation (3) does not hold accurately, and the output voltage V _OUT represented by the equation (4) always causes an error. Therefore,
There is a problem in that accurate voltage division cannot be obtained even by the voltage dividing circuit shown in FIG.

The present invention has been made to solve the above problems in the conventional voltage divider circuit, and an object thereof is to provide a voltage divider circuit having a high input impedance, a small circuit scale, and a small error.

[0010]

In order to solve the above problems, the present invention provides an input terminal 1 as shown in the conceptual diagram of FIG.
Connect the input terminal to the output terminal 2 and the input terminal 1
A first voltage-current conversion circuit 3 having two output terminals, and a first current mirror circuit 4 having an input terminal connected to the output terminal of the first voltage-current conversion circuit 3 and an output terminal connected to the output terminal 2. And a first resistor R1 provided between the output terminal 2 and one terminal of the power supply, and the first voltage-current conversion circuit 3 has a plurality of transistors having the same polarity and has an input terminal. Is used as the base of the transistor, the output current of the first voltage-current conversion circuit 3 is configured to cancel the emitter-base voltage of each transistor and to be proportional to the input voltage. Configure.

In the voltage dividing circuit thus configured,
Since the base of the transistor is used as the input terminal of the first voltage-current conversion circuit 3 connected to the input terminal 1, the input impedance can be increased. Further, since the buffer composed of the operational amplifier is not used, the capacitor for phase compensation is not required, and the circuit scale can be reduced. Further, since the first voltage-current conversion circuit 3 is configured to cancel the base-emitter voltage of the transistors having the same polarity, the error in the output voltage can be reduced.

[0012]

Next, an embodiment will be described. FIG. 2 is a circuit configuration diagram showing a concrete first embodiment of the voltage dividing circuit according to the present invention. In this embodiment,
In the first voltage-current conversion circuit 3 in the conceptual diagram of the present invention shown in FIG. 1, the emitter is grounded and the base is the second resistor R.
A first transistor Q1 grounded via a second transistor Q2, an emitter connected to the base of the first transistor Q1, a second transistor Q2 whose base is connected to the collector of the first transistor Q1, and a second collector Q2. Third transistor Q connected to the collector of the transistor Q2 of
3 and a third resistor R3 provided between the emitter of the third transistor Q3, the collector of the first transistor Q1 and the base of the second transistor Q2.
The base of the transistor Q3 is connected to the input terminal 1, and the collector of the second transistor Q2 and the collector of the third transistor Q3 are connected to the input terminal of the first current mirror circuit 4.

Next, the operation of the first embodiment configured as described above will be described. The current flowing through the third resistor R3 is I ₁ , the current flowing through the second resistor R2 is I ₂ , the current flowing through the first resistor R1 is I _3, and the resistance value R ₃ of the third resistor R3 is the second value. Value R ₂ of the resistor R ₂ of the first resistor R
Assuming that the resistance value R ₁ is ₁ , I ₁ and I ₂ are expressed by the following equations (5) and (6), respectively. In addition, each transistor Q
The base-emitter voltage of 1, Q2 and Q3 is V _BE , and the input voltage is V _IN . I ₁ = (V _IN -3V _BE ) / R ₃・ ・ ・ ・ ・ ・ ・ ・ ・ ・ (5) I ₂ = V _BE / R ₂・ ・ ・ ・ ・(6) since the current (I ₁ + I ₂₎ is folded back in the first current mirror circuit 4, when _{R 2 = R 3/3,} I 3 is expressed by the following equation (7). I ₃ = I ₁ + I ₂ = V _IN / R ₃ (7) Note that the base current of the transistor is neglected here, and this condition will be described below. Since the output voltage V ₀ is the voltage drop of the first resistor R1 due to I ₃ , it is expressed by the following equation (8). V ₀ = I ₃ · R ₁ = (R ₁ / R ₃ ) · V _IN (8) From the equation (8), the input voltage V _IN is the third resistor R3 and the first resistor R1. It can be seen that the voltage is divided by the ratio.

In the procedure for deriving the output voltage V ₀ ,
3V _BE of the equation (5) is the base-emitter voltage of the first, second and third transistors Q1, Q2, Q3, and V _BE of the equation (6) is the base voltage of the first transistor Q1. It is the voltage between the emitters. Transistors Q1, Q
Since 2 and Q3 are all composed of npn transistors, V _BE becomes almost equal, and the influence of V _BE disappears in the equation (7). As a result, the error in the output voltage due to V _BE is reduced.

Further, in the voltage dividing circuit according to the first embodiment shown in FIG. 2, the input terminal 1 has the transistor Q3.
Since it is connected to the base of, the circuit with high input impedance can be realized. Further, since the voltage dividing circuit can be realized without using an operational amplifier, the circuit scale can be reduced.

In the first embodiment, the npn transistor forming the first voltage-current conversion circuit is changed to a pnp transistor, and the pnp transistor forming the first current mirror circuit is changed to an npn transistor, so that the power supply and the ground are exchanged. As a result, as shown in FIG. 3, it is possible to realize a voltage divider circuit in which both the input voltage and the output voltage are based on the power supply. In addition, in FIG. 3, Q4, Q5, and Q6 are pnp
4th, 5th and 6th transistors in the shape of the first, 2nd and 3rd transistors Q in the voltage dividing circuit shown in FIG.
It corresponds to 1, Q2 and Q3. The relationship between the input voltage and the output voltage in this voltage dividing circuit can be derived in the same manner as in the voltage dividing circuit shown in FIG. 2, and is expressed by the following equation (9). _{V CC -V 0 = I 3 ·} R 1 = Note _{(R 1 / R 3) ·} (V CC -V IN) ··· (9), V CC is the voltage of the power supply.

FIG. 4 shows a modification of the first embodiment in which the output voltage is changed in the voltage dividing circuit according to the first embodiment shown in FIG. Conventionally,
When changing the output voltage in the voltage divider circuit, the configuration shown in Fig. 15 is used, but if a transistor is used as a switch in the voltage divider circuit shown in Fig. 15, the collector-emitter voltage of the transistor The presence of V _CE creates a potential difference between the parallel resistance and ground.
Therefore, an error occurs in the output voltage.

On the other hand, in the voltage divider circuit shown in FIG. 4, the current mirror circuit 4 has a plurality of output terminals (3 in the illustrated example).
The switch 5 is provided between the output terminal and the output terminal 2, and this switch is turned on / off to change the current flowing to the resistor R1 and change the output voltage. Output terminals and output terminals 2 of the current mirror circuit 4
If a transistor is used as the switch 5 provided between them,
A slight potential difference is generated between the output terminal of the current mirror circuit 4 and the output terminal 2. However, since the output of the current mirror circuit 4 has a large output impedance, no error occurs in the output current. Therefore, it is possible to accurately change the output voltage.

Next, a second embodiment will be described. FIG. 5 is a block diagram of the second embodiment.
Is a concrete circuit configuration diagram thereof. The voltage divider circuit according to this embodiment has an input terminal connected to the input terminal 1, has two output terminals, and outputs a current proportional to a value obtained by subtracting the base-emitter voltage from the input voltage. Of the voltage-current conversion circuit 11, the emitter of which is grounded through the fourth resistor R4, the collector of which is connected to the first output terminal of the second voltage-current conversion circuit 11, and the emitter of which is An eighth transistor Q8, which is grounded and whose collector is connected to the base of the seventh transistor Q7, whose base is connected to the emitter of the seventh transistor Q7, and whose input terminal is the second transistor of the second voltage-current conversion circuit 11. And a second current mirror circuit 12 whose output end is connected to the base of the seventh transistor Q7 and the collector of the eighth transistor Q8, respectively, to form a first voltage-current conversion circuit. . Further, similarly to the first embodiment, the input end is connected to the first output end of the second voltage-current conversion circuit 11 and the collector of the seventh transistor Q7, and the output end is connected to the output terminal 2, respectively. The first current mirror circuit 5 and the first resistor R1 connected between the output terminal of the first current mirror circuit 5 and the ground are provided to form a voltage dividing circuit.

As shown in FIG. 6, the second voltage-current conversion circuit 11 has a ninth transistor Q9 whose emitter is grounded through the fifth resistor R5 and whose base is connected to the input terminal 1. , Its emitter is grounded through a sixth resistor R6, and its base is composed of a tenth transistor Q10 connected to the input terminal 1, and its input end is a ninth transistor Q10.
At the base of the first output terminal of the ninth transistor Q9
The second output terminal is connected to the collector of the
Connected to each collector.

Next, the operation of the second embodiment thus configured will be described. In FIG. 6, the resistance value of the fourth resistor R4 is R ₄ , and the resistance value of the fifth resistor R5 is R ₅
If the current flowing through the fifth resistor R5 is I ₄ , the current flowing through the fourth resistor R4 is I ₅ , and the current flowing through the first resistor R1 is I ₆ , then I ₄ and I ₅ are given by ), (11). I ₄ = (V _IN −V _BE ) / R ₅・ ・ ・ ・ ・ ・ ・ ・ ・ ・ (10) I ₅ = V _BE / R ₄・ ・ ・ ・ ・ ・ ・ ・ ・ ・(11) Further, since I ₆ is the sum of I ₄ and I ₅ , I ₆ is represented by the following equation (12) when R ₄ = R ₅ . I ₆ = I ₄ + I ₅ = V _IN / R ₅ (12) Therefore, the output voltage V ₀ is expressed by the following equation (13). V ₀ = I ₆ · R ₁ = (R ₁ / R ₅ ) · V _IN (13) From the above equation (13), the input voltage V _IN is equal to the resistance value R _{5 of the fifth} resistor R ₅ . It can be seen that the voltage is divided by the ratio of the resistance value R ₁ of the first resistor R1.

In the procedure for deriving the output voltage V ₀ ,
V _BE of the equation (10) is the base-emitter voltage of the ninth transistor Q9, and V _BE of the equation (11) is the base-emitter voltage of the eighth transistor Q8. The transistors Q8 and Q9 are formed of npn transistors, and since the collector currents of the transistors are equal, V _BE becomes equal to each other, and the influence of V _BE disappears in the equation (12). As a result,
The error in the output voltage due to V _BE is reduced. Also in this embodiment, since the input terminal is connected to the base of the transistor, a circuit with high input impedance can be formed, and a voltage dividing circuit can be realized without using an operational amplifier, so that the circuit scale can be reduced. It is possible.

In the second embodiment, the npn transistor forming the first voltage-current conversion circuit is changed to a pnp transistor, and the pnp transistors forming the first and second current mirror circuits are changed to npn transistors. By exchanging the ground, as shown in FIG. 7, it is possible to realize a voltage dividing circuit in which both the input voltage and the output voltage are based on the power supply. Note that in FIG. 7, Q7 ', Q
8 ', Q11, and Q12 are pnp type transistors, which are the seventh to tenth transistors Q7 to Q7 in the voltage dividing circuit shown in FIG.
It corresponds to Q10. The relationship between the input voltage and the output voltage in this voltage dividing circuit can be derived in the same manner as in the voltage dividing circuit shown in FIG. 6, and is expressed by the following equation (14). V _CC- V ₀ = I ₆ · R ₁ = (R ₁ / R ₅ ) · (V _CC −V _IN ) ... (14) Next, in the case of changing the output voltage, A modified example is shown in FIG. In the modification shown in FIG. 8 as well, similar to the voltage divider circuit shown in FIG. 4, the first current mirror circuit 4 is provided with a plurality of outputs, and each output of the first current mirror circuit 4 and the output terminal 2 are connected. A switch is provided between them to configure. Also in the case of this modification, the error of the output voltage can be reduced as compared with the conventional example for the same reason as that of the voltage dividing circuit shown in FIG.

Next, a third embodiment will be described. FIG. 9 is a block diagram showing the third embodiment.
FIG. 10 is a specific circuit configuration diagram thereof. In the voltage divider circuit according to this embodiment, a collector is grounded together, a base is connected to the input terminal 1, a thirteenth transistor Q13 and a fourteenth transistor Q14, and a base is a first power supply 21.
In addition, a fifteenth transistor Q15 whose emitter is connected to the emitter of a thirteenth transistor Q13 via a seventh resistor R7, a base of the first power source 21 and a base of the fifteenth transistor Q15, and an emitter of A sixteenth transistor Q16 connected to the emitter of the fourteenth transistor Q14 via an eighth resistor R8, and a base of the fifteenth transistor Q15 and the bases of the sixteenth transistor Q16 and the first power supply 21, respectively. A seventeenth transistor Q17 which is connected and whose emitter is grounded via a ninth resistor R9;
An eighteenth transistor Q18 whose emitter is connected to the second power supply 22 through the tenth resistor R10, whose collector is connected to the collector of the seventeenth transistor Q17, and whose base is connected to the collector of the sixteenth transistor Q16; Is the second power source
A nineteenth transistor Q19 having a base connected to the emitter of the eighteenth transistor Q18, a collector connected to the collector of the sixteenth transistor Q16 and a base of the eighteenth transistor Q18, and an input end connected to the fifteenth transistor. And a second current mirror circuit 23 whose output end is connected to the collector of the seventeenth transistor Q17 and the collector of the eighteenth transistor Q18, respectively, to form a first voltage-current conversion circuit. .

Further, the input end is connected to the collector of the seventeenth transistor Q17, the collector of the eighteenth transistor Q18 and the output end of the second current mirror circuit 23, and the output end is connected to the output terminal 2, respectively. A current divider circuit 1 and a first resistor R1 connected between the output terminal of the first current mirror circuit 4 and the ground are provided to form a voltage dividing circuit.

Next, the operation of the third embodiment configured as described above will be described. 9 and 10,
Resistance R ₇ of the seventh resistor R7, the resistance value R ₈ of the resistor R8 of the eighth, ninth and resistance R ₉ of the resistor R9, the tenth resistor R10
Is set to R _10, and the current flowing through the seventh resistor R 7 is I
₇ , the current flowing through the eighth resistor R8 is I ₈ , and the current flowing through the tenth resistor R8 is
The current flowing through 10 is I ₉ , the output current of the second current mirror circuit 23 is I ₁₀ , the current flowing through the ninth resistor R9 is I ₁₁ ,
Assuming that the input current of the first current mirror circuit 4 is I ₁₂ , the current flowing through the first resistor R1 is I _13, and the output voltage V _ref of the first power supply is the current I ₇ , I ₉ , I ₁₀ , I. ₁₁ is represented by the following equations (15), (16), (17), (18). _{, I 7 = (V ref -2V} BE -V IN) / R 7 ······ (15) I 9 = V BE / R 10 ················ _{(16) I 10 = I 7} ··················· (17) I 11 = (V ref -V BE) / R 9 ······· (18) Further, I ₉ , I ₁₀ , I ₁₁ , and I ₁₂ have the relationship shown in the following equation (19). And _{I 11 = I 9 + I 10} + I 12 ············ (19) R 7 = R 9 = R 10, (15) ~ (18) by substituting expression (19) below , I ₁₂ is solved, I ₁₂ is expressed by the following equation (20). I ₁₂ = V _IN / R ₇ (20) Since I ₁₃ = I ₁₂ , the output voltage V ₀ is expressed by the following equation (21). . V ₀ = (R ₁ / R ₇ ) · V _IN ······························· (21) From the equation (21), the input voltage V _IN is divided by the ratio of R ₇ and R _1. I understand that.

In the above output voltage deriving procedure, (15)
2V _BE in the equation is the 13th and 15th transistor Q1 respectively.
3, the base-emitter voltage of Q15, (16),
V _BE of the equation (18) is the base-emitter voltage of the 19th and 17th transistors Q19 and Q17, respectively. In the voltage divider circuit of this embodiment, V _BE canceled out is the transistors Q13 and Q19, and the transistors Q15 and Q17 when expressed as a single transistor. Transistors Q13 and Q19 are both pnp
It is a transistor, and transistors Q15 and Q17 are both n
It is a pn transistor. Therefore, since the polarities of the canceled transistors are equal, V _BE becomes equal,
In equation (20), the effect of V _BE is small. As a result, V _BE
The error in the output voltage due to

In the voltage divider circuit according to this embodiment, since the input terminal is connected to the base of the transistor, a circuit having high input impedance can be realized. Further, since the voltage dividing circuit can be realized without using an operational amplifier, the circuit scale can be reduced.

Further, in the voltage dividing circuit according to the present embodiment, the input voltage is 0 in the transistors Q13 and Q14.
Since it is more than V, the collector-emitter voltage V _CE is V _CE
≧ V _BE . Therefore, even when V _IN = 0 V, the transistors Q13 and Q14 do not saturate, and the input can be from the ground level. Therefore, the lower limit of the input voltage range can be set lower than those of the voltage dividing circuits according to the first and second embodiments shown in FIGS.

In the third embodiment, the npn transistor is a pnp transistor and the pnp transistor is an npn transistor.
By replacing the transistor with a power source and ground, as shown in FIG. 11, it is possible to realize a voltage dividing circuit in which both the input voltage and the output voltage are based on the power source. Note that FIG.
In FIG. 9, the transistors corresponding to the transistors in the third embodiment shown in FIG. 9 are denoted by the same reference numerals with dashes. The relationship between the input voltage and the output voltage in this voltage dividing circuit can be derived in the same manner as in the voltage dividing circuit shown in FIGS. 9 and 10, and is expressed by the following equation (22). V _CC −V ₀ = I ₁₃ · R ₁ = (R ₁ / R ₇ ) · (V _CC −V _IN ) ... (22) Partial voltage of the modification of the third embodiment shown in FIG. 11. The circuit is
Since the circuit has the power supply and the ground switched, it operates normally even when the input voltage is the second power supply V _CC .

FIG. 12 shows a modification of the third embodiment when the output voltage is changed. Similarly to the voltage divider circuit shown in FIG. 4, the modification shown in FIG. 12 is also configured by providing a plurality of output terminals in the first current mirror circuit and providing a switch between the output terminal and each output terminal. It is a thing. Also in the case of this modification, for the same reason as that of the voltage dividing circuit shown in FIG.
It is possible to reduce the error in the output voltage as compared with the conventional example.

[0032]

As described above based on the embodiments, according to the present invention, since the base of the transistor is connected to the input terminal, the input impedance can be increased and the buffer including the operational amplifier can be provided. Since it is not necessary to use it, the circuit scale can be reduced.
Since the voltage between the emitters is canceled, the error in the output voltage can be reduced.

[Brief description of drawings]

FIG. 1 is a conceptual diagram for explaining a voltage dividing circuit according to the present invention.

FIG. 2 is a circuit configuration diagram showing a first embodiment of a voltage dividing circuit according to the present invention.

FIG. 3 is a circuit configuration diagram showing a modified example of the first embodiment shown in FIG.

FIG. 4 is a schematic configuration diagram showing another modified example of the first embodiment shown in FIG.

FIG. 5 is a block configuration diagram showing a second embodiment of the present invention.

FIG. 6 is a circuit configuration diagram of the second embodiment shown in FIG.

FIG. 7 is a block configuration diagram showing a modification of the second embodiment shown in FIG.

8 is a schematic configuration diagram showing another modified example of the second embodiment shown in FIG.

FIG. 9 is a block diagram showing a third embodiment of the present invention.

FIG. 10 is a circuit configuration diagram of the third embodiment shown in FIG. 9.

FIG. 11 is a block configuration diagram showing a modification of the third embodiment shown in FIG. 9.

FIG. 12 is a schematic configuration diagram showing another modification of the third embodiment shown in FIG. 9.

FIG. 13 is a diagram showing a configuration example of a conventional voltage dividing circuit.

FIG. 14 is a diagram showing another configuration example of a conventional voltage dividing circuit.

15 is a diagram showing a configuration in the case of changing the output voltage in the conventional example shown in FIG.

FIG. 16 is a diagram showing still another configuration example of the conventional voltage dividing circuit.

[Explanation of symbols]

 1 Input Terminal 2 Output Terminal 3 First Voltage / Current Conversion Circuit 4 First Current Mirror Circuit 11 Second Voltage / Current Conversion Circuit 12 Second Current Mirror Circuit 21 First Power Supply 22 Second Power Supply 23 Second Current mirror circuit

Claims (8)

[Claims] 1. A first voltage-current conversion circuit having an input terminal, an output terminal, an input terminal connected to the input terminal and having one output terminal, and an input terminal of the first voltage-current conversion circuit. The output terminal includes a first current mirror circuit having an output terminal connected to the output terminal, and a first resistor provided between the output terminal and one terminal of a power supply. The current conversion circuit has a plurality of transistors having the same polarity, uses the base of the transistor as an input terminal, and the output current of the first voltage-current conversion circuit cancels the emitter-base voltage of each transistor. A voltage dividing circuit characterized by being configured to be proportional to an input voltage. 2. The first voltage-current conversion circuit includes a first transistor whose emitter is grounded and whose base is grounded through a second resistor, and whose emitter is the base of the first transistor and whose base is the first transistor. A second transistor connected to the collector of the first transistor, a third transistor whose collector is connected to the collector of the second transistor, an emitter of the third transistor, a collector of the first transistor, and a second transistor And a third resistor provided between the base of the transistor and the base of the third transistor as an input end, and the collector of the second transistor and the collector of the third transistor as an output end. The voltage dividing circuit according to claim 1, which is characterized in that. 3. The first voltage-current conversion circuit includes a fourth transistor having an emitter connected to a power supply and a base connected to a power supply via a second resistor, and an emitter connected to a base of the fourth transistor. , A fifth transistor whose base is connected to the collector of the fourth transistor, respectively,
A sixth transistor whose collector is connected to the collector of the fifth transistor, and a third resistor provided between the emitter of the sixth transistor and the collector of the fourth transistor and the base of the fifth transistor. 2. The voltage dividing circuit according to claim 1, wherein the sixth transistor has a base as an input terminal and a collector of the fifth transistor and a collector of the sixth transistor as an output terminal. 4. The first voltage-current conversion circuit has an input terminal and first and second output terminals, and is proportional to a value obtained by subtracting the base-emitter voltage of a transistor existing inside from the input voltage. A second voltage-current conversion circuit that outputs the generated current, the emitter is connected to one terminal of the power supply through the fourth resistor, and the collector is connected to the first output end of the second voltage-current conversion circuit. A seventh transistor, an emitter connected to one terminal of the power supply, a collector connected to the base of the seventh transistor, an eighth transistor connected to the emitter of the seventh transistor at the base, and an input terminal A second output terminal of the second voltage-current conversion circuit, and a second current mirror circuit whose output terminal is connected to the base of the seventh transistor and the collector of the eighth transistor, respectively. The input terminal of the second voltage-current conversion circuit is the input terminal of the first voltage-current conversion circuit, and the first output terminal of the second voltage-current conversion circuit and the collector of the seventh transistor are the first voltage-current conversion circuit. 2. The voltage dividing circuit according to claim 1, wherein the voltage dividing circuit is an output terminal of the voltage dividing circuit. 5. In the second voltage-current conversion circuit, an emitter is grounded through a fifth resistor, a base is connected to an input end of a ninth transistor, and an emitter is connected through a sixth resistor. A ninth transistor which is grounded and whose base is connected to the input end, and which has the collector of the ninth transistor as the first output end and the collector of the tenth transistor as the second output end. The voltage dividing circuit according to claim 4, wherein the voltage dividing circuit is a voltage dividing circuit. 6. An eleventh transistor having an emitter connected to a power supply via a fifth resistor, a base connected to an input end, and an emitter connected to a sixth voltage-current conversion circuit.
Is connected to the power supply via the resistor and the base is connected to the input terminal, and the collector of the eleventh transistor is the first output terminal and the collector of the twelfth transistor is the second terminal. 5. The voltage dividing circuit according to claim 4, wherein the voltage dividing circuit is an output terminal of the voltage dividing circuit. 7. The first voltage-current conversion circuit includes: a thirteenth and a fourteenth transistors, collectors of which are both grounded and bases of which are commonly connected; a base of which is a first power supply; and an emitter of which is a seventh power supply. A fifteenth transistor connected to the emitter of the thirteenth transistor via a resistor, a base of the first power supply and the base of the fifteenth transistor, and an emitter of the fourteenth transistor via the eighth resistor. A sixteenth transistor connected to the emitters, and a seventeenth transistor whose bases are connected to the bases of the fifteenth and sixteenth transistors and the first power supply, respectively, and the emitters of which are grounded via the ninth resistor. , The emitter is connected to the second power supply through the tenth resistor, the collector is connected to the collector of the seventeenth transistor, and the base is connected to the collector of the sixteenth transistor. And Njisuta, the emitter second power supply, a base to the emitter of the eighteenth transistor, the collector and the collector is the 16th transistor 18
, The input end of which is connected to the collector of the fifteenth transistor, and the output end of which is connected to the collector of the seventeenth transistor and the collector of the eighteenth transistor, respectively. A current mirror circuit, the bases of the thirteenth transistor and the fourteenth transistor as input ends, the output end of the second current mirror circuit, the collector of the seventeenth transistor and the collector of the eighteenth transistor as output ends The voltage dividing circuit according to claim 1, wherein 8. The first current mirror circuit is provided with a plurality of output terminals, and the output terminals are connected to an output terminal via a switch. The voltage dividing circuit according to item.