JPH09321429A - Manufacture of multilayer wiring board - Google Patents

Manufacture of multilayer wiring board

Info

Publication number
JPH09321429A
JPH09321429A JP13672996A JP13672996A JPH09321429A JP H09321429 A JPH09321429 A JP H09321429A JP 13672996 A JP13672996 A JP 13672996A JP 13672996 A JP13672996 A JP 13672996A JP H09321429 A JPH09321429 A JP H09321429A
Authority
JP
Japan
Prior art keywords
resin layer
insulating resin
reference hole
conductor circuit
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13672996A
Other languages
Japanese (ja)
Inventor
Hajime Sugiyama
肇 杉山
Masayuki Ishihara
政行 石原
Shuji Maeda
修二 前田
Shingo Yoshioka
慎悟 吉岡
Eiichiro Saito
英一郎 斉藤
Shinichi Iketani
晋一 池谷
Hiroaki Fujiwara
弘明 藤原
Katsuhiko Ito
克彦 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP13672996A priority Critical patent/JPH09321429A/en
Publication of JPH09321429A publication Critical patent/JPH09321429A/en
Pending legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method wherein a large formation area of a conductor circuit can be obtained while ensuring reliability in a manufacturing method wherein an insulation resin layer is formed after a reference hole is stopped up by using an adhesive tape, a reference hole is exposed and then a conductor circuit is formed by using a reference hole as a reference for positioning. SOLUTION: In this method, a projection part 11 enclosing a reference hole 3 is provided to a core board 2 before an insulation resin layer is formed and a reference hole is stopped up by an adhesive tape put within a range which is enclosed with the projection part 11. Or the projection part 11 enclosing the reference hole 3 with an edge of the core board 2 is provided in the core board 2 before an insulation resin layer is formed and a reference hole is stopped up by an adhesive tape put within a range enclosed with an edge of the core board 2 and the projection part 11.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、電子・電気機器等
に使用される多層配線板の製造方法に関し、さらに詳し
くは絶縁樹脂層上に導体回路を形成する積み上げ方式の
多層配線板の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer wiring board used for electronic and electric equipment, and more particularly to a method for manufacturing a stacked type multilayer wiring board in which a conductor circuit is formed on an insulating resin layer. Regarding

【0002】[0002]

【従来の技術】近年、電子・電気機器の小型化、軽量化
に伴い、多層配線板の薄型化が要望されている。この要
望を満たすものとして絶縁樹脂層上に導体回路を形成す
る積み上げ方式の多層配線板が注目されている。その製
造方法としては下記の工程を順次行う方法が知られてい
る。 表面に導体回路を形成済みのコア基板(多層化基板を
含む)の一方の表面に絶縁樹脂層を形成する。 得られた絶縁樹脂層にビアホールを形成する。 銅メッキ等の方法で絶縁樹脂層上に導体回路を形成す
る。この際前記ビアホールにも導体を付与し、この導体
によりコア基板の導体回路と絶縁樹脂層上の導体回路を
電気的に接続する。 以下、上記の工程を繰り返して所望の多層配線板を製
造する。
2. Description of the Related Art In recent years, as electronic and electric devices have become smaller and lighter, there has been a demand for thinner multilayer wiring boards. In order to meet this demand, a stack-type multilayer wiring board in which a conductor circuit is formed on an insulating resin layer is receiving attention. As a manufacturing method thereof, a method of sequentially performing the following steps is known. An insulating resin layer is formed on one surface of a core substrate (including a multi-layered substrate) on which a conductor circuit has been formed. A via hole is formed in the obtained insulating resin layer. A conductor circuit is formed on the insulating resin layer by a method such as copper plating. At this time, a conductor is also provided in the via hole, and the conductor circuit of the core substrate and the conductor circuit on the insulating resin layer are electrically connected by this conductor. Hereinafter, the above-mentioned steps are repeated to manufacture a desired multilayer wiring board.

【0003】上記の積み上げ方式の多層配線板の製造方
法では、図4に示すように、導体回路1及び複数個の基
準穴3を形成したコア基板2を準備し〔図4(a)〕、
基準穴3を接着性のテープ4を用いて塞いだ後〔図4
(b)〕、基準穴3を被覆して絶縁樹脂層5を形成し
〔図4(c)〕、次いで例えばナイフ等を用いて基準穴
3の上の絶縁樹脂層5及びテープ4を除去して基準穴3
を露出させ、次いでこの露出させた基準穴3を導体回路
形成のための位置決めの基準として用いて、絶縁樹脂層
5上に新たな導体回路を形成することが従来行われてい
る。
In the above-mentioned stacking type multilayer wiring board manufacturing method, as shown in FIG. 4, a core substrate 2 having a conductor circuit 1 and a plurality of reference holes 3 formed therein is prepared [FIG. 4 (a)],
After closing the reference hole 3 with an adhesive tape 4 [Fig.
(B)], the insulating resin layer 5 is formed by covering the reference hole 3 [FIG. 4 (c)], and then the insulating resin layer 5 and the tape 4 on the reference hole 3 are removed by using, for example, a knife. Reference hole 3
Conventionally, a new conductor circuit is formed on the insulating resin layer 5 by using the exposed reference hole 3 as a reference for positioning for forming a conductor circuit.

【0004】しかし、上記の従来の方法では、絶縁樹脂
層5を形成する際に、接着性のテープ4の接着剤成分が
周囲に染み出し、染み出した部分では絶縁樹脂層5の膜
厚が不均一となるという問題や、絶縁樹脂層5が剥離し
やすくなる問題等の多層配線板の信頼性を損なう問題が
生じていた。
However, in the above-mentioned conventional method, when the insulating resin layer 5 is formed, the adhesive component of the adhesive tape 4 exudes to the surroundings, and the film thickness of the insulating resin layer 5 at the exuded portion is reduced. There have been problems that the reliability of the multilayer wiring board is impaired, such as the problem of non-uniformity and the problem that the insulating resin layer 5 is easily peeled off.

【0005】[0005]

【発明が解決しようとする課題】本発明は上記のような
事情に鑑みてなされたものであって、その目的とすると
ころは、コア基板に設けた複数個の基準穴を接着性のテ
ープを用いて塞いだ後、基準穴を被覆して絶縁樹脂層を
形成し、次いで基準穴を露出させ、次いでこの露出させ
た基準穴を導体回路形成のための位置決めの基準として
用いて、絶縁樹脂層上に導体回路を形成する多層配線板
の製造方法であって、接着性のテープの接着剤成分の染
み出す範囲を小さくでき、その結果、信頼性を確保しな
がら新たな導体回路を形成できる絶縁樹脂層上の面積を
広くとることができる製造方法を提供することにある。
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an adhesive tape having a plurality of reference holes formed in a core substrate. After covering with the insulating resin layer, the insulating resin layer is formed by covering the reference hole, exposing the reference hole, and then using the exposed reference hole as a positioning reference for forming a conductor circuit. A method for manufacturing a multilayer wiring board in which a conductor circuit is formed on an insulating tape, which can reduce the exudation range of the adhesive component of an adhesive tape, and as a result, can form a new conductor circuit while ensuring reliability. An object of the present invention is to provide a manufacturing method capable of taking a large area on the resin layer.

【0006】[0006]

【課題を解決するための手段】請求項1に係る発明の多
層配線板の製造方法は、複数個の基準穴を設けているコ
ア基板の上に、基準穴を被覆して絶縁樹脂層を形成した
後、基準穴を覆う絶縁樹脂層を除去して基準穴を露出さ
せ、次いでこの露出させた基準穴を導体回路形成のため
の位置決めの基準として用いて、残存する絶縁樹脂層上
に導体回路を形成する積み上げ方式の多層配線板の製造
方法において、絶縁樹脂層を形成する前に、基準穴を包
囲する突起部をコア基板に設けると共に、この突起部で
囲まれる範囲内に収納される接着性テープで基準穴を塞
いでいることを特徴とする。
According to a first aspect of the present invention, there is provided a method for manufacturing a multilayer wiring board, wherein a reference hole is formed on a core substrate having a plurality of reference holes to form an insulating resin layer. After that, the insulating resin layer covering the reference hole is removed to expose the reference hole, and then the exposed reference hole is used as a positioning reference for forming the conductor circuit to form a conductor circuit on the remaining insulating resin layer. In the method for manufacturing a stacked-type multi-layer wiring board for forming a wiring board, a protrusion that surrounds the reference hole is provided on the core substrate before the insulating resin layer is formed, and an adhesive that is housed within a range surrounded by the protrusion is It is characterized in that the reference hole is closed with a sex tape.

【0007】請求項2に係る発明の多層配線板の製造方
法は、複数個の基準穴を設けているコア基板の上に、基
準穴を被覆して絶縁樹脂層を形成した後、基準穴を覆う
絶縁樹脂層を除去して基準穴を露出させ、次いでこの露
出させた基準穴を導体回路形成のための位置決めの基準
として用いて、残存する絶縁樹脂層上に導体回路を形成
する積み上げ方式の多層配線板の製造方法において、絶
縁樹脂層を形成する前に、基準穴をコア基板の端縁とで
包囲する突起部をコア基板に設けると共に、コア基板の
端縁と突起部で囲まれる範囲内に収納される接着性テー
プで基準穴を塞いでいることを特徴とする。
According to a second aspect of the present invention, there is provided a method of manufacturing a multilayer wiring board, wherein a reference hole is formed on a core substrate having a plurality of reference holes by covering the reference holes with an insulating resin layer. The stacked insulating resin layer is removed to expose the reference hole, and the exposed reference hole is used as a positioning reference for forming a conductor circuit to form a conductor circuit on the remaining insulating resin layer. In the method for manufacturing a multilayer wiring board, a protrusion that surrounds the reference hole with the edge of the core substrate is provided on the core substrate before forming the insulating resin layer, and a range surrounded by the edge and the protrusion of the core substrate. It is characterized in that the reference hole is closed with an adhesive tape housed inside.

【0008】[0008]

【発明の実施の形態】請求項1に係る発明の実施の形態
を図面を参照して説明する。図1は実施の形態を説明す
るための平面図であり、図2は断面図である。図2
(a)に示すように、コア基板2に対し導体回路1及び
基準穴3と共に、基準穴3を包囲する突起部11を設け
る。この突起部11は図1に示すように基準穴3の周囲
に基準穴3を包囲するように設けるが、突起部11の形
成方法については特に限定はなく、例えば、コア基板2
の表面に金属箔を備えておき、この金属箔をエッチング
して突起部11を形成する等の方法で行えばよい。コア
基板2としては、例えば、銅箔が表面に接着されている
ガラス布基材エポキシ樹脂積層板等が使用できるが、導
体回路1を形成していない単なる絶縁基板を使用するこ
ともできる。基準穴3の個数については2個以上であれ
ばよく、必要な個数を設けて差し支えない。次いで、基
準穴3を接着性のテープ4を用いて塞ぐが、図2(b)
に示すように、テープ4は突起部11で囲まれる範囲内
に収納されるように接着する。次いで、図2(c)に示
すように、基準穴3を被覆して絶縁樹脂層5を形成し、
次いで、図2(d)に示すように、例えばナイフ等を用
いて基準穴3の上の絶縁樹脂層5及びテープ4を除去し
て基準穴3を露出させ、次いでこの露出させた基準穴3
を導体回路形成のための位置決めの基準として用いて、
絶縁樹脂層5上に新たな導体回路を形成する。このよう
に、図1及び図2に示す実施の形態では、突起部11で
囲まれる範囲内にテープ4は収納されるので、絶縁樹脂
層5を形成する際に、接着性のテープ4の接着剤成分が
周囲に染み出しても、突起部11で囲まれる範囲内で止
まり、突起部11で囲まれる範囲の外に接着剤成分が広
がることがない。従って、接着剤成分が染み出す範囲が
狭い範囲(突起部11で囲まれる範囲)のみとなり、絶
縁樹脂層5の膜厚が不均一となるという問題や、絶縁樹
脂層5が剥離しやすくなるという問題が生じる面積を小
さくできる。そのため、信頼性を確保しながら新たな導
体回路を形成できる絶縁樹脂層上の面積を広くとること
ができるようになる。すなわち、導体回路を形成可能な
有効面積を広げることが可能となる。
DETAILED DESCRIPTION OF THE INVENTION An embodiment of the invention according to claim 1 will be described with reference to the drawings. FIG. 1 is a plan view for explaining the embodiment, and FIG. 2 is a sectional view. FIG.
As shown in (a), the core substrate 2 is provided with the conductor circuit 1 and the reference hole 3, and the protrusion 11 surrounding the reference hole 3. The protrusion 11 is provided around the reference hole 3 so as to surround the reference hole 3 as shown in FIG. 1. However, the method of forming the protrusion 11 is not particularly limited.
A metal foil may be provided on the surface of, and the projection 11 may be formed by etching the metal foil. As the core substrate 2, for example, a glass cloth base material epoxy resin laminated plate having a copper foil adhered to its surface can be used, but a simple insulating substrate on which the conductor circuit 1 is not formed can also be used. The number of reference holes 3 may be two or more, and the necessary number may be provided. Then, the reference hole 3 is closed with an adhesive tape 4, as shown in FIG.
As shown in, the tape 4 is adhered so that it is housed within the range surrounded by the protrusion 11. Next, as shown in FIG. 2C, the reference hole 3 is covered to form the insulating resin layer 5,
Then, as shown in FIG. 2D, the insulating resin layer 5 and the tape 4 on the reference hole 3 are removed by using, for example, a knife to expose the reference hole 3, and then the exposed reference hole 3
Is used as a positioning reference for forming a conductor circuit,
A new conductor circuit is formed on the insulating resin layer 5. As described above, in the embodiment shown in FIGS. 1 and 2, since the tape 4 is housed within the range surrounded by the protrusions 11, the adhesive tape 4 is adhered when the insulating resin layer 5 is formed. Even if the agent component oozes out to the surroundings, it stops within the range surrounded by the protrusions 11 and the adhesive component does not spread outside the range surrounded by the protrusions 11. Therefore, the range in which the adhesive component exudes is only a narrow range (the range surrounded by the protrusions 11), and the problem that the film thickness of the insulating resin layer 5 becomes uneven and the insulating resin layer 5 easily peels The area where problems occur can be reduced. Therefore, it is possible to increase the area on the insulating resin layer where a new conductor circuit can be formed while ensuring reliability. That is, it is possible to increase the effective area in which the conductor circuit can be formed.

【0009】次に、請求項2に係る発明の実施の形態を
図面を参照して説明する。図3は実施の形態を説明する
ための平面図である。図3に示すように、コア基板2に
対し導体回路1及び基準穴3と共に、基準穴3をコア基
板2の端縁12とで包囲する突起部11をコア基板2に
設ける。突起部11の形成方法や、使用するコア基板2
については、前記の請求項1に係る発明の実施の形態の
場合と同様である。次いで、基準穴3を接着性のテープ
を用いて塞ぐが、この接着性のテープはコア基板2の端
縁12と突起部11で囲まれる範囲内に収納されるよう
に接着する。以降の工程は前記の請求項1に係る発明の
実施の形態の場合と同様である。このように、この実施
の形態では、コア基板2の端縁12と突起部11で囲ま
れる範囲内にテープは収納されるので、絶縁樹脂層を形
成する際に、接着性のテープの接着剤成分が周囲に染み
出しても、端縁12と突起部11で囲まれる範囲内で止
まり、それ以上の範囲に接着剤成分が広がることがな
い。従って、接着剤成分が染み出す範囲が狭い範囲(端
縁12と突起部11で囲まれる範囲)のみとなり、新た
な導体回路を形成する位置の絶縁樹脂層5の膜厚が不均
一となるという問題や、新たな導体回路を形成する位置
の絶縁樹脂層5が剥離しやすくなるという問題が生じる
面積を小さくできる。そのため、信頼性を確保しながら
新たな導体回路を形成できる絶縁樹脂層上の面積を広く
とることができるようになる。すなわち、導体回路を形
成可能な有効面積を広げることが可能となる。
Next, an embodiment of the invention according to claim 2 will be described with reference to the drawings. FIG. 3 is a plan view for explaining the embodiment. As shown in FIG. 3, the core circuit board 2 is provided with the conductor circuit 1 and the reference hole 3, and the projecting portion 11 that surrounds the reference hole 3 with the edge 12 of the core circuit board 2. Method of forming protrusion 11 and core substrate 2 used
Is the same as that of the embodiment of the invention according to claim 1. Next, the reference hole 3 is closed with an adhesive tape, and the adhesive tape is adhered so as to be housed within the range surrounded by the edge 12 of the core substrate 2 and the protrusion 11. The subsequent steps are the same as those in the embodiment of the invention according to claim 1. As described above, in this embodiment, since the tape is accommodated within the range surrounded by the edge 12 of the core substrate 2 and the protrusion 11, the adhesive of the adhesive tape is used when the insulating resin layer is formed. Even if the component exudes to the surroundings, it stops within the range surrounded by the edge 12 and the protrusion 11, and the adhesive component does not spread in the range beyond that. Therefore, the range in which the adhesive component exudes is only a narrow range (the range surrounded by the edge 12 and the protrusion 11), and the film thickness of the insulating resin layer 5 at the position where a new conductor circuit is formed becomes uneven. It is possible to reduce an area in which a problem or a problem that the insulating resin layer 5 at a position where a new conductor circuit is formed is easily separated is generated. Therefore, it is possible to increase the area on the insulating resin layer where a new conductor circuit can be formed while ensuring reliability. That is, it is possible to increase the effective area in which the conductor circuit can be formed.

【0010】[0010]

【発明の効果】請求項1に係る発明の多層プリント配線
板の製造方法では、絶縁樹脂層を形成する前に、基準穴
を包囲する突起部をコア基板に設けると共に、この突起
部で囲まれる範囲内に収納される接着性テープで基準穴
を塞いでいるために、接着性のテープの接着剤成分の染
み出す範囲を小さくでき、その結果、信頼性を確保しな
がら新たな導体回路を形成できる絶縁樹脂層上の面積を
広くとることが可能となる。
In the method for manufacturing a multilayer printed wiring board according to the first aspect of the present invention, the projecting portion surrounding the reference hole is provided on the core substrate and is surrounded by the projecting portion before the insulating resin layer is formed. Since the reference hole is closed with the adhesive tape that is stored within the range, the area where the adhesive component of the adhesive tape leaks out can be reduced, and as a result, a new conductor circuit is formed while ensuring reliability. It is possible to increase the area of the insulating resin layer that can be formed.

【0011】請求項2に係る発明の多層プリント配線板
の製造方法では、絶縁樹脂層を形成する前に、基準穴を
コア基板の端縁とで包囲する突起部をコア基板に設ける
と共に、コア基板の端縁と突起部で囲まれる範囲内に収
納される接着性テープで基準穴を塞いでいるために、接
着性のテープの接着剤成分の染み出す範囲を小さくで
き、その結果、信頼性を確保しながら新たな導体回路を
形成できる絶縁樹脂層上の面積を広くとることが可能と
なる。
In the method for manufacturing a multilayer printed wiring board according to the second aspect of the present invention, before forming the insulating resin layer, the core board is provided with a protrusion that surrounds the reference hole with the end edge of the core board. Since the reference hole is closed by the adhesive tape that is stored within the area surrounded by the edge of the board and the protrusion, the area where the adhesive component of the adhesive tape exudes can be reduced, resulting in reliability. It is possible to secure a large area on the insulating resin layer where a new conductor circuit can be formed.

【図面の簡単な説明】[Brief description of drawings]

【図1】請求項1に係る発明の多層配線板の製造方法の
実施の形態を説明する平面図である。
FIG. 1 is a plan view illustrating an embodiment of a method for manufacturing a multilayer wiring board according to the first aspect of the invention.

【図2】請求項1に係る発明の多層配線板の製造方法の
実施の形態を説明する断面図である。
FIG. 2 is a cross-sectional view illustrating an embodiment of a method for manufacturing a multilayer wiring board according to the first aspect of the invention.

【図3】請求項2に係る発明の多層配線板の製造方法の
実施の形態を説明する平面図である。
FIG. 3 is a plan view illustrating an embodiment of a method for manufacturing a multilayer wiring board according to the second aspect of the invention.

【図4】従来の多層配線板の製造方法を説明する断面図
である。
FIG. 4 is a cross-sectional view illustrating a conventional method for manufacturing a multilayer wiring board.

【符号の説明】[Explanation of symbols]

1 導体回路 2 コア基板 3 基準穴 4 テープ 5 絶縁樹脂層 11 突起部 12 端縁 1 Conductor Circuit 2 Core Board 3 Reference Hole 4 Tape 5 Insulating Resin Layer 11 Protrusion 12 Edge

フロントページの続き (72)発明者 吉岡 慎悟 大阪府門真市大字門真1048番地松下電工株 式会社内 (72)発明者 斉藤 英一郎 大阪府門真市大字門真1048番地松下電工株 式会社内 (72)発明者 池谷 晋一 大阪府門真市大字門真1048番地松下電工株 式会社内 (72)発明者 藤原 弘明 大阪府門真市大字門真1048番地松下電工株 式会社内 (72)発明者 伊藤 克彦 大阪府門真市大字門真1048番地松下電工株 式会社内Front page continuation (72) Inventor Shingo Yoshioka 1048 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Works Ltd. (72) Inventor Eiichiro Saito 1048, Kadoma, Kadoma City, Osaka Matsushita Electric Works Ltd. (72) Invention Person Shinichi Iketani 1048 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Works Co., Ltd. (72) Inventor Hiroaki Fujiwara 1048 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Works Co., Ltd. (72) Inventor, Katsuhiko Ito Kadoma City, Osaka Prefecture 1048 Kadoma Matsushita Electric Works Co., Ltd.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 複数個の基準穴を設けているコア基板の
上に、基準穴を被覆して絶縁樹脂層を形成した後、基準
穴を覆う絶縁樹脂層を除去して基準穴を露出させ、次い
でこの露出させた基準穴を導体回路形成のための位置決
めの基準として用いて、残存する絶縁樹脂層上に導体回
路を形成する積み上げ方式の多層配線板の製造方法にお
いて、絶縁樹脂層を形成する前に、基準穴を包囲する突
起部をコア基板に設けると共に、この突起部で囲まれる
範囲内に収納される接着性テープで基準穴を塞いでいる
ことを特徴とする多層配線板の製造方法。
1. A core substrate having a plurality of reference holes formed thereon, the reference holes being covered to form an insulating resin layer, and the insulating resin layer covering the reference holes being removed to expose the reference holes. Then, using the exposed reference hole as a positioning reference for forming the conductor circuit, in the method for manufacturing a stacked-type multilayer wiring board in which the conductor circuit is formed on the remaining insulating resin layer, the insulating resin layer is formed. Prior to manufacturing, a multilayer wiring board characterized in that a protrusion surrounding the reference hole is provided on the core substrate, and the reference hole is closed with an adhesive tape accommodated in the area surrounded by the protrusion. Method.
【請求項2】 複数個の基準穴を設けているコア基板の
上に、基準穴を被覆して絶縁樹脂層を形成した後、基準
穴を覆う絶縁樹脂層を除去して基準穴を露出させ、次い
でこの露出させた基準穴を導体回路形成のための位置決
めの基準として用いて、残存する絶縁樹脂層上に導体回
路を形成する積み上げ方式の多層配線板の製造方法にお
いて、絶縁樹脂層を形成する前に、基準穴をコア基板の
端縁とで包囲する突起部をコア基板に設けると共に、コ
ア基板の端縁と突起部で囲まれる範囲内に収納される接
着性テープで基準穴を塞いでいることを特徴とする多層
配線板の製造方法。
2. A core substrate having a plurality of reference holes formed thereon, the reference holes being covered to form an insulating resin layer, and the insulating resin layer covering the reference holes being removed to expose the reference holes. Then, using the exposed reference hole as a positioning reference for forming the conductor circuit, in the method for manufacturing a stacked-type multilayer wiring board in which the conductor circuit is formed on the remaining insulating resin layer, the insulating resin layer is formed. Before, the protrusion is formed on the core substrate so as to surround the reference hole with the edge of the core substrate, and the reference hole is closed with the adhesive tape housed within the range surrounded by the edge of the core substrate and the protrusion. A method for manufacturing a multilayer wiring board, characterized in that
JP13672996A 1996-05-30 1996-05-30 Manufacture of multilayer wiring board Pending JPH09321429A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13672996A JPH09321429A (en) 1996-05-30 1996-05-30 Manufacture of multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13672996A JPH09321429A (en) 1996-05-30 1996-05-30 Manufacture of multilayer wiring board

Publications (1)

Publication Number Publication Date
JPH09321429A true JPH09321429A (en) 1997-12-12

Family

ID=15182145

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13672996A Pending JPH09321429A (en) 1996-05-30 1996-05-30 Manufacture of multilayer wiring board

Country Status (1)

Country Link
JP (1) JPH09321429A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006237088A (en) * 2005-02-22 2006-09-07 Sumitomo Metal Electronics Devices Inc Method of manufacturing multilayer printed wiring board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006237088A (en) * 2005-02-22 2006-09-07 Sumitomo Metal Electronics Devices Inc Method of manufacturing multilayer printed wiring board

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