JPH09321159A - Bic mos integrated circuit device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid increasing the contact resistance due to reduction of the element size and increasing the parasitic resistance of a bipolar transistor due to reduction of the element size. SOLUTION: An NMOS transistor 114 comprises a gate oxide film 11 on a P well region 105 and gate electrode 16 on this film 11. A source/drain region 18 is formed through the gate electrode 16. A PMOS transistor 115 comprises a gate oxide film 11 on an epitaxial layer 104 and source/drain region 19 formed through the gate electrode 16 on the oxide film 11. A bipolar transistor 113 comprises a collector electrode pickup region 31 extending from the epitaxial layer 104 surface to a buried n-type layer 102 and base electrode pickup region 32 formed through an oxide film 107, thus forming them on the same substrate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a BiCMOS integrated circuit device in which a bipolar transistor and a CMOS transistor, which are required to be miniaturized, are formed on the same substrate and a manufacturing method thereof.

[0002]

12 to 20 are sectional views showing a method of manufacturing a conventional BiCMOS integrated circuit device in the order of steps. As shown in FIG. 12, a partially high-concentration N-type layer 20 is formed as a buried layer in a P-type silicon substrate 201 having a plane orientation (100).
2 and a P-type layer 203 are provided. Subsequently, an N type epitaxial layer 204 is grown on the silicon substrate 201 by the vapor phase growth method.

The P-type silicon substrate 201 has an impurity concentration of 4 × 10 ¹⁵ cm ⁻³ and a high concentration of the N-type layer 202 has an impurity concentration of 5 × 10 ¹⁹ c.
m ⁻³ . The concentration of the P-type layer 203 is 1 × 10 ¹⁷
cm ^-3 . Further, the epitaxial layer 204 has a phosphorus concentration of 1 × 10 ¹⁶ cm ⁻³ and a thickness of about 1.0 μm.

Next, the surface of the silicon substrate 201 is set to 100 nm.
After approximately oxidizing to form the oxide film 251, ion implantation for forming the P well region 205 necessary for forming the CMOS transistor is performed. The ion implantation conditions are ¹¹ B ⁺ , an acceleration voltage of 100 keV, and a dose of 2.0 × 10 ¹³ cm ^-2 .

Next, as shown in FIG. 13, a silicon substrate
201 After removing the oxide film (251) on the surface,
An element formation region 206 is provided by the OS method. In the process up to this point, the silicon nitride film is patterned by the selective oxidation method for forming the field oxide film 207. Here, the P well region 205 is also self-aligned with boron using the silicon nitride film as a mask. Is ion-implanted. The ion implantation conditions are ¹¹ B ⁺ , an acceleration voltage of 100 keV, and a dose of 4 × 10 ¹³ cm ^-2 . Similarly, phosphorus is ion-implanted into the N-well region in a self-aligned manner using the silicon nitride film as a mask. The ion implantation conditions here are ³¹ P
⁺ , 100 keV, 4 × 10 ¹³ cm ⁻² .

Further, after the field region is selectively oxidized, the collector electrode extraction region portion 20 of the bipolar transistor is formed.
In order to form 8, phosphorus ion implantation is performed under the conditions of 50 keV and 5 × 10 ¹⁵ cm ⁻² .

Next, as shown in FIG. 14, an oxide film 252 of about 15 nm is formed in the element forming region. After that, ion implantation for determining the threshold value is performed in the channel regions of the P-channel MOS transistor and the N-channel MOS transistor (231, 232). After that, N
The channel MOS transistor is an NMOS transistor,
The P-channel MOS transistor is called a PMOS transistor.

Next, as shown in FIG. 15, after the oxide film 252 formed on the element region is removed, an oxide film 209 of 8 nm is formed again. Then, a polycrystalline silicon film 210 containing no impurities is deposited on the entire surface of the substrate to have a thickness of about 350 nm.

Next, as shown in FIG. 16, after phosphorus is added to the polycrystalline silicon film 210 by a vapor phase diffusion method, the polycrystalline silicon film 210 is anisotropically ion-etched by a gate electrode of a CMOS transistor. Remove the part that becomes 211. Next, in order to form well-known LDD structures 212 and 213 that are often used in CMOS transistors, patterning with photoresist and ion implantation are performed on the NMOS transistor 214 and the PMOS transistor 215, respectively.

Then, for the purpose of recovering damage to the silicon substrate caused in the element region by ion implantation for forming the LDD structure, oxidation is performed at 800 ° C. for 15 minutes in a dry oxygen atmosphere.

Next, as shown in FIG. 17, a silicon nitride film (216) having a thickness of 50 nm is formed on the entire surface of the semiconductor substrate by the CVD method.
Deposit to a degree. Then, when the entire main surface of the semiconductor substrate is etched by the anisotropic ion etching method, a side wall 216 of a silicon nitride film is formed on the side wall of the gate electrode 211 formed of a polycrystalline silicon film. CMO at the same time
Since the source / drain portions of the S transistor and the silicon substrate surface in the element region of the bipolar transistor are exposed, oxidation is performed for 30 minutes in a dry oxygen atmosphere at 850 ° C.

Next, as shown in FIG. 18, a photoresist pattern having openings in the base electrode region 217 of the bipolar transistor and the PMOS transistor region is formed,
Ion implantation of boron fluoride is performed. An example of ion implantation conditions at this time is ¹¹ BF ₂ ⁺ , acceleration voltage 3
It is 0 keV and the dose amount is 3 × 10 ¹⁵ cm ⁻² . Accordingly, the source / drain region 218 of the PMOS transistor is
Can be.

Further, similarly, a photoresist pattern having an opening in the NMOS transistor region is formed and arsenic ion implantation is performed. As an example of ion implantation conditions, ⁷⁵ As ⁺ , accelerating voltage 60 keV, dose 5 × 10
¹⁵ cm ^-2 . As a result, the source / drain regions 219 of the NMOS transistor are formed.

Next, as shown in FIG. 19, an acceleration voltage of 20 ke is used as a base region 220 of the bipolar transistor.
After implanting boron ions under the conditions of V and a dose of 2 × 10 ¹³ cm ^-2 , a silicon oxide film 22 is formed on the entire surface of the substrate.
1 is deposited to about 100 nm. Then, an emitter diffusion window 222 is opened in the emitter portion of the bipolar transistor. Polycrystalline silicon film on the entire surface of semiconductor substrate (223)
Is deposited, and the polycrystalline silicon film is removed by an isotropic etching method except for the portions to be the emitter diffusion source and the emitter electrode. Arsenic ion implantation is performed on the entire surface of the semiconductor substrate with an acceleration voltage of 40 keV and a dose of 1 × 10 ¹⁶ cm ^-2.
Under the following conditions.

Next, as shown in FIG. 20, a silicon oxide film (interlayer insulating film) 22 serving as a protective film is formed on the entire surface of the semiconductor substrate.
After depositing 4, perform halogen lamp heat treatment at 1000 ° C. for 20 seconds in a nitrogen atmosphere to electrically activate the impurities implanted into the source / drain electrode, the base electrode, the emitter, and the gate electrode. (Including formation of emitter region 226). Next, a contact hole is formed by a generally well-known method, and a wiring metal 225 is attached / worked.

The above structure has the following problems. (1) The contact resistance between the wiring material and the device electrode rises with the miniaturization of the device size, particularly with the reduction of the contact opening diameter. Therefore, the improvement in device performance due to miniaturization is reduced. (2) Not only in CMOS but also in bipolar transistors, the parasitic resistance of the element itself increases with the miniaturization of the element size.

[0017]

SUMMARY OF THE INVENTION In consideration of the above circumstances, the present invention provides a BiCMOS integrated circuit device in which an increase in contact resistance due to miniaturization of element size and an increase in parasitic resistance due to miniaturization of element size of a bipolar transistor. It is an object of the present invention to provide a BiCMOS integrated circuit device and a method of manufacturing the same for preventing it.

[0018]

According to the present invention, in a BiCMOS integrated circuit device in which a bipolar transistor and a CMOS transistor are formed on the same substrate, the CM
Regarding the OS transistor, each source / drain region in which the connectable surface of the wiring metal has a silicide structure,
The bipolar transistor is characterized by comprising an emitter electrode of polycrystalline silicon or a polycrystalline silicon silicide structure, and a base / collector region having a silicide structure on a surface capable of connecting a wiring metal.

In the present invention, a bipolar transistor and a C
BiCM in which MOS transistors are formed on the same substrate
In the method for manufacturing an OS integrated circuit device, the step of simultaneously forming the emitter electrode of the bipolar transistor and each gate electrode of the CMOS transistor, and the CM.
A salicide step of simultaneously silicidizing at least each source / drain region of the OS transistor and a connectable surface of the wiring metal in the base / collector region of the bipolar transistor, and thermal diffusion of impurities from the emitter electrode to the emitter region of the bipolar transistor. And a step of forming by.

According to the present invention, an increase in contact resistance due to miniaturization is prevented by silicidation. Necessary part silicidation is performed in self-alignment for bipolar and CMOS transistors.
Silicide) structure is applied.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1A is a pattern plan view of an essential part showing a configuration of a BiCMOS integrated circuit device according to an embodiment of the present invention, and FIG. 1B is a 1A of FIG. 1A. -1
It is sectional drawing which followed the A line.

A high-concentration N-type layer 102 and a P-type layer 103 are provided as buried layers in a P-type silicon substrate 101.
An N type epitaxial layer 10 is formed on the silicon substrate 101.
4 is formed, and a P well region 105 is formed in the region of the epitaxial layer on the P type layer 103. A bipolar transistor 113 and an N-channel MOS transistor are formed in the element formation regions divided by the field oxide film 107, respectively.
114 and a P channel MOS transistor 115. After that, the N-channel MOS transistor is an NMOS
Transistors and P-channel MOS transistors are PMO
It is called an S transistor.

In the NMOS transistor 114, the gate oxide film 11 is formed on the surface of the P well region 105, and the gate electrode 16 is formed on the gate oxide film 11 with the insulating side wall 22. Source / drain regions 18 are formed on the surface of the P well region 105 with the gate electrode 16 interposed therebetween. The upper surface of the gate electrode 16 and the surface of the source / drain region 18 are silicided.

The above-mentioned surface of the silicided source / drain region 18 is a surface to which the source / drain wiring metal can be connected, that is, the gate electrode 16 and the side wall 22 with the side wall 22 on the surface of the element formation region. The entire surface of the source / drain region which is not covered (FIG. 1
(Refer to the hatched part in (a) 18).

In the PMOS transistor 115, the gate oxide film 11 is formed on the surface of the epitaxial layer 104, and the gate electrode 16 is formed on the gate oxide film 11 along with the side wall 22. Source / drain regions 19 are formed on the surface of the epitaxial layer 104 across the gate electrode 16. The upper surface of the gate electrode 16 and the surface of the source / drain region 19 are silicided.

The surface of the silicidized source / drain region 19 mentioned above is a surface to which the source / drain wiring metal can be connected, that is, the gate electrode 16 and the side wall 22 with the side wall 22 on the surface of the element formation region. The entire surface of the source / drain region which is not covered (FIG. 1
(Refer to the hatched line in (a) 19).

In the bipolar transistor 113, a collector electrode extraction region 31 reaching the buried N-type layer 102 from the surface of the epitaxial layer 104 is formed, and a base region and a base electrode extraction region 32 are formed on the surface of the epitaxial layer 104 with an oxide film 107 interposed therebetween. Has been done. An emitter electrode 33 is formed at a predetermined position on the base region. The emitter electrode 33 is an emitter diffusion source, and the emitter part is an oxide film.
An emitter diffusion window 13 is opened in 11a, and is formed by diffusing impurities from the emitter electrode 33 into the base region through this window (33a). A side wall 22 is formed on the emitter electrode 33. Collector electrode extraction area 3
1, the surface of the base electrode extraction region 32 and the upper surface of the emitter electrode 33 are silicidized.

The above-mentioned surfaces of the silicided collector electrode lead-out region 31 and the base electrode lead-out region 32 are surfaces to which the collector / base wiring metal can be connected, that is, the sidewalls 22 on the surface of the element forming region.
Is the entire surface of the collector / base region which is not covered with the emitter electrode 33 and the oxide film 107 (see 31 and 32 shown by hatching in FIG. 1A).

Wiring metal 12 for the gate, source / drain of each of the MOS transistors 114 and 115, and the base, emitter, and collector of the bipolar transistor 113.
Reference numeral 5 is connected to each connectable surface that is silicidized through each contact hole 123 opened in the silicon oxide film (interlayer insulating film) 124.

According to the above structure, the gate metal, the source / drain of the MOS transistor and the wiring metal of the base, emitter and collector of the bipolar transistor are connected to the silicided surface, so that the contact resistance is significantly reduced. In particular, each contact is fine in such a fine integrated dimension that the finished dimension GD of the gate of the MOS transistor is 0.25 μm or less, and this silicidized structure greatly contributes to the reduction of the resistance of the wiring contact.

Further, especially in a bipolar transistor, the parasitic resistance related to the base is significantly reduced. So,
In the bipolar transistor, increase in parasitic resistance due to miniaturization can be prevented.

Moreover, the gate and source / drain of the MOS transistor and the base of the bipolar transistor,
The salicide of the emitter and collector is performed at the same time, and is characterized by a salicide structure. The manufacturing method will be described below.

2 to 11 show a BiCMOS according to the present invention.
FIG. 9 is a cross-sectional view showing the method of manufacturing the integrated circuit device in the order of steps.
As shown in FIG. 2, an N-type layer 10 of a high concentration is partially formed as a buried layer in a P-type silicon substrate 101 having a plane orientation (100).
2 and a P-type layer 103 are provided. Subsequently, an N type epitaxial layer 104 is grown on the silicon substrate 101 by the vapor phase growth method.

The P type silicon substrate 101 has an impurity concentration of 4 × 10 ¹⁵ cm ⁻³ and a high concentration of the N type layer 10.
The concentration of 2 is 5 × 10 ¹⁹ cm ⁻³ with antimony as an impurity.
It is a degree. The concentration of the P-type layer is about 1 × 10 ¹⁷ cm ^-3 . Further, the epitaxial layer has a concentration of 1 × 10 ¹⁶ cm ⁻³ with phosphorus added and has a thickness of about 1.0 μm.

Next, the surface of the silicon substrate 101 is set to 100 nm.
Oxidation is performed to some extent (oxide film 151), and then ion implantation for forming a P well region 105 necessary for forming a CMOS transistor is performed. The ion implantation conditions are ¹¹ B ⁺ , an acceleration voltage of 100 keV, and a dose of 2.0 × 10 ¹³ cm ^-2 .

Next, as shown in FIG. 3, after the oxide film (151) on the surface of the substrate is removed, an element forming region 106 is formed by a generally known LOCOS method. In the process of reaching here,
A silicon nitride film (not shown) is patterned due to the selective oxidation of the field region (field oxide film 107). Here, boron ions are also self-aligned in the P well region 105 using the silicon nitride film as a mask. To do. The implantation conditions are ¹¹ B ⁺ , accelerating voltage 100 keV,
The dose amount is 4 × 10 ¹³ cm ^-2 . Further, also in the N well region, phosphorus is ion-implanted in a self-aligned manner using the silicon nitride film as a mask. Ion implantation conditions here are ³¹
P ⁺ , 100 keV, 4 × 10 ¹³ cm ^-2 .

After selectively oxidizing the field region,
Collector electrode extraction area of bipolar transistor 31
In order to form the film, phosphorus ion implantation is performed under the conditions of 50 keV and 5 × 10 ¹⁵ cm ⁻² .

Next, as shown in FIG. 4, an oxide film 152 of about 15 nm is formed in the element formation region. Then PMO
Ion implantation for determining the threshold value is performed in the channel region of each S / NMOS transistor (108, 109).
Ion implantation is then applied to the internal base region of the bipolar transistor (110).

Next, as shown in FIG. 5, after the oxide film 152 formed on the element region is removed, an oxide film 11 of 8 nm is formed again. Then, a polycrystalline silicon film 12 containing no impurities is deposited on the entire surface of the substrate by about 50 nm.
Further, an emitter diffusion window 13 of the bipolar transistor is opened in the polycrystalline silicon film 12. An example of the dimensions of the emitter diffusion window is 1 μm on the long side and 0.5 μ on the short side.
m.

Next, as shown in FIG. 6, a polycrystalline silicon film 14 containing no impurities is deposited on the entire surface of the substrate to a thickness of about 150 nm. Here, the polycrystalline silicon film 14 deposited on the polycrystalline silicon film 12 has a thickness of about 200 nm. Then, a photoresist pattern 171 having an opening in a region of about 3 μm from the periphery of the emitter diffusion window 13 is formed, and phosphorus is added to the polycrystalline silicon film 14 through the opening by an ion implantation method. The conditions of ion implantation here are, for example, an acceleration voltage of 35 keV and a dose amount of 1 × 10 ¹⁶ cm ^-2 .

Next, as shown in FIG. 7, after removing the photoresist (171) formed at the time of the phosphorus ion implantation, the polycrystalline silicon film 14 is subjected to anisotropic ion etching to form a gate electrode of a CMOS transistor. The portion to be 16 and the portion to be the emitter electrode 33 of the bipolar transistor are removed and left. Next, in order to form well-known LDD structures 181, 191, which are often used in CMOS transistors, patterning by photoresist and ion implantation are performed for each of the NMOS transistor 114 and the PMOS transistor 115.

Subsequently, for the purpose of recovering damage to the silicon substrate generated in the element region by ion implantation for forming the LDD structure, oxidation treatment is performed at 800 ° C. for 15 minutes in a dry oxygen atmosphere.

Next, as shown in FIG. 8, a silicon nitride film (22) is deposited on the entire surface of the semiconductor substrate by the CVD method to a thickness of about 50 nm. Then, the entire main surface of the semiconductor substrate is etched by the anisotropic ion etching method, so that the sidewalls 22 of the silicon nitride film are formed on the sidewalls of the emitter electrode 33 and the gate electrode 16 formed of the polycrystalline silicon film.

As a result of the above process, the surface of each source / drain of the CMOS transistor and the collector / base of the bipolar transistor are exposed, and the upper surface of the polycrystalline silicon serving as the emitter electrode and the gate electrode is also a polycrystalline silicon surface. Exposed. Titanium is deposited to a thickness of about 50 nm on the entire surface of the semiconductor substrate including this exposed surface by a sputtering method (titanium film 23).

Next, as shown in FIG. 9, heat treatment using a halogen lamp is performed at 750 ° C. for 30 seconds. Then, by the titanium film 23, each source / drain of the CMOS transistor and the collector / drain of the bipolar transistor are formed.
The exposed surface of the base silicon substrate and the exposed surface of polycrystalline silicon that will become the emitter electrode and gate electrode are silicified (titanium silicide 24).

After that, the titanium film 23 (non-silicided titanium film) remaining on the substrate after the heat treatment is removed by immersing it in a treatment liquid containing sulfuric acid and hydrogen peroxide. Next, heat treatment is performed at 850 ° C. for 30 seconds.

As a result of the above steps, the surfaces of the base, emitter and collector electrodes of the bipolar transistor, and the gate and source / drain electrodes of the MOS transistor are simultaneously silicided in a self-aligned manner, and salicide (Se
lf Aligned Silicide) structure. Such a process is called a salicide process.

Next, as shown in FIG. 10, a photoresist pattern 172 having openings in the emitter / base region of the bipolar transistor and the PMOS transistor region is formed, and boron ion implantation is carried out. As an example of ion implantation conditions, ¹¹ B ⁺ , 30 keV, 3 × 10 ¹⁵ cm
^-2 .

Next, as shown in FIG.
A photoresist pattern 173 having an opening in the S transistor region is formed and arsenic ion implantation is performed. As an example of ion implantation conditions, ⁷⁵ As ⁺ , 60 keV, 5 ×
It is 10 ¹⁵ cm ^-2 .

Next, a silicon oxide film (interlayer insulating film) 124 serving as a protective film is deposited on the entire surface of the semiconductor substrate, and then halogen lamp heat treatment is performed at 900 ° C. for 30 seconds in a nitrogen atmosphere to perform a source / source process. Electrical activation of impurities implanted into the drain electrode, the base electrode, and the emitter / gate electrode is attempted.

As a result, the source / drain regions 19 of the PMOS transistor and the source / drain regions of the NMOS transistor
The drain region 18, the collector electrode extraction region 31, the base electrode extraction region 32, and the emitter region 33a of the bipolar transistor are completed. Next, a silicon oxide film (interlayer insulating film) 124 and a contact hole 123 are formed by a well-known method, and a wiring metal 125 is deposited / processed to obtain the structure shown in FIG.

According to the method of the above structure, the contact resistance can be easily reduced by the salicide structure that has undergone the salicide process. The finished dimension GD of the gate of the CMOS transistor portion in the configuration of FIG. 1 is, for example, 0.25.
In the case of forming an integrated circuit on the order of μm, this salicide structure technology can be expected to have the following effects (1) to (3). (1) The contact resistance with the wiring material can be significantly reduced. (Assuming a contact hole diameter of 0.8 μm) (2) Reduction of base resistance The following table shows a comparison in a region in which a relatively large collector current flows where the contribution of parasitic resistance is large. (3) Performance improvement as a bipolar transistor based on the above (1) and (2) By reducing the parasitic resistance related to the base, it is possible to improve the maximum oscillation frequency fmax by 30% or more. Definition of fmax fmax = (fT / 8πRbC _jc ) ^1/2 (1) fT: Cutoff frequency Rb: Base resistance C _jc : Base / collector junction capacitance According to the above formula (1), Rb and C _jc can be reduced. So
It greatly contributes to the performance improvement of the bipolar transistor.

As a result of the above, even in a BiCMOS integrated circuit having an extremely fine integrated size in which the finish of the gate of the MOS transistor is smaller than 0.25 μm, the performance is greatly expected to be improved by reducing the resistance of the wiring contact and the parasitic resistance. it can.

[0054]

As described above, according to the present invention,
By providing the wiring metal connecting portion with the salicide structure, it is possible to provide a BiCMOS integrated circuit device which is easy to manufacture and prevents an increase in contact resistance due to miniaturization and an increase in parasitic resistance of a bipolar transistor, and a manufacturing method thereof.

[Brief description of drawings]

FIG. 1A is a BiCM according to an embodiment of the present invention.
A plan view of a pattern of an essential part showing a configuration of an OS integrated circuit device,
FIG. 1B is a sectional view taken along the line 1A-1A in FIG.

FIG. 2 is a first cross-sectional view showing a method of manufacturing a BiCMOS integrated circuit device according to the present invention in the order of steps.

FIG. 3 is a second cross-sectional view following FIG. 2 showing a method for manufacturing a BiCMOS integrated circuit device according to the present invention in process order.

FIG. 4 is a third cross-sectional view subsequent to FIG. 3, showing the method of manufacturing the BiCMOS integrated circuit device according to the present invention in the order of steps.

FIG. 5 is a fourth cross-sectional view following FIG. 4, showing the method of manufacturing the BiCMOS integrated circuit device according to the present invention in the order of steps.

FIG. 6 is a fifth cross-sectional view following FIG. 5, showing the method of manufacturing the BiCMOS integrated circuit device according to the present invention in the order of steps.

FIG. 7 is a sixth cross-sectional view following FIG. 6, showing the method of manufacturing the BiCMOS integrated circuit device according to the present invention in the order of steps.

FIG. 8 is a seventh cross-sectional view following FIG. 7, showing the method of manufacturing the BiCMOS integrated circuit device according to the present invention in the order of steps.

FIG. 9 is an eighth cross-sectional view following FIG. 8, showing the method of manufacturing the BiCMOS integrated circuit device according to the present invention in the order of steps.

FIG. 10 is a ninth cross-sectional view following FIG. 9 showing a method for manufacturing a BiCMOS integrated circuit device according to the present invention in the order of steps.

FIG. 11 is a tenth cross-sectional view following FIG. 10 showing a method for manufacturing a BiCMOS integrated circuit device according to the present invention in process order.

FIG. 12 is a first sectional view showing a method of manufacturing a conventional BiCMOS integrated circuit device in the order of steps.

FIG. 13 is a second cross-sectional view following FIG. 12, showing a method of manufacturing a conventional BiCMOS integrated circuit device in the order of steps.

FIG. 14 is a third cross-sectional view following FIG. 13 showing a conventional method for manufacturing a BiCMOS integrated circuit device in the order of steps.

FIG. 15 is a fourth cross-sectional view following FIG. 14 showing a method for manufacturing a conventional BiCMOS integrated circuit device in the order of steps.

FIG. 16 is a fifth cross-sectional view following FIG. 15 showing a method of manufacturing a conventional BiCMOS integrated circuit device in the order of steps.

FIG. 17 is a sixth cross-sectional view following FIG. 16 showing a method of manufacturing a conventional BiCMOS integrated circuit device in the order of steps.

FIG. 18 is a seventh cross-sectional view subsequent to FIG. 17, showing the manufacturing method of the conventional BiCMOS integrated circuit device in the order of steps.

FIG. 19 is an eighth cross-sectional view following FIG. 18 showing the method of manufacturing the conventional BiCMOS integrated circuit device in the order of steps.

FIG. 20 is a ninth cross-sectional view following FIG. 19 showing the method of manufacturing the conventional BiCMOS integrated circuit device in the order of steps.

[Explanation of symbols]

11 ... Gate oxide film 11a, 151, 152 ... Oxide film 12, 14 ... Polycrystalline silicon film 13 ... Emitter diffusion window 171, 172, 173 ... Photoresist pattern 16 ... Gate electrode 18, 19 ... Source / drain region 22 ... Side wall (Silicon nitride film side wall) 23 ... Titanium 31 ... Collector electrode extraction region 32 ... Base electrode extraction region 33 ... Emitter electrode 33a ... Emitter region 101 ... P-type silicon substrate 102 ... N-type layer 103 ... P-type layer 104 ... Epitaxial layer 105 ... P-well region 106 ... Element formation region 108 ... 109 ... 20 ... 107 ... Field oxide film 113 ... Bipolar transistor 114 ... NMOS transistor (N channel MOS transistor) 115 ... PMOS transistor (P channel MOS transistor) 123 ... Contact hole 124 … Silicon oxide film (interlayer insulating film) 125… Wiring metal 151, 152… Oxide film

Claims (6)

[Claims] 1. A BiCMOS integrated circuit device in which a bipolar transistor and a CMOS transistor are formed on the same substrate, wherein each CMOS transistor has a source / drain region in which a connectable surface of a wiring metal has a silicide structure, A bipolar transistor, comprising: an emitter electrode of polycrystalline silicon or a polycrystalline silicon silicide structure; and a base / collector region having a silicide structure on a surface capable of connecting wiring metal.
iCMOS integrated circuit device. 2. A BiCMOS integrated circuit device in which a bipolar transistor and a CMOS transistor are formed on the same substrate, wherein in the CMOS transistor, each source / drain region and an upper surface of which a connectable surface of a wiring metal has a silicide structure are provided. Regarding each of the first and second conductivity type MOS transistors having a gate electrode having a silicide structure, and the bipolar transistor, an emitter electrode of polycrystalline silicon or a polycrystalline silicon silicide structure and a connectable surface of a wiring metal have a silicide structure. BiCMOS integrated circuit device, characterized in that it comprises a bipolar transistor of the first polarity or the second polarity having a base / collector region with a gate length of 0.25 μm or less in each of the MOS transistors. 3. The BiCMOS according to claim 1 or 2.
In the integrated circuit device, the emitter electrode contains phosphorus. 4. A method for manufacturing a BiCMOS integrated circuit device in which a bipolar transistor and a CMOS transistor are formed on the same substrate, wherein an emitter electrode of the bipolar transistor and the CM.
A step of simultaneously forming each gate electrode of an OS transistor; a salicide step of simultaneously silicidizing at least each source / drain region of the CMOS transistor and a connectable surface of a wiring metal in a base / collector region of the bipolar transistor; And a step of forming an emitter region of the bipolar transistor by thermal diffusion of impurities from the emitter electrode. 5. A method for manufacturing a BiCMOS integrated circuit device in which a bipolar transistor and a CMOS transistor are formed on the same substrate, wherein an emitter electrode of the bipolar transistor and the CM are provided.
A step of simultaneously forming each gate electrode of the OS transistor; a connectable surface of the source / drain regions of the CMOS transistor and a wiring metal of a base / collector region of the bipolar transistor; an upper surface of each gate electrode of the CMOS transistor; Manufacture of a BiCMOS integrated circuit device comprising a salicide step of simultaneously siliciding the upper surface of the emitter electrode of the bipolar transistor, and a step of forming an emitter region of the bipolar transistor by thermal diffusion of impurities from the emitter electrode. Method. 6. The BiCMOS according to claim 4 or 5.
In the method of manufacturing an integrated circuit device, each gate length of the CMOS transistor is formed to be 0.25 μm or less, and the emitter electrode of the bipolar transistor contains phosphorus and the emitter region is formed by thermal diffusion of phosphorus. Is characterized by.