JPH09320266A - Dynamic random access memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the consumption of useless current as well as to improve reliability. SOLUTION: A charge pump circuit 59 generates a step-up potential Vpp2 on the second level which a word driver 63 requires. A charge pump circuit 57 generates a step-up potential Vpp1 on the first level which a BLI driver 61 requires. For this reason, there is no need to generate a step-up potential larger than necessary. Accordingly, useless current consumtion is suppressed and in addition, circuit destruction can be prevented, improving the reliability.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic random access memory (hereinafter referred to as "DRAM"), and more particularly to a boosted potential generating circuit.

[0002]

2. Description of the Related Art A conventional semiconductor memory device (pseudo static random access memory, non-volatile semiconductor memory device) is disclosed in, for example, Japanese Patent Laid-Open No. 5-18996.
No. 1 and Japanese Patent Laid-Open No. 1-160059.

FIG. 27 is a schematic block diagram showing a part of a conventional DRAM. Referring to FIG. 27, the conventional DRA
M includes a boosted potential generation circuit including a ring oscillator 205, a detection circuit 207, and a charge pump circuit 209. The detection circuit 207 has a boosted potential node Npp.
When the boosted potential Vpp falls below a predetermined level, the ring oscillator 205 is operated.
Then, charge pump circuit 209 generates boosted potential Vpp at boosted potential node Npp in response to clock signal CLK from ring oscillator 205. On the other hand, the detection circuit 207 stops the operation of the ring oscillator 205 when the potential level of the boosted potential node Npp reaches or exceeds the predetermined level. Therefore, the charge pump circuit 209
Stops generation of boosted potential Vpp to boosted potential node Npp. Boosted potential Vpp generated at boosted potential node Npp by charge pump circuit 209 is supplied to BLI driver 211 and word driver 213. The boosted potential Vpp is at a level higher than the power supply potential Vcc. Next, the reason why the boosted potential Vpp is required for the BLI driver 211 and the word driver 213 will be described.

FIG. 28 is a circuit diagram showing details of a memory cell of a conventional DRAM. Referring to FIG. 28, DRAM
The memory cell is formed of one NMOS transistor 215 and one capacitor 217. NMOS
The gate electrode of the transistor 215 is connected to the word line WL. One source of NMOS transistor 215 /
The drain electrode is connected to the bit line BL. NMOS
The other source / drain electrode of the transistor 215 is connected to one electrode of the capacitor 217. When a P-type semiconductor substrate is used, the substrate potential of the NMOS transistor 215 is often the negative potential Vbb. The other electrode of the capacitor 217 has the cell plate potential Vcp. This cell plate potential Vcp is 1/2 the power supply potential Vcc (1/2 Vcc).

In the memory cell (storage node SN),
A case of writing "H" level data (power supply potential Vcc level data) will be described. Data at the power supply potential Vcc level is transmitted to the bit line BL from a sense amplifier (not shown). It is necessary to transmit the data of the power supply potential Vcc level to the storage node SN without being affected by the threshold voltage Vthm of the NMOS transistor 215. That is, it is necessary to completely turn on the NMOS transistor 215. Therefore, the potential of the word line WL is Vcc + Vthm
The boosted potential Vpp described above is required. The word driver 213 is a circuit for supplying the boosted potential Vpp satisfying such requirements to the word line WL by using the boosted potential potential node Npp as a power supply.

FIG. 29 is a schematic block diagram showing another part of a conventional DRAM. In FIG. 29, the shared sense amplifier system is adopted. This is adopted to reduce the layout area of the sense amplifier. Each of the memory array blocks B1 and B2 includes a plurality of bit line pairs BLL, / BLL, BLR, / BLR and a plurality of memory cells (not shown). Each of the sense amplifier rows 25 and 27 amplifies the potential difference between the bit line pair. The memory array block B1 and the memory array block B2 share the sense amplifier row 25. Here, when the memory array block B2 is selected,
Turn off the NMOS transistors 29 and 31, and turn on the NMOS
The transistors 33 to 39 are turned on. Then, the memory array block B2 uses the sense amplifier rows 25 and 27. In this case, for example, "H" for writing or rewriting, which is amplified by the sense amplifier row 25, is used.
Level data (power supply potential Vcc level data)
It is necessary to transmit to the bit line BLR without being affected by the threshold voltage Vthb of the NMOS transistor 35. Therefore, the potential of the bit line separation line BLI0R connected to the gate electrode of the NMOS transistor 35 is Vc
It is required that the boosted potential Vpp is not less than c + Vthb. Note that this means that the bit line separation line BLI0
The same applies to L and BLI1L. B
The LI driver 211 uses the boosted potential node Npp as a power source to generate such bit line isolation lines BLI0L and BLI0.
This is a circuit for supplying the boosted potential Vpp to R and BLI1L.

[0007]

As described above, in the conventional DRAM, the boosted potential Vpp (bit line separation lines BLI0L, BLI0) supplied to the BLI driver 211 is used.
The boosted potential Vpp supplied to R and BLI1L) and the boosted potential Vpp supplied to the word driver 213 (boosted potential Vpp supplied to the word line WL) are supplied from one charge pump circuit 209. Thus, from one charge pump circuit to two types of drivers (BLI
Problems in the case where the boosted potential Vpp is supplied to the driver and the word driver) will be described.

FIG. 30 is a circuit diagram showing details of a memory cell used for explaining the first problem of the conventional DRAM. The same parts as those in FIG. 28 are designated by the same reference numerals and the description thereof will be omitted as appropriate.

Referring to FIG. 30, the operation of writing "H" level data (power supply potential Vcc level data) into a memory cell will be described. Data at the power supply potential Vcc level is transmitted to the bit line BL from a sense amplifier (not shown). Next, consider a case where word line WL is activated (set to “H” level) and data of power supply potential Vcc level is written to storage node SN of capacitor 217. When the bit line BL (source S of the NMOS transistor 215) reaches the power supply potential Vcc level, the substrate potential Vbb is given to the NMOS transistor 215, and therefore | V is provided between the source S and the substrate.
bb-Vcc | large back gate potential Vb
s occurs. Generally, the threshold voltage Vphm of the NMOS transistor 215 of the memory cell is the threshold of the NMOS transistor used in circuits other than the memory cell such as peripheral circuits in order to reduce the subthreshold leakage current and improve the refresh characteristic. It is higher than the value voltage. In addition to this situation, in the memory cell,
When the potential of the source S of the NMOS transistor 215 rises and the back gate potential Vbs increases, the threshold voltage Vth of the NMOS transistor 215 of the memory cell is increased.
m will be further increased.

FIG. 31 shows the back gate potential Vbs used for explaining the first problem of the conventional DRAM and the threshold voltage V of the NMOS transistor used for the memory cell.
It is a figure which shows the relationship with thm. The horizontal axis represents the back gate potential Vbs, and the vertical axis represents the threshold voltage Vthm.

Referring to FIG. 31, back gate potential Vb
When s is | Vbb |, the threshold voltage is Vth.
It becomes m1. On the other hand, the NMOS transistor 21 of FIG.
When the source S of 5 becomes the power supply potential Vcc (power supply potential Vcc
Since the back gate potential becomes | Vbb-Vcc | (when writing cc level data), the threshold voltage of the NMOS transistor 215 in FIG. 30 becomes Vthm2. In other words, when data of power supply potential Vcc level is written to the memory cell, the threshold voltage becomes higher by ΔVthm than when data of ground potential GND level is written.

On the other hand, as shown in FIG. 29, N connected to bit line isolation lines BLI0L, BLI0R, BLI1L.
The MOS transistors 29 to 39 are normal peripheral NMs.
OS transistor. Therefore, the threshold voltage Vthb of the NMOS transistors 29 to 39 connected to the bit line separation line is lower than the threshold voltage Vthm of the NMOS transistor used for the memory cell. This means that the bit line separation lines BLI0L, BLI0R, B
This means that the potential level of the boosted potential Vpp supplied to the LI1L may be lower than the potential level of the boosted potential Vpp supplied to the word line WL.

From the above, the first problem of the conventional DRAM is as follows. As shown in FIG. 27, from one charge pump circuit 209, two types of drivers (B
In the LI driver 211 and the word driver 213),
When the boosted potential Vpp is supplied, the boosted potential Vpp having the same potential level is supplied from the BLI driver 211 and the word driver 213 to the bit line separation lines BLI0L, BLI0R,
It will be supplied to BLI1L and word line WL. Therefore, the potential level of boosted potential Vpp is set based on word line WL that requires a higher potential level than bit line isolation lines BLI0L, BLI0R, BLI1L. That is, the bit line separation line BLI
0, BLI0R, and BLI1L have their gates connected to the NMOSs 29 to 39, which are supplied with a boosted potential Vpp having a potential level higher than necessary. This means that the current is unnecessarily consumed and the reliability of the NMOS transistors 29 to 39 is deteriorated.

Next, the second problem of the conventional DRAM will be described. The second problem occurs in a DRAM having a low power supply potential such that the power supply potential is 2 V or less.

FIG. 32 is a circuit diagram showing a general boosted potential generating circuit used for explaining the second problem of the conventional DRAM.

Referring to FIG. 32, a general boosted potential generating circuit includes diodes 219 and 221, a capacitor 225.
And an oscillator 223. The diode 219, which serves as a precharge circuit, changes the power supply potential Vcc to
Supply to the node NA and precharge the node NA.
Therefore, the one electrode of the capacitor 225 connected to the node NA is charged. After the completion of precharge, the oscillator 223 sets the other electrode of the capacitor 225 from the ground potential GND level to the power supply potential Vcc level. That is, the oscillator 223 has a GND-
A clock signal of Vcc amplitude is generated. When a clock signal of the power supply potential Vcc level is applied to the other electrode of the capacitor 225, the node NA changes to the power supply potential Vc.
The voltage is boosted from the c level to the 2Vcc level, which is double the level. Diode 221 serving as a switch element transmits the potential of 2Vcc level to boosted potential node Npp. In this way, the boosted potential generating circuit generates boosted potential Vpp at boosted potential node Npp.

The maximum potential level of the boosted potential that can be generated by such a general boosted potential generation circuit is the power supply potential Vcc even if the boosted potential generation circuit is an ideal circuit.
Is twice the potential level. Therefore, the power supply potential Vcc
Is less than 2V, the word line WL (FIG. 28)
The boosted potential Vpp supplied to is also reduced. Therefore, when data of power supply potential Vcc level is written in the memory cell, it is affected by threshold voltage Vthm of NMOS transistor 215 (FIG. 28) forming the memory cell. The cause of such inconvenience will be described in detail.

FIG. 33 is a diagram showing the relationship between the power supply potential Vcc and the maximum boosted potential Vpp which can be generated by the boosted potential generating circuit of FIG. 32, which is used for explaining the second problem of the conventional DRAM. Is. The horizontal axis represents the power supply potential Vcc.
And the vertical axis represents the boosted potential Vpp.

Referring to FIG. 33, the straight line d is the power supply potential V
The cc level is shown. That is, for the straight line d, as shown in FIG.
The vertical axis of 3 is the power supply potential Vcc. Here, the threshold voltage Vthm of the NMOS transistor 215 (FIG. 28) of the memory cell cannot be lowered with the same slope as the power supply potential Vcc. That is, threshold voltage Vthm has the same value regardless of power supply potential Vcc. Therefore, the minimum potential level required for boosted potential Vpp has almost the same gradient as power supply potential Vcc. The straight line c indicates the minimum potential level required for the boosted potential Vpp.

Further, in actuality, the minimum required potential level of the boosted potential Vpp is the value of Vcc + Vthm, the operation margin m2 (0.V), and the detection circuit 20.
7 (FIG. 28), the control margin m1 (0.
It is necessary to add a few V). Here, the straight line b indicates the minimum potential level actually required for the boosted potential Vpp. The reason why the threshold voltage Vthm of the NMOS transistor used for the memory cell cannot be lowered with the same slope as the power supply potential Vcc is to maintain the refresh characteristic, and the control margin m1 is necessary because the charge pump is required. This is to prevent the circuit 209 (FIG. 28) from frequently operating and increasing current consumption. In summary, the minimum potential level of the boosted potential Vpp that is actually required is Vcc + Vthm + m1 + m2 (line b in FIG. 33).

On the other hand, the maximum boosted potential Vpp that can be generated by the boosted potential generating circuit (FIG. 32) sharply decreases as the power supply potential Vcc decreases. Here, the straight line a in FIG. 33 is
32 shows the maximum potential level of boosted potential Vpp that can be generated by the boosted potential generation circuit (FIG. 32).

Such a sudden drop is caused by the maximum boosted potential Vpp which can be generated by the boosted potential generating circuit (FIG. 32) being 2
Since it is at Vcc level, boosted potential generation circuit (FIG. 32)
This is because the maximum boosted potential Vpp that can occur has a gradient twice that of the power supply potential Vcc. Here, the power supply potential Vcc
Is Vb, that is, when the power supply potential Vcc is large, the maximum level of the boosted potential Vpp (straight line a) that can be generated by the boosted potential generation circuit (FIG. 32) is the level of the actually required boosted potential Vpp. There is no problem because it exceeds (straight line b). However, when the power supply potential Vcc is Va or less, that is, when the power supply potential Vcc is as small as 2 V or less, a problem occurs. That is, the power supply potential Vc
When c is Va, the level of the maximum boosted potential Vpp that can be generated by the boosted potential generation circuit (FIG. 32) is the same as the actually minimum level of the boosted potential Vpp, and the power supply potential Vcc is Va. In the following cases, the boosted potential generating circuit (see FIG.
The maximum level of the boosted potential Vpp that can occur in 2) becomes smaller than the actually required minimum level of the boosted potential Vpp. Therefore, if the power supply potential is small, the boosted potential generation circuit of FIG. 32 cannot supply the actually required boosted potential Vpp. The above is the first inconvenience. Next, the second inconvenience will be described.

FIG. 34 is a diagram showing a power supply for supplying boosted potential Vpp, which is used for explaining the second problem of the conventional DRAM. The same parts as those in FIG. 32 are designated by the same reference numerals, and the description thereof will be omitted as appropriate. In addition, the switch 227 of FIG. 34 corresponds to the diode 2 of FIG.
It corresponds to 21.

Referring to FIG. 34, if the capacitance of the capacitor 229 is Cv, the capacitor 229 will have CvVp
This means that the charge of p is accumulated. In this sense, the boosted potential node Npp to which the capacitor 229 is connected is
It can be said that the power supply supplies the boosted potential Vpp.

Here, during one operation period (during one cycle), the power supply Npp has a certain fixed charge amount, that is,
Consume Cv · Vpp. For this reason, the consumed electric charge is consumed in one cycle by the boosted potential generating circuit (diode 21
9, capacitor 225, oscillator 223, switch 2
If it is not supplemented as indicated by the arrow a from (comprising No. 27), the potential level of the boosted potential Vpp is lowered in the next cycle, and there is a risk of malfunction. The charge amount that can be replenished from the boosted potential generation circuit is Cp.
(2Vcc-Vpp). If 2Vcc-Vpp
Is small, that is, when the difference between the maximum potential level of the boosted potential that can be generated by the boosted potential generation circuit and the minimum potential level required by the boosted potential is small, the value of the capacitor (pump capacitor) 225 becomes smaller. It becomes extremely large, which causes an adverse effect of increasing the chip size. This is the second inconvenience.

The following can be considered as one of the solutions for eliminating the above first and second inconveniences. DRAM with a low power supply potential such that the power supply potential Vcc is 2 V or less
The maximum potential level of the boosted potential Vpp that can be generated by the boosted potential generation circuit is the power supply potential Vcc when used in
If it is not sufficient to double the value, a boosted potential generation circuit that can generate a value that is at least twice the power supply potential Vcc is adopted. Incidentally, such a boosted potential generating circuit is described in detail in JP-A-7-46825.

However, when one boosted potential generating circuit capable of generating a boosted potential at a level more than twice the power supply voltage Vcc is used, for example, one charge pump circuit is provided for BLI driver 211 and word driver 213. When the boosted potential Vpp at a level twice or more the power supply potential Vcc is supplied from 209 (FIG. 28), the following problem occurs. That is, the word line WL (FIG. 28) is also connected to the bit line isolation lines BLI0L, BLI0R, BLI1L (FIG. 2).
9) also has a boosted potential Vpp that is at least twice the power supply voltage Vcc.
Will be supplied. Therefore, the word line WL (FIG. 28) has a boosted potential Vp twice or more the power supply potential Vcc.
p can be given to meet the requirements of the word line WL,
NMOS transistor (bit line isolation transistor) 2
9 to 39 (FIG. 29) are supplied with a boosted potential Vpp having an unnecessarily high level. Therefore, NM
OS transistor (bit line isolation transistor) 29-
39 (FIG. 29) deteriorates reliability and consumes unnecessary current. This is the second problem.

The present invention is based on the above-mentioned first and second aspects.
The present invention has been made in order to solve the above problem and aims to provide a highly reliable DRAM while suppressing current consumption.

[0029]

A dynamic random access memory according to a first aspect of the present invention comprises a plurality of internal circuits, a plurality of boosted potential supply lines, and a plurality of boosted potential generating means. The plurality of boosted potential supply lines are provided corresponding to the plurality of internal circuits. Each boosted potential supply line supplies a boosted potential to the corresponding internal circuit. The plurality of boosted potential generating means are provided corresponding to the plurality of internal circuits. Each boosted potential generating means generates a boosted potential applied to the corresponding boosted potential supply line. The boosted potential generating means generates the boosted potential so that the potential level of the corresponding boosted potential supply line becomes the level corresponding to the corresponding internal circuit.

A dynamic random access memory according to a second aspect of the present invention is the dynamic random access memory according to the first aspect, wherein at least two of the plurality of boosted potential generating means have boosted potentials of substantially the same level. To occur.

A dynamic random access memory according to a third aspect of the present invention is the one according to the second aspect, wherein the boosted potential generating means includes a charge pump means for generating the boosted potential. The ability of the charge pump means to generate boosted potentials at substantially the same level is substantially equal.

The dynamic random access memory according to a fourth aspect of the present invention is the one according to the first aspect, wherein at least two of the plurality of boosted potential generating means generate boosted potentials of different levels. .

A dynamic random access memory according to a fifth aspect of the present invention is the one according to the fourth aspect, wherein the boosted potential generating means includes a detecting means. This detection means detects the potential level of the corresponding boosted potential supply line,
The boosted potential applied to the boosted potential supply line is maintained at the level corresponding to the corresponding internal circuit according to a predetermined detection level. In the boosted potential generating means for generating boosted potentials of different levels, the predetermined detection levels are different.

A dynamic random access memory according to a sixth aspect of the present invention is the one according to the fifth aspect, wherein the boosted potential generating means further includes a charge pump means for generating the boosted potential. The ability of the charge pump means to generate different levels of boosted potential is substantially equal.

The dynamic random access memory according to a seventh aspect of the present invention is the one according to the fifth aspect, wherein the boosted potential generating means further includes charge pump means for generating a boosted potential. The ability of the charge pump means to generate different levels of boosted potential is different.

A dynamic random access memory according to an eighth aspect of the present invention is the one according to the seventh aspect, wherein the charge pump means performs a boosting operation on the power supply potential to obtain a boosted potential. To occur. In the charge pump means that generates boosted potentials at different levels, the number of times the boosting operation is performed is different.

A dynamic random access memory according to a ninth aspect of the present invention is the one according to the fourth aspect, wherein at least one of the plurality of boosted potential generating means is:
A power supply potential detecting means for detecting the level of the power supply potential is included.
The capability of the boosted potential generation means including the power supply potential detection means is switched according to the detection result of the power supply potential detection means.

The dynamic random access memory according to a tenth aspect of the present invention is the one according to the ninth aspect, in which the boosted potential generating means including the power supply potential detecting means includes a plurality of charges for generating boosted potentials. Further included is pump means. The capacity of each charge pump means is different. The higher the level of the power supply potential, the smaller the capacity of the charge pump means operates, and the lower the level of the power supply potential, the larger the capacity of the charge pump means operates.

The dynamic random access memory according to an eleventh aspect of the present invention is the one according to the ninth aspect, wherein the boosted potential generating means including the power supply potential detecting means is a charge pump means for generating a boosted potential. Further includes. The charge pump means generates a boosted potential by performing a boosting operation on the power supply potential. The higher the power supply potential level, the smaller the number of boosting operations, and the lower the power supply potential level, the larger the number of boosting operations.

The dynamic random access memory according to claim 12 of the present invention has a plurality of operation modes. This dynamic random access memory has a first internal circuit, a first boosted potential supply line, and a first
Boosted potential generating means. The first boosted potential supply line supplies the first boosted potential to the first internal circuit. First
The boosted potential generating means of 1 generates a first boosted potential to be applied to the first boosted potential supply line. The first boosted potential generating means generates the first boosted potential so that the potential level of the first boosted potential supply line becomes a level corresponding to that of the first internal circuit. The first boosted potential generation means includes first power supply potential detection means for detecting the level of the power supply potential. The capability of the first boosted potential generating means is independent of a plurality of operation modes.
The switching is performed according to the detection result of the first power supply potential detecting means.

A dynamic random access memory according to a thirteenth aspect of the present invention is the one according to the twelfth aspect, wherein the first boosted potential generating means includes a plurality of charges for generating the first boosted potential. Further included is pump means. The capacity of each charge pump means is different. The higher the level of the power supply potential, the smaller the capacity of the charge pump means operates, and the lower the level of the power supply potential, the larger the capacity of the charge pump means operates.

A dynamic random access memory according to a fourteenth aspect of the present invention is the one according to the twelfth aspect, wherein the first boosted potential generating means is a charge pump means for generating the first boosted potential. including. The charge pump means performs a boosting operation on the power supply potential,
A first boosted potential is generated. The higher the power supply potential level, the smaller the number of boosting operations, and the lower the power supply potential level, the larger the number of boosting operations.

A dynamic random access memory according to a fifteenth aspect of the present invention is the one according to the twelfth aspect, wherein a second internal circuit, a second boosted potential supply line, and
Further provided is a second boosted potential generating means. The second boosted potential supply line supplies the second boosted potential to the second internal circuit. The second boosted potential generating means generates a second boosted potential applied to the second boosted potential supply line. The second boosted potential generating means generates the second boosted potential so that the potential level of the second boosted potential supply line becomes the level corresponding to the second internal circuit.

A dynamic random access memory according to a sixteenth aspect of the present invention is the one according to the twelfth aspect, wherein a plurality of second internal circuits and a plurality of second boosted potential supply lines are provided. It further comprises a plurality of second boosted potential generating means. The plurality of second boosted potential supply lines are provided corresponding to the plurality of second internal circuits. Each second boosted potential supply line supplies the second boosted potential to the corresponding second internal circuit. The plurality of second boosted potential generating means are provided corresponding to the plurality of second internal circuits. Each second boosted potential generating means generates a second boosted potential applied to the corresponding second boosted potential supply line. The second boosted potential generating means generates the second boosted potential so that the potential level of the corresponding second boosted potential supply line becomes the level corresponding to the corresponding second internal circuit.

A dynamic random access memory according to a seventeenth aspect of the present invention is the one according to the fifteenth aspect, wherein the second boosted potential generating means is a second power source for detecting the level of the power source potential. It includes a potential detecting means. The capability of the second boosted potential generating means is switched according to the detection result of the second power supply potential detecting means.

A dynamic random access memory according to an eighteenth aspect of the present invention is the one according to the sixteenth aspect, wherein at least one of the plurality of second boosted potential generating means has a power supply potential level. A second power supply potential detecting means for detecting The capability of the second boosted potential generation means including the second power supply potential detection means is switched according to the detection result of the second power supply potential detection means.

[0047]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A DRAM according to the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a schematic block diagram showing an overall structure of a DRAM according to Embodiment 1 of the present invention.

Referring to FIG. 1, this DRAM is formed on one semiconductor substrate 1. This DRAM includes an address signal input terminal group 3, an output pin 5, an address buffer 7, row decoders 9, 11, 13 and a word driver 1.
5, 17, 19, BLI drivers 21, 23, sense amplifier rows 25, 27, NMOS transistors (bit line isolation transistors) 29, 31, 33, 35, 37, 3
9, 41, 43, column decoder 45, preamplifier 4
7, output buffer 49, boosted potential generation unit 51 and memory array blocks B1, B2 and B3. …
Means repetition.

Now, consider the case where the memory array block B2 is selected. At this time, the sense amplifier array 25 and the bit line pair BLL, / BLL are separated by the NMOS transistors 29, 31. The sense amplifier array 25 and the bit line pair BLR, / BLR are connected by NMOS transistors 33, 35. The sense amplifier array 27 and the bit line pair BLR, / BLR are NMO
It is separated by the S transistors 41 and 43.
The sense amplifier array 27 and the bit line pair BLL, / BLL are connected by NMOS transistors 37, 39.

In such a case, the NMOS transistors 29, 31, 41, 43 are off. The BLI driver 2 is connected to the gates of the NMOS transistors 33 and 35.
The boosted potential Vpp1 supplied from 1 is input,
It is turned on. The BLI driver 21 supplies the boosted potential Vpp1 to the NMOS transistors 33 and 35 with the boosted potential Vpp1 supplied from the boosted potential generation unit 51 as a power supply potential. On the other hand, the boosted potential Vpp1 is supplied from the BLI driver 23 to the gates of the NMOS transistors 37 and 39, and the NMOS transistors 37 and 39 are turned on.
The BLI driver 23 uses the boosted potential Vpp1 supplied from the boosted potential generation unit 51 as a power supply potential to perform NMO.
The boosted potential Vpp1 is supplied to the S transistors 37 and 39.

The address signal input from the address signal input terminal group 3 is input to the row decoder 11 as a row address signal via the address buffer 7. The row address signal is decoded by the row decoder 11 and then used by the word driver 17 which activates the word line WL. The word driver 17 raises the word line WL designated by the row address signal. That is, the word driver 17 applies the boosted potential Vpp2 to the word line WL designated by the row address signal. The word driver 17 uses the boosted potential Vpp2 supplied from the boosted potential generation unit 51 as a power supply potential and the word line WL.
Is supplied with a boosted potential Vpp2. Further, the column address signal input in time division after the row address signal is fetched is input to the column decoder 45. The column decoder 45 activates a column select line (not shown) after decoding the column address signal. The data of the memory cell selected by both the word line WL and the column selection line (not shown) is amplified by the sense amplifier rows 25 and 27, and then output to the outside from the output pin 5 via the preamplifier 47 and the output buffer 49. It The memory array block B2
, A plurality of memory cells are arranged in a matrix. The row decoders 9 and 13 are the row decoder 11
The word drivers 15 and 19 are similar to the word driver 17, and the memory array blocks B1 and B3 are similar to the memory array block B2. Although only the read operation has been described above, writing is also possible. The characteristic of the DRAM according to the first embodiment resides in the boosted potential generation unit 51. Further, this DRAM has a plurality of operation modes. The operation mode includes, for example, a normal read / write operation, a standby (standby) state, and a battery backup mode.

FIG. 2 is a schematic block diagram showing a part of the DRAM of FIG. The boosted potential generating unit 51 of FIG. 1 is mainly shown.

Referring to FIG. 2, the boosted potential generating unit includes a first boosted potential generating circuit including a detection circuit D1, a ring oscillator 53 and a charge pump circuit 57,
A second boosted potential generation circuit including a detection circuit D2, a ring oscillator 55 and a charge pump circuit 59 is included. The BLI driver 61 is the BLI driver 2 of FIG.
1 and 23. The word driver 63 corresponds to the word drivers 15, 17, 19 of FIG.

The operation will be described. The detection circuit D1 is
Boosted potential node (BLI driver 61 has boosted potential Vpp
1 wiring for supplying 1) The potential level of Npp1 is detected, and when the boosted potential Vpp1 falls below the first level, the ring oscillator 53 is operated to raise the boosted potential Vpp.
When 1 becomes larger than the first level, the operation of the ring oscillator 53 is stopped. Charge pump circuit 57
Generates boosted potential Vpp1 at boosted potential node Npp1 based on clock signal CLK from ring oscillator 53 when boosted potential Vpp1 falls below the first level. The first level serving as a reference for detection in the detection circuit D1 is set so that the potential level of the boosted potential Vpp1 required by the BLI driver 61 can be maintained.

The detection circuit D2 has a boosted potential node (a wiring for supplying the boosted potential Vpp2 to the word driver 63) Np.
The potential level of p2 is detected, and the boosted potential Vpp2 becomes the second
Ring oscillator 5 when the level becomes lower than
5 is operated, and the operation of the ring oscillator 55 is stopped when the boosted potential Vpp2 becomes higher than the second level. The charge pump circuit 59, when the boosted potential Vpp2 drops below the second level, causes the ring oscillator 5 to
A boosted potential Vpp2 is generated at boosted potential node Npp2 based on clock signal CLK output from 5. The second level serving as a reference for detection in the detection circuit D2 is set so that the potential level of the boosted potential Vpp2 required by the word driver 63 can be maintained.

The charge pump circuit 57 and the charge pump circuit 59 have the same structure. The first level serving as a reference for detection in the detection circuit D1 is smaller than the second level serving as a reference for detection in the detection circuit D2. Therefore, the boosted potential Vpp1 is equal to the boosted potential Vpp2.
Will be smaller than.

As described above, the DRA according to the first embodiment
In M, there are two different boosting potentials (Vpp1, V
pp2) for generating different boosted potential generation circuits (a boosted potential generation circuit on the left side and a boosted potential generation circuit on the right side in FIG. 2). Therefore, the boosted potential Vpp1 having a magnitude required by the BLI driver 61, that is, NMO.
When turning on the S transistors 29 to 43 (FIG. 1), the boosted potential Vpp1 that is not affected by the threshold voltage can be supplied to the BLI driver 61. On the other hand, the boosted potential Vpp2 required by the word driver 63, that is, the boosted potential Vpp2 not affected by the threshold voltage when turning on the NMOS transistor forming the memory cell is supplied to the word driver 63. it can.

Therefore, as in the case where the boosted potential is supplied from one boosted potential generating circuit to the BLI driver and the word driver, the boosted potential is adjusted to the potential level required by the word driver which requires a high potential level. No need. Thus, the DRAM according to the first embodiment
Then, it is possible to supply the boost potential Vpp1 as large as necessary to the BLI driver 61, that is, it is not necessary to supply the boost potential Vpp1 larger than necessary, so that it is possible to suppress unnecessary current consumption.

Further, in the DRAM according to the first embodiment, BLI driver 61 does not apply unnecessarily large boosted potential Vpp1 to NMOS transistors (bit line isolation transistors) 29 to 43 (FIG. 1).
The circuit can be prevented from being broken, and the reliability can be improved.

Further, in the DRAM according to the first embodiment,
The BLI driver 61 is provided with a first boosted potential generation circuit, and the word driver 63 is provided with a second boosted potential generation circuit. Therefore, the operation of the first boosted potential generation circuit is not affected by the operation of the word driver 63, and the operation of the second boosted potential generation circuit is BL.
It is not affected by the operation of the I driver 61.

FIG. 3 shows the charge pump circuit 57 of FIG.
It is a circuit diagram which shows the detail of 59. The boosted potential node Npp in FIG. 3 is the boosted potential node Npp1 or N in FIG.
pp2. The boosted potential Vpp generated at the boosted potential node Npp in FIG. 3 is the boosted potential Vpp1 or V in FIG.
pp2.

Referring to FIG. 3, the charge pump circuit is
Capacitors 65 and 67 and NMOS transistor 6
Including 9, 71, 73. The capacitor 67 has a node NA
And a node to which the clock signal CLK is input. Capacitor 65 is connected between a node to which clock signal CLK is input and node NB. NMO
The S transistor 73 has a node NA and a boosted potential node N.
It is connected to pp and its gate is connected to the node NB. The NMOS transistor 69 has a power supply potential Vcc.
Is connected between the node having the NM
OS transistor 71 is connected between a node having power supply potential Vcc and node NB. The clock signal CLK is a pulse type.

The operation will be described. Before operation, node N
A and NB are power supply potential Vcc or power supply potential Vc
It is precharged to a potential lower than c by a threshold voltage. This precharging is done by NMOS
The transistors 69 and 71. Capacitors 65 and 67
A clock signal CLK is input to. The clock signal changes from the ground potential GND (0V) to the power supply potential Vcc.
Then, the potentials of the nodes NA and NB rise from the power supply potential Vcc level to twice the level of 2Vcc level due to capacitive coupling. 2V of this node NA
A cc level potential is supplied to the boosted potential node Npp as the boosted potential Vpp via the NMOS transistor 73. However, since the final driver of the charge pump circuit is the NMOS transistor 73, the potential at the level lower than 2Vcc by the threshold voltage Vthn of the NMOS transistor 73 is supplied to the boosted potential node Npp.

FIG. 4 shows the charge pump circuit 57 of FIG.
It is a circuit diagram which shows the detail of the other example of 59. The boosted potential node Npp in FIG. 4 is the boosted potential node Npp in FIG.
1 or Npp2. The boosted potential Vpp in FIG. 4 is the boosted potential Vpp1 or Vpp2 in FIG.

Referring to FIG. 4, the charge pump circuit is
Capacitors 75 and 77, level conversion circuit 79 and NM
The OS transistor 81 is included.

Capacitor 75 is connected between a node to which clock signal CLK is input and node NA. The level conversion circuit 79 widens the amplitude of the clock signal CLK and outputs it to the capacitor 77. Capacitor 77 is connected between level conversion circuit 79 and node NB. N
MOS transistor 81 is connected between node NA and boosted potential node Npp.

The charge pump circuit configured as described above is a circuit for generating boosted potential Vpp at a higher level than that of the charge pump circuit of FIG. That is,
The potential level input to the gate of the NMOS transistor 81 is set higher than the potential level (2Vcc level) input to the gate of the NMOS transistor 73 in FIG.
The potential supplied to pp is from 2 Vcc to the threshold voltage V
Thn not to fall.

FIG. 5 is a circuit diagram showing details of the level conversion circuit 79 of FIG. The same parts as those in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

Referring to FIG. 5, the level conversion circuit is NM.
OS transistors 83 and 85, PMOS transistor 8
7, 89 and an inverter 91. The PMOS transistor 87 and the NMOS transistor 83 have a boosted potential V
It is connected in series between a node having pp and a node having ground potential GND. PMOS transistor 89 and NMOS transistor 85 are connected in series between a node having boosted potential Vpp and a node having ground potential GND. Clock signal CLK as input signal IN
Is input to the gate of the NMOS transistor 83.
Clock signal CLK inverted by the inverter 91
Is input to the gate of the NMOS transistor 85. P
The gate of the MOS transistor 89 is connected to the drain of the NMOS transistor 83. The gate of the PMOS transistor 87 is connected to the drain of the NMOS transistor 85. The output signal OUT is output from the drain of the NMOS transistor 85 to the capacitor 77 of FIG.

The operation of the charge pump circuit will be described with reference to FIGS. 4 and 5. Level conversion circuit 79
When the clock signal CLK having the ground potential GND level is input to the level conversion circuit 79,
A signal OUT of the ground potential GND level is output to 7.
Next, when clock signal CLK changes from ground potential GND level to power supply potential Vcc level, level conversion circuit 79 outputs boosted potential Vpp level signal OUT to capacitor 77. That is, in the capacitor 77,
Since boosted potential Vpp is applied, the potential of node NB becomes a potential higher than 2Vcc due to the coupling capacitance. Therefore, the potential of the node NA at the level of 2 Vcc is raised to the boosted potential node Npp without being affected by the threshold voltage Vthn of the NMOS transistor 81.
Can be transmitted as the boosted potential Vpp. That is, the potential transmitted to the boosted potential node Npp is 2Vc.
The threshold voltage Vthn does not drop from c.

FIG. 6 shows the charge pump circuit 57 of FIG.
It is a circuit diagram which shows the further another example of 59 in detail. The boosted potential node Npp in FIG. 6 is the boosted potential node Npp in FIG.
1 or Npp2. The boosted potential Vpp in FIG. 6 is the boosted potential Vpp1 or Vpp2 in FIG.

Referring to FIG. 6, the charge pump circuit is
It includes an inverter 93, diodes 95 and 97, NMOS transistors 99 and 101, a PMOS transistor 103 and capacitors 105, 107 and 109. The capacitor 107 is connected between the node to which the clock signal CLK is input and the node NC. NMOS transistor 101 is connected between node NC and boosted potential node Npp, and its gate is connected to node NB.
The input node of inverter 93 is connected to the input node of clock signal CLK. The output node of the inverter 93 is connected to the gate of the PMOS transistor 103 and the NMO.
It is connected to the gate of the S transistor 99. Diode 95, PMOS transistor 103 and NMOS transistor 99 are connected in series between a node having power supply potential Vcc and a node having ground potential GND.
Capacitor 105 is connected between the input node of clock signal CLK and node NA. Capacitor 109
Is the drain of the NMOS transistor 99 and the node NB
Connected between and. The diode 97 has a power supply potential Vc.
It is connected between the node having c and the node NB.

FIG. 7 is a timing chart for explaining the operation of the charge pump circuit of FIG.

The operation of the charge pump circuit will be described with reference to FIGS. 6 and 7. Node NA is charged to the power supply potential Vcc level by diode 95 as a precharge circuit. When the clock signal CLK changes from 0 V to the power supply potential Vcc, the node NA is generated due to capacitive coupling.
Potential becomes 2Vcc level which is twice the power supply potential Vcc level. On the other hand, the potential of 0V is applied to the gate of the PMOS transistor 103, so that it turns on. Therefore, the potential of 2Vcc level is applied to capacitor 109 from node NA. The operation up to this corresponds to the expansion of the clock signal CLK, which has the amplitude of the ground potential GND (0V) to the power supply potential Vcc, to the amplitude of the ground potential GND (0V) to 2Vcc. As described above, since the capacitor 109 is supplied with the potential of 2 Vcc level, the node N
The potential of B is 3V, which is three times that of the power supply potential Vcc level
Raised to cc level. Therefore, the capacitor 1
The potential of 2Vcc level at the node NC created by 07 is an NMOS receiving the potential of 3Vcc at its gate.
NMOS transistor 1 by transistor 101
The voltage is directly transmitted to the boosted potential node Npp without lowering the threshold voltage Vthn of 01.

FIG. 8 is a circuit diagram showing details of the detection circuit D1 shown in FIG. Referring to FIG. 8, the detection circuit D1 is NM
OS transistor 111, PMOS transistor 113
And a resistance element 115. NMOS transistor 1
11, PMOS transistor 113 and resistance element 11
5 is connected in series between a node having power supply potential Vcc and a node having ground potential GND. The gate of the NMOS transistor 111 has a boosted potential node Np shown in FIG.
will be connected to p1. Therefore, the boosted potential Vpp1 is applied to the gate of the NMOS transistor 111. Note that the NMOS transistor 111
Is similar to the NMOS transistor used in the memory cell. Further, the threshold voltage of the NMOS transistor 111 is set to Vthm, and the PMOS transistor 1
The threshold voltage of 13 is Vthp.

The operation will be described. A potential of Vcc-Vthp is applied to the gate of the PMOS transistor 113. Therefore, the node NA has the power supply potential Vc.
It is at the c level. Therefore, in the NMOS transistor 111, the boosted potential Vpp1 is Vcc + Vthm.
When it is larger (Vpp1> Vcc + Vthm), it is turned on. Therefore, the detection circuit outputs the "H" level pump inactivation signal / OE to the ring oscillator 53 of FIG. Since the ring oscillator 53 of FIG. 2 stops operating and the charge pump circuit 57 also stops by the "H" level pump inactivation signal / OE, generation of the boosted potential Vpp1 is stopped.

When the boosted potential Vpp1 is not higher than Vcc + Vthm, the NMOS transistor 111 is off. Therefore, the detection circuit outputs the "L" level pump inactivation signal / OE to the ring oscillator 53 in FIG. The "L" level pump inactivation signal / OE causes the ring oscillator 53 in FIG. 2 to start operating, and the charge pump circuit 57 also generates the boosted potential Vpp1. As described above, the detection circuit D1 has the boosted potential Vpp1.
To maintain Vcc + Vthm.

FIG. 9 is a circuit diagram showing details of the detection circuit D2 shown in FIG. Referring to FIG. 9, the detection circuit D2 is PM
OS transistors 117 and 119 and resistance element 121
including. PMOS transistor 117, PMOS transistor 119 and resistance element 121 are connected in series between boosted potential node Npp2 and the node having ground potential GND in FIG. The PMOS transistor 117 is diode-connected. The power supply potential Vcc is input to the gate of the PMOS transistor 119. The threshold voltage of the PMOS transistors 117 and 119 is Vthp. In the detection circuit D2 thus configured, when the boosted potential Vpp2 becomes higher than Vcc + 2Vthp (Vpp2> Vcc + 2Vthp), the pump deactivation signal / OE of "H" level is sent to the ring oscillator 5 of FIG.
5 is output. “H” level pump inactivity signal / OE
As a result, the ring oscillator 55 stops operating, and therefore the charge pump circuit 59 also stops generating the boosted potential Vpp2. On the other hand, the boosted potential Vpp2 is Vcc + 2Vth
When it becomes p or less, the detection circuit D2 outputs an "L" level pump inactivation signal / OE to the ring oscillator 55 in FIG. "L" level pump inactivity signal / O
The ring oscillator 55 starts operating due to E, and the charge pump circuit 59 also generates the boosted potential Vpp2.

As described above, the DRAM according to the first embodiment can supply the boosted potential at the level required by each of the BLI driver and the word driver. Therefore, it is not necessary to generate an unnecessarily large boosted potential, so that unnecessary current is not consumed and reliability is not impaired.

(Second Embodiment) FIG. 10 shows a second embodiment.
FIG. 6 is a schematic block diagram showing a part of a DRAM according to the present invention. The overall structure of the DRAM according to the second embodiment is the same as that shown in FIG.
It is similar to RAM. Further, the same parts as those in FIG. 2 are designated by the same reference numerals, and the description thereof will be omitted as appropriate.

Referring to FIG. 10, a first boosted potential generating circuit including a detection circuit D1, a ring oscillator 53 and a charge pump circuit P1 and a second boosted potential generating circuit including a detection circuit D2, a ring oscillator 55 and a charge pump circuit P2.
This boosted potential generating circuit constitutes the boosted potential generating unit 51 of FIG. Part of the DRAM of FIG. 10 and the DR of FIG.
A part of AM is different in the charge pump circuit.
That is, the charge pump circuit 57 and the charge pump circuit 59 in FIG. 2 are the same, but the charge pump circuit P1 and the charge pump circuit P2 in FIG. 10 are different. The maximum value of boosted potential Vpp1 that can be generated by charge pump circuit P1 in FIG. 10 is smaller than the maximum value of boosted potential Vpp1 that can be generated by charge pump circuit P2 in FIG. The charge pump circuit of FIG. 3 can be used as the charge pump circuit P1. As the charge pump circuit P2, the charge pump circuit of FIG. 4 or 6 can be used.

The operation will be briefly described. The charge pump circuit P1 supplies the boosted potential V to the BLI driver 61 in response to the clock signal CLK from the ring oscillator 53.
Supply pp1. The detection circuit D1 has a boosted potential Vpp1.
The first potential required by the BLI driver 61
This is for controlling the ring oscillator 53 in order to maintain the above level. On the other hand, the charge pump circuit P2
Supplies the boosted potential Vpp2 to the word driver 63 based on the clock signal CLK from the ring oscillator 55. The detection circuit D2 controls the operation of the ring oscillator 55 in order to maintain the potential level of the boosted potential Vpp2 at the second level required by the word driver 63.
Here, the first level serving as a reference for detection by the detection circuit D1 is smaller than the second level serving as a reference for detection by the detection circuit D2.

As described above, the DRA according to the second embodiment
In M, two boosted potential generation circuits (first boosted potential generation circuit and second boosted potential generation circuit) that generate different boosted potentials are provided, and two drivers (BLI driver) that require boosted potentials at different levels are provided. 61, word driver 6
The boosted potential is supplied to 3). Therefore, similarly to the first embodiment, the BLI driver 61 can be supplied with a boosted potential at a necessary level, and the BLI driver 61 can be supplied with the boosted potential.
On the other hand, it is not necessary to generate an unnecessarily large boosted potential. Therefore, in the DRAM according to the second embodiment, useless current consumption can be suppressed. Further, in the DRAM according to the second embodiment, a circuit element (NMOS transistor 29 in FIG.
~ 43) can be prevented and the reliability can be improved.

Further, in the DRAM according to the second embodiment,
The BLI driver 61 is provided with a first boosted potential generation circuit, and the word driver 63 is provided with a second boosted potential generation circuit. Therefore, the operation of the first boosted potential generation circuit is not affected by the operation of the word driver 63, and the operation of the second boosted potential generation circuit is BL.
It is not affected by the operation of the I driver 61.

(Embodiment 3) DR according to Embodiment 3
AM relates to a DRAM having a low power supply potential. For example, this is the case when the power supply potential is 2 V or less.

FIG. 11 is a schematic block diagram showing a part of a DRAM according to the third embodiment. Embodiment 3
The overall structure of the DRAM according to the above is the same as that of the DRAM of FIG. The same parts as those in FIG. 2 are designated by the same reference numerals, and the description thereof will be omitted as appropriate.

Referring to FIG. 11, a first boosted potential generation circuit including detection circuit D1, ring oscillator 53 and 2Vcc generation charge pump circuit P3, and detection circuit D
2, the second boosted potential generating circuit including the ring oscillator 55 and the 3Vcc generating charge pump circuit P4,
The boosted potential generation unit 51 of FIG. 1 is configured. The difference between the part of the DRAM of FIG. 11 and the part of the DRAM of FIG. 2 is the charge pump circuit. That is, in FIG. 2, the charge pump circuit 57 of the first boosted potential generating circuit is shown.
11 is similar to the charge pump 59 of the second boosted potential generation circuit, but in FIG. 11, the charge pump circuit of the first boosted potential generation circuit is the 2Vcc generation charge pump circuit P3, and the second boosted potential generation circuit is the same. The charge pump circuit of the potential generation circuit is the 3Vcc generation charge pump circuit P4. 2 to supply boosted potential Vpp1 of 2 Vcc level
As the Vcc generation charge pump circuit P3, the charge pump circuit of FIG. 3, FIG. 4 or FIG. 6 can be used. The operation of the boosted potential generating unit will be briefly described with reference to FIG. The 2Vcc generation charge pump circuit P3 supplies the boosted potential Vpp1 to the BLI driver 61. The detection circuit D1 controls the operation of the ring oscillator 53 in order to maintain the boosted potential Vpp1 at the first level required by the BLI driver 61. On the other hand, 3
The Vcc generation charge pump circuit P4 supplies the boosted potential Vpp2 to the word driver 63 in response to the clock signal CLK from the ring oscillator 55. Detection circuit D2
Maintains the boosted potential Vpp2 at the second level required by the word driver 63, the ring oscillator 55
Control the behavior of. The first level serving as a reference for detection in the detection circuit D1 is smaller than the second level serving as a reference for detection in the detection circuit D2.

As described above, the DRA according to the third embodiment
In M, the BLI driver 61 and the word driver 63
Can supply the boosted potential at a level required by each of the BLI driver 61 and the word driver 63.
Therefore, as in the first embodiment, the BLI driver 61
On the other hand, it is not necessary to generate an unnecessarily large boosted potential, so that useless current consumption can be suppressed. Further, since a boosted potential larger than necessary is not generated, the circuit element (see FIG.
It is possible to prevent the destruction of the NMOS transistors 29 to 43) and improve the reliability. Also, 3Vcc
Since the generated charge pump circuit P4 can generate the boosted potential Vpp2 at the level of 3 Vcc, the DRAM of the low power supply potential is used.
Also in this case, the boosted potential Vpp2 at the level required by the word driver 63 can be supplied. Therefore, in the DRAM according to the third embodiment, the above effect can be obtained even when the power supply potential is low.

Further, in the DRAM according to the third embodiment,
The BLI driver 61 is provided with a first boosted potential generation circuit, and the word driver 63 is provided with a second boosted potential generation circuit. Therefore, the operation of the first boosted potential generation circuit is not affected by the operation of the word driver 63, and the operation of the second boosted potential generation circuit is BLI.
It is not affected by the operation of the driver 61.

FIG. 12 is a circuit diagram showing details of 3Vcc generating charge pump circuit P4 of FIG. FIG.
The same parts as those in 1 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

Referring to FIG. 12, 3Vcc generating charge pump circuit P4 includes capacitors 123 and 125, diodes 127 and 129, an NMOS transistor 131 and a level converting circuit 133.

The capacitor 123 receives the clock signal CLK.
Is connected between the input node and the node NA. Diode 127 is connected between a node having power supply potential Vcc and node NA. Capacitor 125 is connected between the output node of level conversion circuit 133 and node NB. Diode 129 is connected between a node having power supply potential Vcc and node NB. The NMOS transistor 131 includes a node NB and a boosted potential node Npp.
It is connected between 2 and. The gate of the NMOS transistor 131 is connected to the node NB. Here, the level conversion circuit 133 is similar to the level conversion circuit of FIG. However, the level conversion circuit of FIG.
The level conversion circuit 133 of FIG. 2 is connected between the node having p and the node having the ground potential GND.
Is connected between node NA and a node having ground potential GND. Node NA is set to the power supply potential Vcc level by diode 127 as a precharge circuit. When the clock signal CLK applied to the capacitor 123 is changed from the ground potential GND level to the power supply potential Vcc level, the potential of the node NA becomes 2Vcc level due to capacitive coupling. The level conversion circuit 133, which uses the node NA having the potential of the 2Vcc level as a power source, outputs the potential of the 2Vcc level to the capacitor 125. This means that the clock signal C
This corresponds to widening the amplitude of LK from the ground potential GND to the power supply potential Vcc amplitude to the ground potential GND to 2Vcc amplitude. When a potential of 2 Vcc is applied to the capacitor 125, the node N that is precharged to the power supply potential Vcc
The potential of B becomes 3 Vcc due to capacitive coupling. NMO
The S-transistor 131 has a voltage level of 3V at the node NB.
The potential of cc level is transmitted to boosted potential node Npp2. However, to be precise, it is affected by the threshold voltage Vthn of the NMOS transistor 131, so that the potential of 3Vcc-Vthn is transmitted to the boosted potential node Npp2. As described above, the 3Vcc generating charge pump circuit P4 of FIG. 12 can generate the boosted potential Vpp2 of 3Vcc-Vthn at the maximum.

FIG. 13 is a circuit diagram showing details of another example of 3Vcc charge pump generating circuit P4 of FIG. Note that the same parts as those in FIG. 12 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

Referring to FIG. 13, NMOS transistor 135 is connected between node NB and boosted potential node Npp2. The gate of the NMOS transistor 135 is connected to the node NB. The NMOS transistor 135 differs from the NMOS transistor 131 of FIG. 12 in that the NMOS transistor 135 has a triple well structure. Thus, FIG.
Since the 3Vcc generation charge pump circuit P4 of 3 adopts the triple well structure NMOS transistor 135, the normal NMOS transistor 1 as shown in FIG.
As compared with the case where 31 is adopted, the influence of the threshold voltage at the time of transmitting the 3Vcc level potential of the node NB to the boosted potential node Npp2 can be reduced. That is, 3V in FIG.
Maximum boosted potential Vpp2 that can be generated by cc generation charge pump circuit P4 is larger than maximum boosted potential Vpp2 that can be generated by 3Vcc generation charge pump circuit P4 in FIG.

FIG. 14 is a circuit diagram showing details of still another example of 3Vcc generating charge pump circuit P4 of FIG. The same parts as those in FIG. 11 are designated by the same reference numerals, and the description thereof will be omitted as appropriate.

Referring to FIG. 14, 3Vcc generating charge pump circuit P4 includes diodes 141, 143, NMO.
S transistors 137 and 139, capacitors 145 and 1
47 and an inverter 149. Capacitor 145
Is connected between node NA and the input node of clock signal CLK. The diode 141 has a power supply potential Vcc.
Is connected between the node having the NM
OS transistor 137 is connected between nodes NA and NB. The gate of the NMOS transistor 137 is connected to the node NA. Diode 143 is connected between a node having power supply potential Vcc and node NB. NMOS transistor 139 is connected between node NB and boosted potential node Npp2. NMOS
The gate of transistor 139 is connected to node NB. The capacitor 147 is connected to the node NB and the inverter 14
And 9 output nodes. Inverter 149
The clock signal CLK is input to the input node of.

FIG. 15 is a timing chart for explaining the operation of 3Vcc generating charge pump circuit P4 of FIG.

Referring to FIGS. 14 and 15, 3 Vcc
The operation of the generated charge pump circuit will be described. Node NA
Is precharged to the power supply potential Vcc level by the diode 141. When clock signal CLK is changed from ground potential GND (0V) to power supply potential Vcc, the potential of node NA is set to 2Vcc level due to capacitive coupling. The potential at the 2Vcc level of this node NA is NM
It is transmitted to the node NB through the OS transistor 137. Therefore, the potential of node NB that has been precharged to power supply potential Vcc level further rises to the level of power supply potential Vcc and becomes 2Vcc-Vthn. Next, when the clock signal CLK is changed from the power supply potential Vcc to the ground potential GND (0V), the clock signal CLK is inverted by the inverter 149, so that the node NB having the potential of 2Vcc-Vthn level is capacitively coupled. Will rise to the level of 3Vcc-Vthn. Then, the NMOS transistor 139 transmits the 3Vcc-Vthn level potential of the node NB to the boosted potential node Npp as the boosted potential Vpp2. However, to be exact, the threshold voltage V
In consideration of thn, 3Vcc-2 is applied to the node Npp.
A Vthn level potential is applied. Note that Vthn
Is the threshold voltage of the NMOS transistors 137 and 139. The 3Vcc generating charge pump circuit P4 configured in this manner can generate the boosted potential Vpp2 at the maximum level of 3Vcc-2Vthn.

The operation of the 3Vcc generating charge pump circuit of FIG. 14 can be summarized as follows.
The first boosting operation is performed on cc, and the second boosting operation is further performed at node NB to generate boosted potential Vpp2 of 3Vcc-2Vthn level at boosted potential node Npp.

DRAM according to the third embodiment as described above
Then, since it is not necessary to generate a boosted potential larger than necessary, useless current consumption can be suppressed. Furthermore, since a boosted potential larger than necessary is not generated, it is possible to prevent the circuit from being broken and improve the reliability.

(Embodiment 4) DR according to Embodiment 4
AM is a wide power supply specification DRA with a wide power supply potential.
Target M. The wide power supply specification is a DRAM that can be used with a low power supply potential or a high power supply potential within the range because a wide range of power supply potentials can be used.

In such a wide power supply type DRAM, when the low power supply potential Vcc is used, the maximum is 2 Vc.
Depending on the boosted potential generating circuit capable of generating only the boosted potential of c, it is not possible to generate the boosted potential at the “H” level sufficient to supply to the word line. On the other hand, wide power supply specification DRA
In M, when a high power supply potential is used, a boosted potential generation circuit that generates a boosted potential of 3 Vcc at the maximum is used. Therefore, as the “H” level potential supplied to the word line,
Excessive boosted potential will be generated. The DRAM according to the fourth embodiment is for solving such a problem.

FIG. 16 is a schematic block diagram showing a part of DRAM according to the fourth embodiment. Note that the same parts as those in FIG. The overall structure of the DRAM according to the fourth embodiment is similar to that of the DRAM of FIG.

Referring to FIG. 16, a first boosted potential generating circuit including a detecting circuit D1, a ring oscillator 53 and a 2Vcc generating charge pump circuit P3, and a detecting circuit D are shown.
2, a ring oscillator 55, a switch circuit 153, a power supply potential detection circuit 151, a 2Vcc generation charge pump circuit P5 and a 3Vcc generation charge pump circuit P6, and the second boosted potential generation circuit is the boosted potential generation unit 51 of FIG. Configure.

The operation will be described with reference to FIG. 2V
The cc generation charge pump circuit P3 receives the boosted potential Vp based on the clock signal CLK from the ring oscillator 50.
p1 is generated and supplied to the BLI driver 61. The detection circuit D1 detects the potential level of the boosted potential Vpp1,
The ring oscillator 53 is controlled to maintain the boosted potential Vpp1 at the first level required by the BLI driver 61.

The power supply potential detection circuit 151 has a power supply potential Vc.
The potential level of c is detected. Then, the switching signal SS having different levels is output to the switch circuit 153 according to the level of the power supply potential. The switch circuit 153 responds to the switching signal SS by 2Vc regardless of the operation mode of the DRAM.
Either the c-generation charge pump circuit P5 or the 3Vcc generation charge pump circuit P6 is operated. When the level of the power supply potential Vcc detected by the power supply potential detection circuit 151 is lower than the predetermined level, the switch circuit 15
3 operates the 3Vcc generation charge pump circuit P6. Power supply potential Vc detected by the power supply potential detection circuit 151
If c is larger than a predetermined level, the switch circuit 15
3 operates the 2Vcc generation charge pump circuit P5. The 2Vcc generating charge pump circuit P5 can generate the boosted potential Vpp2 of 2Vcc at the maximum. 3Vc
The c generation charge pump circuit P6 can generate the boosted potential Vpp2 of 3 Vcc at the maximum.

Boosted potential Vpp2 generated by either 2Vcc generation charge pump circuit P5 or 3Vcc charge pump circuit P6 is applied to word driver 63. The detection circuit D2 detects the potential level of the boosted potential Vpp2 and controls the operation of the ring oscillator 55 in order to maintain the boosted potential Vpp2 at the second level required by the word driver 63. The switch circuit 153 is 2
When operating Vcc generation charge pump circuit P5, clock signal CLK from ring oscillator 55 is transmitted to 2Vcc generation charge pump circuit P5. The switch circuit 153 has a 3Vcc generation charge pump circuit P6.
Is operated, the clock signal CLK from the ring oscillator 55 is transmitted to the 3Vcc generation charge pump circuit P6.

As the 2Vcc generation charge pump circuit P5, the charge pump circuits shown in FIGS. 3, 4 and 6 can be used. As the 3Vcc generation charge pump circuit P6, the charge pump circuits of FIGS. 12, 13 and 14 can be used.

In the DRAM configured as described above, B
Each of the LI driver 61 and the word driver 63 can supply the boosted potential at a required level to each of the BLI driver 61 and the word driver 63. Therefore, as in the first embodiment, it is not necessary to generate an unnecessarily large boosted potential for the BLI driver 61, and useless current consumption can be suppressed. Further, since a boosted potential larger than necessary is not generated, it is possible to prevent the circuit elements (NMOS transistors 29 to 43 in FIG. 1) from being broken and improve the reliability.

When the power supply potential Vcc is small,
Sufficient boosted potential can be generated by using the 3Vcc generation charge pump circuit P6 having a large capacity. On the other hand, when the power supply potential Vcc is large, the 2Vcc generation charge pump circuit P5 having a small capacity is operated, and the large capacity 3Vc
Since the c-generation charge pump circuit P6 is not operated, it does not generate an unnecessarily large boosted potential. Therefore, useless consumption of current can be suppressed.

Further, in the DRAM according to the fourth embodiment,
The BLI driver 61 is provided with a first boosted potential generation circuit, and the word driver 63 is provided with a second boosted potential generation circuit. Therefore, the operation of the first boosted potential generation circuit is not affected by the operation of the word driver 63, and the operation of the second boosted potential generation circuit is not affected by the operation of the BLI driver 61.

FIG. 17 shows the power supply potential detection circuit 15 of FIG.
It is a circuit diagram which shows the detail of 1. The same parts as those in FIG. 16 are designated by the same reference numerals, and the description thereof will be omitted as appropriate.

Referring to FIG. 17, the power supply potential detecting circuit is
PMOS transistors 155, 157, 159, 16
1,163,165, NMOS transistors 167,1
69 and a resistance element 171.

PMOS transistors 155, 157, 1
59 and resistance element 171 are connected in series between a node having power supply potential Vcc and a node having ground potential GND. PMOS transistors 155, 157, 1
Each of 59 is diode-connected. PMOS transistors 161, 163 and NMOS transistor 16
7 is a node having a power supply potential Vcc and a ground potential GND
Is connected in series with the node having. A potential of Vcc-Vthp level is applied to the gate of the PMOS transistor 161. Here, the threshold voltage of the PMOS transistor 161 is Vthp. PMOS
The gates of the transistor 163 and the NMOS 167 are
It is connected to the node NA. PMOS transistor 165
And NMOS 169 are connected in series between a node having power supply potential Vcc and a node having ground potential GND. The gates of the PMOS transistor 165 and the NMOS transistor 169 are connected to the NMOS transistor 16
7 drain. NMOS transistor 16
The switching signal SS is output from the drain of 9.

The operation will be described. The threshold voltage of the PMOS transistors 155 to 159 is Vthp.
In such a case, the potential level of the power supply potential Vcc is 3V.
Above thp, the node NA is charged. Therefore, the PMOS transistor 163 turns off and the NMOS transistor 167 turns on. In response to this, the PMOS transistor 165 turns on and the NMOS transistor 16
9 turns off. Therefore, when the potential level of power supply potential Vcc is higher than 3Vthp, switching signal SS of "H" level is output to switch circuit 153 in FIG. Then, the switch circuit 153 is 2 Vc
The c generation charge pump circuit P5 is operated. On the other hand, when the potential level of power supply potential Vcc is lower than 3Vthp, node NA is not charged. Therefore, PM
The OS transistor 163 is turned on and the NMOS transistor 167 is turned off. In response, the PMOS transistor 165 turns off and the NMOS transistor 169 turns on. Therefore, when the potential level of power supply potential Vcc is lower than 3 Vthp, switching signal SS of "L" level is output to switch circuit 153 in FIG. The switch circuit 153 has a voltage of 3V.
The cc generation charge pump circuit P6 is operated.

FIG. 18 shows the power supply potential detection circuit 15 of FIG.
It is a circuit diagram which shows the detail of the other example of 1. The same parts as those in FIG. 16 are designated by the same reference numerals, and the description thereof will be omitted as appropriate.

Referring to FIG. 18, the power supply potential detecting circuit is
It includes a constant potential generation circuit 177, a current mirror circuit 179, and resistance elements 173 and 175. The resistance element 17
3 and the resistance element 175 form a level shifter circuit.

Constant potential generating circuit 177 applies a reference potential of a constant level to one input node of current mirror circuit 179. The level shifter circuit including the resistance elements 173 and 175 level-shifts the power supply potential Vcc and supplies it to the other input node of the current mirror circuit 179. The current mirror circuit 179 compares the reference potential from the constant potential generation circuit 177 with the potential from the level shifter circuit including the resistance elements 173 and 175, and when the potential from the level shifter circuit is higher than the reference potential, "H" The switching signal SS of the "level" is output to the switch circuit 153 of FIG. Then, the switch circuit 153 of FIG. 16 operates the 2Vcc generation charge pump circuit P5. On the other hand, when the potential from the level shifter circuit including the resistance elements 173 and 175 is smaller than the reference potential from the constant potential generation circuit 177, the current mirror circuit 179 switches the switching signal SS of “L” level to the switch of FIG. Output to the circuit 153. In response to this, switch circuit 153 operates 3 Vcc generation charge pump circuit P6.

FIG. 19 is a circuit diagram showing details of the switch circuit 153 of FIG. Note that in FIG.
The same reference numerals as 6 are the same as those in FIG.

Referring to FIG. 19, the switch circuit includes a logic circuit 181 and a NAND circuit 183. At one input node of the logic circuit 181 and the NAND circuit 183, the switching signal SS from the power supply potential detection circuit 151 of FIG.
Is entered. Logic circuit 181 and NAND circuit 18
The clock signal CLK is input to the other input node of 3.

The power supply potential Vcc is the power supply potential detection circuit 15
16, if the switching signal SS at the “H” level is input to the logic circuit 181 and the NAND circuit 183, the NAND circuit 183 outputs the clock signal CLK as shown in FIG. 2Vcc generating charge pump circuit P5. On the other hand, the power supply potential V
When it is determined by the power supply potential detection circuit 151 in FIG. 16 that cc is smaller than the predetermined level, the “L” level switching signal SS is input to the logic circuit 181 and the NAND circuit 183. In this case, the logic circuit 181
However, the clock signal CLK is transmitted to the 3Vcc generation charge pump circuit P6 of FIG.

The DRA according to the fourth embodiment as described above
In M, since it is not necessary to generate a boosted potential larger than necessary, it is possible to suppress wasteful consumption of current. Further, since a boosted potential larger than necessary is not generated, it is possible to prevent the destruction of the circuit element and improve the reliability. Also,
Since the capacity of the charge pump circuit is switched according to the level of the power supply potential Vcc, useless current consumption can be suppressed even in the wide power supply specification.

(Fifth Embodiment) DR according to the fifth embodiment
Similar to the DRAM according to the fourth embodiment, the AM is intended for a wide power supply specification DRAM.

FIG. 20 is a schematic block diagram showing a part of a DRAM according to the fifth embodiment. The same parts as those in FIG. 16 are designated by the same reference numerals, and the description thereof will be omitted as appropriate. The overall structure of the DRAM according to the fifth embodiment is similar to that of the DRAM of FIG.

Referring to FIG. 20, a first boosted potential generating circuit including a detecting circuit D1, a ring oscillator 53 and a 2Vcc generating charge pump circuit P3, and a detecting circuit D are shown.
2, the second boosted potential generation circuit including the ring oscillator 55, the charge pump circuit P7, and the power supply potential detection circuit 151 constitutes the boosted potential generation unit 51 of FIG.

The operation will be described. The 2Vcc charge pump circuit P3 generates the boosted potential Vpp1 in response to the clock signal CLK from the ring oscillator 53, and B
It is supplied to the LI driver 61. The detection circuit D1 detects the potential level of the boosted potential VPP1, and detects the BLI driver 61.
In order to maintain the boosted potential Vpp1 at the first level required by, the operation of the ring oscillator 53 is controlled.

The power supply potential detecting circuit 151 is shown in FIG.
Alternatively, the power supply potential detection circuit in FIG. 18 can be used. When the power supply potential detection circuit 151 determines that the potential level of the power supply potential Vcc is lower than the predetermined level,
The charge pump circuit P7 receives the "L" level switching signal SS.
Output to The charge pump circuit P7 is "L".
According to the level switching signal SS, the boosted potential Vpp2 of 3 Vcc at maximum can be generated. When the power supply potential detection circuit 151 determines that the potential level of the power supply potential Vcc is higher than the predetermined level, it outputs the switching signal SS of "H" level to the charge pump circuit P7. Then, the charge pump circuit P7 receives the boosted potential Vp of 2Vcc level at maximum by the switching signal SS of "H" level.
It becomes possible to generate p2. Such switching of the capacity of the charge pump circuit P7 is performed regardless of the operation mode of the DRAM. The charge pump circuit P7 generates the boosted potential Vpp2 according to the clock signal CLK from the ring oscillator 55 and supplies it to the word driver 63. The detection circuit D2 detects the potential level of the boosted potential Vpp2 and controls the operation of the ring oscillator 55 in order to maintain the boosted potential Vpp2 at the second level required by the word driver 63.

As described above, the DRA according to the fifth embodiment
In M, the BLI driver 61 and the word driver 63
Of the BLI driver 61
And the word driver 63. Therefore, as in the first embodiment, it is not necessary to generate an unnecessarily large boosted potential for the BLI driver 61, and useless current consumption can be suppressed. Furthermore, since a boosted potential larger than necessary is not generated, it is possible to prevent the circuit elements (NMOS transistors 29 to 43 in FIG. 1) from being broken and improve the reliability.

When the power supply potential Vcc is small, the capacity of the charge pump circuit is increased and a boosted potential of a sufficient level is generated. On the other hand, when the power supply potential is large, the capacity of the charge pump circuit is reduced, so that an unnecessarily large boosted potential is not generated. Therefore, useless consumption of current can be suppressed.

Further, in the DRAM according to the fifth embodiment,
The BLI driver 61 is provided with a first boosted potential generation circuit, and the word driver 63 is provided with a second boosted potential generation circuit. Therefore, the operation of the first boosted potential generation circuit is not affected by the operation of the word driver 63, and the operation of the second boosted potential generation circuit is not affected by the operation of the BLI driver 61.

FIG. 21 shows the charge pump circuit P of FIG.
7 is a circuit diagram showing details of FIG. The same parts as those in FIG. 20 are designated by the same reference numerals, and the description thereof will be omitted as appropriate.

Referring to FIG. 20, charge pump circuit P
7 is a NAND circuit 185, inverters 186, 18
7, capacitors 189, 191, diodes 193, 1
95, a level conversion circuit 199 and an NMOS transistor 197.

One input node of the inverter 186 is
The switching signal SS is input from the power supply potential detection circuit 151 of FIG. One input node of the NAND circuit 185 has
The output node of the inverter 186 is connected, and the clock signal CLK from the ring oscillator 55 of FIG. 20 is input to the other input node. The output node of NAND circuit 185 is connected to the input node of inverter 187. Capacitor 189 is connected between the output node of inverter 187 and node NA. Diode 193 is connected between a node having power supply potential Vcc and node NA. The capacitor 191 has nodes NB and NC.
Connected between and. The diode 195 has a power supply potential V
It is connected between the node having cc and the node NB.
The NMOS transistor 197 has a boosted potential node Npp.
2 and the node NB. The gate of the NMOS transistor 197 is connected to the node NB. In addition,
The NMOS transistor 197 has a triple well structure similar to that of the NMOS transistor 135 of FIG. The level conversion circuit 199 is similar to the level conversion circuit in FIG. However, while the level conversion circuit of FIG. 5 uses the boosted potential Vpp as the power supply potential,
The level conversion circuit 199 in FIG. 21 uses the potential of the node NA as the power supply potential.

The operation will be described. First, consider a case where power supply potential detecting circuit 151 of FIG. 20 determines that power supply potential Vcc is lower than a predetermined level and outputs switching signal SS of “L” level to inverter 186. That is,
This is the case where a charge pump circuit capable of generating a maximum of 2 Vcc is insufficient because the power supply potential Vcc is small. The node NA is a diode 193 as a precharge circuit.
Is precharged to the power supply potential Vcc level. Since the “L” level switching signal SS is input to the inverter 186, the clock signal CLK is transmitted to the capacitor 189. When clock signal CLK is changed from ground potential GND to power supply potential Vcc, the potential of node NA changes from the level of power supply potential Vcc to the level of 2Vcc due to capacitive coupling. The level conversion circuit 199 outputs a potential of 2Vcc level to the capacitor 191, using the node NA having such a potential of 2Vcc level as a power supply. This corresponds to expanding the amplitude of the clock signal CLK from the ground potential GND to the power supply potential Vcc amplitude to the ground potential GND to 2Vcc amplitude.

Since node NB is precharged to power supply potential Vcc, when a potential of 2 Vcc level is applied to capacitor 191, the capacitance is coupled to node NB.
Potential becomes 3 Vcc. NMOS transistor 197
Transmits the potential of node NB at the 3Vcc level to boosted potential node Npp2. However, to be precise, considering the threshold voltage Vthn of the NMOS transistor 197,
A potential of 3Vcc-Vthn is applied to boosted potential node Npp2. Thus, the power supply potential Vc
When c is small and the switching signal SS of "L" level is input to the inverter 186, the charge pump circuit P7
Can generate boosted potential Vpp2 of 3 Vcc-Vthn at the maximum.

The operation when the "L" level switching signal is input can be summarized as follows: At the node NA, the power supply potential Vcc
To the node N
By performing the second boosting operation at B, 3Vcc-V
A thn level boosted potential Vpp2 is generated.

Next, the power supply potential detecting circuit 151 of FIG.
However, it is determined that the power supply potential Vcc is higher than a predetermined level,
The “H” level switching signal SS is supplied to the charge pump circuit P7.
Consider the case of output to. That is, since the power supply potential Vcc is large, it is sufficient to generate a boosted potential of 2 Vcc level at the maximum. The inverter 186 has
The "H" level switching signal SS is input. For this reason,
NAND regardless of the level change of the clock signal CLK
The output of the circuit 185 is fixed to the "H" level. Therefore, level conversion circuit 199 uses the node NA having the potential of power supply potential Vcc level as the power supply. As a result, when the clock signal CLK is changed from the ground potential GND to the power supply potential Vcc, the level conversion circuit 199.
Outputs a power supply potential Vcc level potential to the capacitor 191. The potential of the node NB precharged to the power supply potential Vcc level is 2V due to capacitive coupling.
cc level. The NMOS transistor 197 is
The potential of the node NB at the level of 2 Vcc is increased to the boosted potential node N.
I will tell pp2. However, to be exact, NMO
Considering the threshold voltage Vthn of the S transistor 197, 2Vcc-Vthn is applied to the boosted potential node Npp2.
The potential of will be transmitted. As described above, when the power supply potential Vcc is large, the power supply potential detection circuit 151 outputs the switching signal SS at the “H” level to the inverter 186, so that the charge pump circuit P7 has a maximum voltage of 2V.
A boosted potential Vpp2 of cc-Vthn level is generated.

The operation when the switching signal of "H" level is input can be summarized as follows: node NB boosts power supply potential Vcc once to obtain 2Vcc-
A boosted potential Vpp2 of Vthn level is generated.

FIG. 22 shows the charge pump circuit P of FIG.
It is a circuit diagram which shows the other example of 7 in detail. The same parts as those in FIG. 14 are designated by the same reference numerals, and the description thereof will be omitted as appropriate.

Referring to FIG. 22, charge pump circuit P
7 is a NAND circuit 201 and inverters 202, 20
3, 149, capacitors 145, 147, NMOS transistors 137, 139 and diodes 141, 14
3 inclusive. The input node of the inverter 202 is shown in FIG.
The switching signal SS is input from the power supply potential detection circuit 151. One input node of the NAND circuit 201 is connected to the output node of the inverter 202, and the other input node is connected to the clock signal C from the ring oscillator 55 of FIG.
LK is input. The input node of the inverter 203 is
It is connected to the output node of NAND circuit 201, and the output node is connected to capacitor 145.

First, the power supply potential detection circuit 151 of FIG.
However, consider a case where the potential level of the power supply potential Vcc is judged to be lower than a predetermined level and the switching signal SS of “L” level is output to the inverter 202. Since the switching signal SS of “H” level is input to the inverter 202, the level change of the clock signal CLK is caused by the capacitor 1
45. Node NA is precharged to power supply potential Vcc. Therefore, the clock signal CLK
However, when the ground potential GND is changed to the power supply potential Vcc, the potential of the node NA becomes a potential of 2Vcc level due to capacitive coupling. In this case, the NMOS transistor 1
37 is turned on, and the node NB is connected to the node Vcc-
A Vthn level potential is applied. As a result, the potential of the node NB changes from the power supply potential Vcc level to 2V.
cc-Vthn level. The threshold voltage of the NMOS transistor 137 is Vthn.

Next, the clock signal CLK changes to the power supply potential Vc.
When the voltage is changed from c to the ground potential GND, the capacitor 1
A potential of power supply potential Vcc level is applied to 47.
Therefore, the potential of the node NB, which is the potential of 2Vcc-Vthn level, is 3Vcc-Vth due to capacitive coupling.
The potential is set to the n level. NMOS transistor 139
Transmits a potential of 3Vcc-Vthn level from node NB to boosted potential node Npp2. However, to be exact,
Considering the boosted potential Vthn of the NMOS transistor 139, 3Vcc-2Vt is applied to the boosted potential node Npp2.
The potential of hn is transmitted. In this way, the power supply potential Vcc
Is small and the switching level SS of "L" level is input to the inverter 202, the maximum is 3Vcc-2Vt.
A boosted potential Vpp2 of hn is generated.

The operation when the switching signal SS of "L" level is input is summarized as follows.
c is subjected to the first boosting operation, and further to the node NB for the second boosting operation to obtain 3Vcc-2Vth.
An n level boosted potential Vpp2 is generated.

Next, consider a case where power supply potential detection circuit 151 of FIG. 20 determines that power supply potential Vcc is higher than a predetermined level and switching signal SS of "H" level is input to inverter 202. In the inverter 202,
Since the switching signal SS of "L" level is input, even if the level of the clock signal CLK changes, N
The output of the AND circuit 201 is fixed at "H" level.
Therefore, even when clock signal CLK changes from ground potential GND to power supply potential Vcc, the potential of node NB is at power supply potential Vcc level. And the clock signal C
When LK is changed from power supply potential Vcc to ground potential GND, capacitor 147 is supplied with a power supply potential Vcc level potential. Therefore, the potential of node NB is changed from the power supply potential Vcc level to 2Vcc level by capacitive coupling. The NMOS transistor 139 transmits the potential of 2Vcc level from the node NB to the boosted potential node Npp2. However, to be precise, considering the threshold voltage Vthn of the NMOS transistor 139, a potential of 2Vcc-Vthn is transmitted to the boosted potential node Npp2. In this way, the power supply potential Vcc
Is large, and the switching signal SS of "H" level is transmitted to the inverter 2
If it is input to 02, the charge pump circuit P7
Is a boosted potential Vpp of 2Vcc-Vthn level at the maximum.
2 is generated.

When the switching signal SS of "H" level is input, the operation is summarized. Node NB performs the boosting operation once to generate boosted potential Vpp2 of 2Vcc-Vthn.

The DRA according to the fifth embodiment as described above
In M, it is not necessary to generate an unnecessarily large boosted potential, so that it is possible to suppress wasteful consumption of current. Further, since a boosted potential larger than necessary is not generated, it is possible to prevent the destruction of the circuit element and improve the reliability. In addition, the charge pump circuit P7 is supplied depending on the level of the power supply potential Vcc.
In the above, since the number of times the boosting operation is performed is switched, it is possible to generate a boosted potential at a required level, and it is possible to suppress unnecessary current consumption even in the case of the wide power supply specification.

The charge pump circuits of FIGS. 21 and 22 switch between one boosting operation and two boosting operations. However, the charge pump circuit P7 of FIG.
It is also possible to switch the boosting operation once and the boosting operation N2 times. Here, N1 and N2 mean natural numbers,
N1 and N2 are different.

(Embodiment 6) DR according to Embodiment 6
The overall structure of the AM is similar to that of the DRAM of FIG. However, in the DRAM according to the sixth embodiment, boosted potential generating unit 51 of FIG.
1, Vpp2 and Vpp3 are generated.

FIG. 23 is a circuit diagram showing details of the sense amplifier array 25 of FIG. The same parts as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted as appropriate.

Referring to FIG. 23, sense amplifier array 25
Shows a plurality of sense amplifiers 5 although not all are shown.
01, a plurality of equalizing circuits 503 and a plurality of equalizing circuits 505. The sense amplifier 501 includes a bit line pair BLL and / BLL and a bit line pair BLR and / BL.
It is provided corresponding to R. Equalize circuit 503 is provided corresponding to bit line pair BLL, / BLL. The same applies to the equalize circuit 505. The equalize circuit 503 includes NMOS transistors 507, 509, 5
11 and the equalizing circuit 505 includes NMOS transistors 513, 515 and 517. FIG.
The sense amplifier row 27 has the same configuration as the sense amplifier row 25.

Here, in the DRAM, the precharge operation is performed before the memory cell operation, and the potential of the bit line is initially set to 1/2 of power supply potential Vcc (that is, 1/2 Vcc). That is, paying attention to the equalize circuit 503 in FIG. 23, at the time of the precharge operation, the potential of the “H” level is applied to the EQ line 519, and the NMOS transistors 507 to 511 are turned on. Then, ½ from the precharge potential supply line 525 to the bit lines BLL and / BLL.
A potential of Vcc is applied. Here, turning on the NMOS transistors 507 to 511 to equalize the potential of the bit line BLL and the potential of the bit line / BLL is called an equalize operation.

In the conventional DRAM, the potential applied to the gates of the NMOS transistors 507 to 511 during the equalizing operation was at the Vcc level. But DRAM
The equalizing operation has become difficult as the low voltage operation is performed. That is, when the power supply potential Vcc of the DRAM decreases, the NMOS transistors 509 and 511 cannot be turned on sufficiently, and the bit lines BLL and / BLL are not turned on.
Therefore, it becomes impossible to supply the potential of 1/2 Vcc.

Therefore, in the DRAM according to the sixth embodiment, the boosted potential is set to EQ line 519 during the equalizing operation.
Give to. When the threshold voltage of the NMOS transistors 509 and 511 is Vthe, the boosted potential applied to the EQ line 519 during the equalizing operation is (1 / 2Vcc + Vt).
he) level.

FIG. 24 is a schematic block diagram showing a part of a DRAM according to the sixth embodiment. Note that the same parts as those in FIG. Referring to FIG. 24, DR according to the sixth embodiment
AM is a detection circuit D1, ring oscillators 53 and 2
A first boosted potential generation circuit including a Vcc generation charge pump circuit P3, a detection circuit D2, and a ring oscillator 55.
And a 3Vcc generation charge pump circuit P4, a second boosted potential generation circuit, a detection circuit D3, a ring oscillator 531 and a (1/2 Vcc + Vthe) generation charge pump circuit P8, and a BLI driver 61. A word driver 63 and an equalize circuit group 529.

Here, the first, second and third boosted potential generating circuits form boosted potential generating unit 51 of FIG. The DRAM of FIG. 24 differs from the DRAM of FIG. 11 in that the DRAM of FIG. 24 includes a third boosted potential generating circuit. Here, the equalizing circuit group 529 includes a plurality of equalizing circuits, and this equalizing circuit is
For example, the equalize circuits 503 and 505 in FIG.

The operation will be described. The detection circuit D3 is
Boosted potential node (equalized circuit group 529 has a boosted potential V
(Wiring for supplying pp3) The potential level of Npp3 is detected, and when the boosted potential Vpp3 falls to the third level, the ring oscillator 531 is operated to raise the boosted potential V
When pp3 becomes larger than the third level, the operation of the ring oscillator 531 is stopped. (1/2 Vcc +
Vthe) generating charge pump circuit P8 has boosted potential V
When pp3 falls to the third level, boosted potential Vpp3 is generated at boosted potential node Npp3 based on clock signal CLK from ring oscillator 531. (1
/ 2Vcc + Vthe) generation charge pump circuit P8
Is the boosted potential Vp at the level of (1/2 Vcc + Vthe)
can generate p3. Here, Vthe is the threshold voltage of the NMOS transistor that constitutes the equalizing circuit. In addition, a third reference serving as a detection reference in the detection circuit D3.
Is set so that the potential level of boosted potential Vpp3 required by equalizing circuit group 529 can be maintained. For example, the first level serving as a reference for detection in the detection circuit D1 is the 2Vcc level, and the detection circuit D2
The second level serving as the reference for detection in is the 3Vcc level, and the third level serving as the reference for detection in the detection circuit D3 is the (1 / 2Vcc + Vthe) level.

As described above, the first level which is the reference of detection in the detection circuit D1 is smaller than the second level which is the reference of detection in the detection circuit D2. Further, the third level serving as the detection reference in the detection circuit D3 is smaller than the first level serving as the detection reference in the detection circuit D1. Therefore, the boosted potential Vpp1
Is smaller than the boosted potential Vpp2 and is equal to the boosted potential Vpp3.
Becomes smaller than the boosted potential Vpp1.

As described above, the DRA according to the sixth embodiment
In M, there are three different boosting potentials (Vpp1, Vpp).
It has three different boosted potential generating circuits for generating pp2, Vpp3). Therefore, the boosted potential Vpp1 having a magnitude required by the BLI driver 61, that is, NM
When the OS transistors 29 to 43 (FIG. 1) are turned on, the boosted potential Vpp1 is not affected by the threshold voltage.
Can be supplied to the BLI driver 61. Further, the boosted potential Vpp2 required by the word driver 63, that is, the boosted potential Vpp2 not affected by the threshold voltage when turning on the NMOS transistor forming the memory cell is supplied to the word driver 63. it can. Further, the boosted potential Vpp3 having a magnitude required by the equalize circuit group 529, that is, the boosted potential Vpp3 having a magnitude which is not affected by the threshold voltage when turning on the NMOS transistor forming the equalize circuit is set to the equalize circuit group 529. Can be supplied to.

As described above, the DRAM according to the sixth embodiment
Then, the boosted potential of the level required by each of the BLI driver 61, the word driver 63, and the equalizing circuit group 529 can be supplied to each of the BLI driver 61, the word driver 63, and the equalizing circuit group 529. For this reason, it is not necessary to generate an unnecessarily large boosted potential, and wasteful consumption of current can be suppressed. Further, since a boosted potential larger than necessary is not generated, it is possible to prevent the circuit elements (the NMOS transistors 29 to 43 in FIG. 1 and the NMOS transistors 507 to 517 in FIG. 23) from being broken, and improve the reliability.

In the DRAM according to the sixth embodiment,
A first boosted potential generation circuit is provided for the BLI driver 61, a second boosted potential generation circuit is provided for the word driver 63, and a third boosted potential generation circuit is provided for the equalize circuit group 529. There is. Therefore, the operation of the first boosted potential generation circuit is not affected by the operations of the word driver 63 and the equalize circuit group 529, and
The operation of the second boosted potential generation circuit is performed by the BLI driver 61.
Also, the operation of the equalize circuit group 529 is not affected, and the operation of the third boosted potential generating circuit is not affected by the operation of the BLI driver 61 and the word driver 63.

Further, in the DRAM according to the sixth embodiment,
Since all the configurations of the DRAM according to the third embodiment are included,
The DRAM according to the sixth embodiment is a D according to the third embodiment.
It has the same effect as the RAM.

Here, the DRAM according to the first to fifth embodiments is provided with the third boosted potential generation circuit including detection circuit D3, ring oscillator 531 and (1/2 Vcc + Vthe) generation charge pump circuit P8 described above. be able to.

(Embodiment 7) DR according to Embodiment 7
The overall configuration of AM is similar to that of the DRAM according to the sixth embodiment (FIG. 1). However, in the DRAM according to the seventh embodiment, the boosted potential generation unit 51 of FIG.
Boosted potentials Vpp1, Vpp2, Vpp of different levels
3, Vpp4 is generated.

FIG. 25 is a schematic block diagram showing a part of a DRAM according to the seventh embodiment. The same parts as those in FIGS. 1 and 24 are designated by the same reference numerals, and the description thereof will be omitted as appropriate.

Referring to FIG. 25, D according to the seventh embodiment
The RAM includes a first boosted potential generation circuit including a detection circuit D1, a ring oscillator 53 and a 2Vcc generation charge pump circuit P3, a detection circuit D2, and a ring oscillator 5.
A second boosted potential generation circuit including a 5 and 3 Vcc generation charge pump circuit P4, a detection circuit D3, a third boosted potential generation circuit including a ring oscillator 531 and (1/2 Vcc + Vthe) generation charge pump circuit P8, and a detection circuit D4, ring oscillator 533 and (V
cc + Vtho) generating charge pump circuit P9, a fourth boosted potential generating circuit, a BLI driver 61, a word driver 63, an equalizing circuit group 529, and an output buffer 49. Here, the first, second, third and fourth boosted potential generating circuits form the boosted potential generating unit 51 of FIG. The DRAM of FIG. 25 and the D of FIG.
The difference from the RAM is that the DRAM of FIG. 25 includes a fourth boosted potential generating circuit.

The operation will be described. The detection circuit D4 is
Boosted potential node (boosted potential Vpp4 in output buffer 49)
The wiring for supplying Npp4 is detected, and when the boosted potential Vpp4 drops to the fourth level, the ring oscillator 533 is operated, and when the boosted potential Vpp4 becomes higher than the fourth level, the ring oscillator 533 is operated. Oscillator 5
The operation of 33 is stopped. The charge pump circuit P9 is
When boosted potential Vpp4 falls to the fourth level, boosted potential Vpp4 is generated at boosted potential node Npp4 based on clock signal CLK from ring oscillator 553. (Vcc + Vtho) generation charge pump circuit P
9 is the boosted potential Vpp4 at the (Vcc + Vtho) level
Can occur. Here, Vtho is the output buffer 49
Is the threshold voltage of the NMOS transistor that constitutes the peripheral circuit such as. This threshold voltage Vtho is the threshold voltage V of the NMOS transistor forming the memory cell.
larger than thm.

The fourth level serving as a reference for detection in detection circuit D4 is set so that the potential level of boosted potential Vpp4 required by output buffer 49 can be maintained.
For example, the first reference serving as the detection reference in the detection circuit D1
Is a (Vcc + Vthm) level, and the second level serving as a reference for detection in the detection circuit D2 is 3
The third level, which is the Vcc level and is the reference for detection in the detection circuit D3, is the (1/2 Vcc + Vthe) level, and the fourth level, which is the reference for the detection in the detection circuit D4, is the (Vcc + Vtho) level. . Thus, the four levels serving as the reference for detection in the four detection circuits D1 to D4 are different, and the levels of the four boosted potentials Vpp1 to Vpp4 applied to the four boosted potential nodes Npp1 to Npp4 are also different.

FIG. 26 is a circuit diagram showing details of output buffer 49 of FIG. Referring to FIG. 26, the output buffer includes a level conversion circuit 535 and NMOS transistors 537 and 539. NMOS transistor 53
7 and 539 are connected in series between a node supplied with power supply potential Vcc and a node supplied with ground potential. Level conversion circuit 535 converts signal RD to Vpp4 level based on boosted potential Vpp4 when signal RD at Vcc level is input. Then, the level-converted signal RD is applied to the gate of the NMOS transistor 537. The gate of the NMOS transistor 539 is
A signal / RD which is the inverted signal RD is provided. Note that N
The threshold voltage of the MOS transistor 537 is Vtho
It is. Here, the level conversion circuit 535 is similar to the level conversion circuit shown in FIG. However, in the DRAM according to the seventh embodiment, the sources of PMOS transistors 87 and 89 in FIG. 5 are connected to node Npp4 (FIGS. 25 and 26) to which boosted potential Vpp4 is applied. The boosted potential Vpp4 is applied to the gate of the NMOS transistor 537 of the output buffer 49 for the following reason. That is, in the case where multi-bit and high-speed operation are required, a sufficient “H” level signal is output.

As described above, the DRA according to the seventh embodiment
In M, four boosted potentials of different levels (Vpp1, V
Four different boosted potential generating circuits for generating pp2, Vpp3, Vpp4) are provided. Therefore, the boost potential Vpp1 having a magnitude required by the BLI driver 61, that is, the boost potential Vpp1 having a magnitude that is not affected by the threshold voltage when turning on the NMOS transistors 29 to 43 (FIG. 1) is set to the BLI driver. 61 can be supplied. Further, the boosted potential Vpp2 required by the word driver 63, that is, the boosted potential Vpp2 not affected by the threshold voltage when turning on the NMOS transistor forming the memory cell is supplied to the word driver 63. it can. Further, the boosted potential Vpp3 required by the equalize circuit group 529, that is, the boosted potential Vpp3 not affected by the threshold voltage when turning on the NMOS transistor forming the equalize circuit is supplied to the equalize circuit group 529. Can be supplied. Further, boosted potential Vpp4 of a magnitude required by output buffer 49, that is, boosted potential Vpp4 of a magnitude capable of outputting a signal of sufficient "H" level, can be supplied to output buffer 49.

As described above, the DRAM according to the seventh embodiment
Then, the boosted potential of the level required by each of the BLI driver 61, the word driver 63, the equalizing circuit group 529, and the output buffer 49 is supplied to each of the BLI driver 61, the word driver 63, the equalizing circuit group 529, and the output buffer 49. it can. Therefore, it is not necessary to generate a boosted potential larger than necessary, and it is possible to suppress wasteful consumption of current. Further, since a boosted potential higher than necessary is not generated, the circuit elements (the NMOS transistors 29 to 43 in FIG. 1 and the NMOS transistor 50 in FIG.
7 to 517, the NMOS transistor 537 shown in FIG. 26 can be prevented from being destroyed, and the reliability can be improved.

In the DRAM according to the seventh embodiment,
A first boosted voltage generation circuit is provided for the BLI driver 61, a second boosted potential generation circuit is provided for the word driver 63, and a third boosted potential generation circuit is provided for the equalize circuit group 529. A fourth boosted potential generation circuit is provided for the output buffer 49. For this reason,
The operation of the first boosted potential generation circuit is performed by the word driver 6
3, the equalizing circuit group 529 and the output buffer 49 are not affected, and the operation of the second boosted potential generating circuit is not influenced by the BLI driver 61, the equalizing circuit group 529, and the output buffer 49. Three
The operation of the boosted potential generating circuit is not affected by the BLI driver 61, the word driver 63 and the output buffer 49, and the operation of the fourth boosted potential generating circuit is BL
It is not affected by the I driver 61, the word driver 63, and the equalizing circuit group 529. The DRAM according to the seventh embodiment is the DRAM according to the sixth embodiment.
The DRAM according to the seventh embodiment includes all the configurations of
Has the same effect as the DRAM according to the sixth embodiment.

In the DRAM according to the first to fifth embodiments, the detection circuit D3 and the ring oscillator 5 are included.
31 and a (1 / 2Vcc + Vthe) generation charge pump circuit P8, a third boosted potential generation circuit, a detection circuit D4, a ring oscillator 533 and (Vcc + V).
and a fourth boosted potential generating circuit including a charge pump circuit P9.

Here, the boosted potential generating circuit for generating the boosted potential and the boosted potential node (the wiring for supplying the boosted potential to the internal circuit) to which the boosted potential is applied will be referred to as "boosted power supply". In the first to seventh embodiments, the boosting power source is 2
Although there are three, three or four systems, it is also possible to use booster power supplies of a plurality of systems of four or more systems. In this case, the boosted potential levels of all boosted power supplies can be different, or the boosted potential levels of all boosted power supplies can be the same.

Further, one of the plurality of boosting power supplies may supply the boosting potential of the same level, or one of the plurality of boosting power supplies may supply the boosting potential of different levels. Good. Further, the detection level of the detection circuit of the boosting power supply that supplies the boosted potential of the same level is the same. In this case, the capacities of the charge pump circuits of the booster power supplies (the maximum boosted potential that the charge pump circuit can generate) can be the same or different. Further, the detection level of the detection circuit of the boosting power source that supplies different levels of boosted potential is different. Also in this case, the capability of the charge pump circuit of the boosting power supply can be the same or different. Further, any or all of the plurality of boosted power supplies may be switched in capability depending on the level of power supply potential Vcc (see FIGS. 16 and 20).

[0176]

In the dynamic random access memory according to the first aspect of the present invention, a plurality of boosted potential supply lines and a plurality of boosted potential generating means are provided corresponding to a plurality of internal circuits. Therefore, the operation of the boosted potential generating means is not affected by the operation of the internal circuits other than the corresponding internal circuit.

In the dynamic random access memory according to the first aspect of the present invention, the boosted potential generating means generates the boosted potential at the level corresponding to the corresponding internal circuit. For this reason, it is not necessary to generate an unnecessarily large boosted potential, and wasteful consumption of current can be suppressed. Further, since the boosted potential larger than necessary is not applied to the circuit element, the reliability can be improved.

In the dynamic random access memory according to the second aspect of the present invention, the capability of the first boosted potential generating means is switched according to the power supply potential. Therefore, when the power supply potential is small, the capability of the first boosted potential generating means can be increased. Therefore, even if the power supply potential is small, the first boosted potential at the level required by the first internal circuit can be generated based on the power supply potential. On the other hand, when the power supply potential is large, the capability of the first boosted potential generating means can be reduced. Therefore, it is possible to prevent the generation of the first boosted potential that is larger than necessary, and it is possible to suppress the wasteful consumption of current.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing an overall configuration of a DRAM according to a first embodiment of the present invention.

FIG. 2 is a schematic block diagram showing a part of the DRAM according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing details of the charge pump circuit of FIG.

FIG. 4 is a circuit diagram showing details of another example of the charge pump circuit of FIG.

FIG. 5 is a circuit diagram showing details of the level conversion circuit of FIG.

FIG. 6 is a circuit diagram showing details of still another example of the charge pump circuit of FIG.

7 is a timing diagram for explaining the operation of the charge pump circuit of FIG.

8 is a circuit diagram showing details of the detection circuit D1 of FIG.

9 is a circuit diagram showing details of the detection circuit D2 of FIG.

FIG. 10 is a schematic block diagram showing a part of a DRAM according to a second embodiment of the present invention.

FIG. 11 is a schematic block diagram showing a part of a DRAM according to a third embodiment of the present invention.

12 is a circuit diagram showing details of the 3Vcc generating charge pump circuit P4 of FIG. 11. FIG.

13 is a circuit diagram showing details of another example of the 3Vcc generating charge pump circuit P4 of FIG. 11. FIG.

14 is a circuit diagram showing details of still another example of the 3Vcc generation charge pump circuit P4 of FIG. 11. FIG.

FIG. 15 is a timing chart for explaining the operation of the 3Vcc generating charge pump circuit P4 of FIG.

FIG. 16 is a schematic block diagram showing a part of a DRAM according to a fourth embodiment of the present invention.

17 is a circuit diagram showing details of the power supply potential detection circuit of FIG.

FIG. 18 is a circuit diagram showing details of another example of the power supply potential detection circuit of FIG. 16.

FIG. 19 is a circuit diagram showing details of the switch circuit of FIG.

FIG. 20 is a schematic block diagram showing a part of a DRAM according to a fifth embodiment of the present invention.

FIG. 21 is a circuit diagram showing details of the charge pump circuit P7 in FIG.

22 is a circuit diagram showing details of another example of the charge pump circuit P7 of FIG. 20. FIG.

FIG. 23 is a circuit diagram showing details of the sense amplifier array in FIG. 1.

FIG. 24 is a schematic block diagram showing a part of a DRAM according to a sixth embodiment of the present invention.

FIG. 25 is a schematic block diagram showing a part of a DRAM according to a seventh embodiment of the present invention.

FIG. 26 is a circuit diagram showing details of the output buffer of FIG. 1 in Embodiment 7 of the present invention.

FIG. 27 is a schematic block diagram showing a part of a conventional DRAM.

FIG. 28 is a circuit diagram showing details of a memory cell of a conventional DRAM.

FIG. 29 is a schematic block diagram showing another part of a conventional DRAM.

FIG. 30 is a circuit diagram showing details of a memory cell used for explaining the first problem of the conventional DRAM.

FIG. 31 is a diagram showing a relationship between a back gate potential Vbs used for explaining a first problem of a conventional DRAM and a threshold voltage Vthm of an NMOS transistor used for a memory cell.

FIG. 32 is a circuit diagram showing a general boosted potential generation circuit used for explaining a second problem of the conventional DRAM.

FIG. 33 is a diagram showing a relationship between the power supply potential Vcc and the maximum boosted potential Vpp that can be generated by the boosted potential generating circuit of FIG. 32, which is used for explaining the second problem of the conventional DRAM.

FIG. 34 is a diagram showing a power supply for supplying a boosted potential Vpp, which is used for explaining a second problem of the conventional DRAM.

[Explanation of symbols]

1 semiconductor substrate, 3 address signal input terminal group, 5 output pins, 7 address buffer, 9 to 13 row decoder, 15 to 19, 63, 213 word driver, 2
1,23,61,211 BLI driver, 25,27
Sense amplifier row, 29 to 43, 69 to 73, 81 to 8
6,99,101,111,131,137,139,
167,169,197,215,507-517,5
37,539 NMOS transistor, 45 column decoder, 47 preamplifier, 49 output buffer, 51
Boosted potential generation unit, 53, 55, 205, 531
533 ring oscillator, 57, 59, 209 charge pump circuit, 65, 67, 75, 77, 105-1
09, 123, 125, 145, 147, 189, 19
1, 217, 225, 229 capacitors, 79, 13
3,199 level conversion circuit, 87, 89, 103, 1
13, 117, 119, 155 to 165 PMOS transistors, 91, 93, 149, 186, 187, 20
2,203 inverters, 95, 97, 127, 129,
141, 143, 193, 195, 219, 221 diode, 115, 121, 171-175 resistance element, 151 power supply potential detection circuit, 153 switch circuit, 177 constant potential generation circuit, 179 current mirror circuit, 181 logic circuit, 183 185,201 N
AND circuit, 207 detection circuit, 223 oscillator,
227 switches, B1 to B3 memory array blocks, D1, D2 detection circuits, NA, NB, NC nodes, BLL, / BLL, BLR, / BLR bit lines,
BLI0L, BLI0R, BLI1L, BLI1R Bit line separation line, P1, P2, P7 charge pump circuit, P3, P5 2Vcc generation charge pump circuit, P
4, P6 3Vcc generation charge pump circuit, 501
Sense amplifier, 503, 505 Equalize circuit, 51
9,522 EQ line, 525,527 precharge potential supply line, 529 equalize circuit group, 535 level conversion circuit, P8 (1/2 Vcc + Vthe) generation charge pump circuit, P9 (Vcc + Vtho) generation charge pump circuit, Npp1 to Npp4 boosted potential node.

Claims (18)

[Claims] 1. A plurality of internal circuits, a plurality of boosted potential supply lines provided corresponding to the plurality of internal circuits, each of which supplies a boosted potential to the corresponding internal circuit, and the plurality of internal circuits. And a plurality of boosted potential generating means for generating boosted potentials to be provided to the corresponding boosted potential supply lines, wherein the boosted potential generation means are potentials of the corresponding boosted potential supply lines. A dynamic random access memory that generates the boosted potential so that the level becomes a level corresponding to the corresponding internal circuit. 2. The dynamic random access memory according to claim 1, wherein at least two of the plurality of boosted potential generating means generate the boosted potentials of substantially the same level. 3. The boosted potential generating means includes charge pump means for generating the boosted potential, and the capability of the charge pump means for generating the boosted potential at substantially the same level is substantially equal. 2. A dynamic random access memory according to 2. 4. The dynamic random access memory according to claim 1, wherein at least two of the plurality of boosted potential generating means generate the boosted potentials at different levels. 5. The boosted potential generating means detects the potential level of the corresponding boosted potential supply line, and applies the boosted potential applied to the boosted potential supply line to the corresponding internal level according to a predetermined detection level. 5. The dynamic detection circuit according to claim 4, wherein the predetermined detection level is different in the boosted potential generating means for generating the boosted potential at different levels, the detection means maintaining a level corresponding to a circuit. Random access memory. 6. The boosted potential generating means further includes charge pump means for generating the boosted potential, and the capability of the charge pump means for generating the boosted potentials at different levels is substantially equal. The described dynamic random access memory. 7. The dynamic mode according to claim 5, wherein the boosted potential generating means further includes charge pump means for generating the boosted potential, and the charge pump means for generating the boosted potentials at different levels have different capacities. -Random access memory. 8. The charge pump means generates the boosted potential by performing a boosting operation on a power supply potential to generate the boosted potential at different levels. 8. The dynamic random access memory according to claim 7, wherein the number of times of applying is different. 9. At least one of the plurality of boosted potential generation means includes a power supply potential detection means for detecting a level of a power supply potential, and the boosted potential generation means including the power supply potential detection means has the capability of: 5. The dynamic random access memory according to claim 4, wherein the dynamic random access memory is switched according to the detection result of the power supply potential detecting means. 10. The boosted potential generating means including the power supply potential detecting means further includes a plurality of charge pump means for generating the boosted potential, wherein the charge pump means have different capacities, and 10. The dynamic random access memory according to claim 9, wherein the higher the level, the smaller the capacity of said charge pump means operates, and the lower the level of said power supply potential, the larger said capacity of said charge pump means operates. 11. The boosted potential generating means including the power supply potential detecting means further includes charge pump means for generating the boosted potential, and the charge pump means performs a boosting operation on the power supply potential. The boosted potential is generated, and the higher the level of the power supply potential, the smaller the number of times of the boosting operation, and the lower the level of the power supply potential, the greater the number of times of the boosting operation. Dynamic random access memory. 12. A dynamic random access memory having a plurality of operation modes, comprising: a first internal circuit; and a first boosted potential supply for supplying a first boosted potential to the first internal circuit. Line, and a first boosted potential generating means for generating the first boosted potential to be applied to the first boosted potential supply line, wherein the first boosted potential generating means is configured to supply the first boosted potential supply. The first boosted potential generating means generates the first boosted potential so that the potential level of the line becomes a level corresponding to the first internal circuit, and the first boosted potential generating means detects the level of the power supply potential. Power source potential detecting means, the capability of the first boosted potential generating means is switched according to the detection result by the first power source potential detecting means regardless of the plurality of operation modes.
Access memory. 13. The first boosted potential generating means further includes a plurality of charge pumping means for generating the first boosted potential, the charge pumping means having different capacities, and the power supply potential level. 13. The dynamic random access memory according to claim 12, wherein the higher the value, the smaller capacity the charge pump means operates, and the lower the level of the power supply potential, the larger capacity the charge pump means operates. 14. The first boosted potential generation means includes charge pump means for generating the first boosted potential, and the charge pump means performs a boosting operation on the power supply potential, 13. The first boosted potential is generated, and the higher the level of the power supply potential, the smaller the number of boosting operations, and the lower the level of the power supply potential, the larger the number of times of the boosting operation. Dynamic random access memory. 15. A second internal circuit, a second boosted potential supply line that supplies a second boosted potential to the second internal circuit, and a second boosted potential supply line that supplies the second boosted potential supply line to the second boosted potential supply line. A second boosted potential generating means for generating a boosted potential, wherein the second boosted potential generating means is such that the potential level of the second boosted potential supply line corresponds to that of the second internal circuit. 13. The dynamic random access memory according to claim 12, wherein the second boosted potential is generated as follows. 16. A plurality of second internal circuits, and a plurality of second internal circuits provided corresponding to the plurality of second internal circuits, each supplying a second boosted potential to the corresponding second internal circuit. A second boosted potential supply line and a plurality of second internal circuits, each of which generates the second boosted potential to be applied to the corresponding second boosted potential supply line. Second boosted potential generating means, wherein the second boosted potential generating means sets the potential level of the corresponding second boosted potential supply line to a level corresponding to the corresponding second internal circuit. 13. The dynamic random number according to claim 12, wherein the second boosted potential is generated so that
Access memory. 17. The second boosted potential generating means includes second power source potential detecting means for detecting the level of the power source potential, and the capability of the second boosted potential generating means is the second power source potential. 16. The dynamic random access memory according to claim 15, wherein the dynamic random access memory is switched according to a detection result by the detection means. 18. At least one of the plurality of second boosted potential generating means includes second power source potential detecting means for detecting a level of power source potential, and the second power source potential detecting means is included. 17. The dynamic random access memory according to claim 16, wherein the capacity of the second boosted potential generating means is switched according to the detection result by the second power supply potential detecting means.