WO2004081945A1 - Semiconductor storage device and semiconductor storage device control method - Google Patents

Semiconductor storage device and semiconductor storage device control method Download PDF

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Publication number
WO2004081945A1
WO2004081945A1 PCT/JP2003/003128 JP0303128W WO2004081945A1 WO 2004081945 A1 WO2004081945 A1 WO 2004081945A1 JP 0303128 W JP0303128 W JP 0303128W WO 2004081945 A1 WO2004081945 A1 WO 2004081945A1
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WO
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Prior art keywords
bit line
ikoraizu
voltage
line
memory device
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PCT/JP2003/003128
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French (fr)
Japanese (ja)
Inventor
Kazufumi Komura
Yoshiharu Kato
Satoru Kawamoto
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Fujitsu Limited
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4094Bit-line management or control circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2207/00Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/005Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines

Abstract

A semiconductor storage device in which equalization of a bit line can be carried out with low power consumption while maintaining a normal access speed and a normal chip area and its control method are disclosed. In a shared sense amplifier semiconductor storage device, a bit line separation gate of a non-selected memory block is made conductive predetermined number of selections equal to or fewer than (k-1) out of continuous k selections of word line in a selected memory block during the active period of an equalizing section after a word line is selected. The circuit for equalizing the interconnection of high load component is driven with a higher voltage level depending on the load component of the interconnection between the sense amplifier power supply line and the bit line, and as a result the power supply line and the bit line are equalized in equivalent times, thereby preventing the short-circuit in the sense amplifier.

Description

The method art bright fine manual semiconductor memory device, and a semiconductor memory device

The present invention relates to a semiconductor memory device and a control method thereof, to a semiconductor memory device and a control method thereof for Improving the especially Ikoraizu operation of bit lines. BACKGROUND

Dynamic random access memory (hereinafter, abbreviated as DRAM) in a semiconductor memory device such as, share one de sense amplifier system to share one sense amplifier group in the two memory blocks is intended to be used. In this case, in order to separate the bi Uz preparative line and the sense amplifier in the memory block that is not selected, bit line isolation gates (BT) is provided.

First 0 is a diagram showing a part of a shared sense amplifier system. Between the bit lines BLZ complementary bi Uz preparative line BLX been connected the sense amplifier S / A, and are shared by the memory blocks BLK 1, BLK 2 adjacent each. Isolation gate B TL, BTI or connected between each corresponding memory block B LK 1, BLK 2 and the sense amplifier S / A, and the corresponding separation gate Ichito control signal sb 1 t 1 X and sb 1 tr X in response, it performs the conduction / non-conduction. Incidentally, Ikoraizu bits lines is performed by Ikoraizu circuit 1 50 provided in the sense amplifier side.

Here, it is sometimes used in place of the alternative sense amplifiers S / As shown in the first 0 Figure the sense amplifier S / A. In the foregoing of the sense amplifier S / A, with an internal step-down voltage V cc is supplied to the sensor Suanpu active lines PSA, is supplied with the ground voltage V ss to Sen Suanpu active line NSA, the sense amplifier SZA is a Akuti flop state is that structure. On the other hand the alternative sense amplifiers S / A s, alternative to the transistor T r 9 of the low-level sense amplifier signal LEX, sometimes alternatively Sensuanpu activity signal LEZ high level to the transistor T rl O is input, alternatively the sense amplifier S / As Vc c and V ss is a structure that is Akutibu state is supplied to.

The first 1 figure Ru der Thailand Mi ring chart showing a self-refresh operation. The self-refresh rice one enable signal SREFE "self-refresh operation in response to high ,, Reperu (§ active) is performed. Proc BL during the period in which the K 1 self refresh control signal sb 1 t 1 to x" Ha connection maintained at I "level, the isolation gate BTL is conductive, bi Uz preparative lines BL LZ in proc B LK 1, bit lines BLZ that BLLX the sense amplifier S / a is connected, and a B LX ever. that period, Wa one word line sw 10, sw 1 1 in response to the "mouth one" level transition of ZR AS an internal RAS signal, ... are sequentially activates, bit line BLLZ, the B LLX as well as list §, / "high" Reperu transition word line sw 10 in response to the RAS, swl l, bit line BL LZ and ... in a non-active, and I co-rise the BL LX.

The separated gate one preparative BTR unselected Purodzuku B LK 2 side, / RAS is at an interval of "Ha I" level, i.e., at an interval of bit lines BLK 1 is Ikoraizu, the control signal sbit rx is a "high" level separation gate BTR is conductive. Thus, unselected Proc BLK 2 bits lines BLRZ, BLRX is bit line BL Z, is Ikoraizu connected to BLX. When self-refresh block B LK 2 Conversely, the same Ikoraizu control over Purodzuku B LK 1 is performed. By performing the same operations following contrast thereto the proc, self-refresh is completed for all memory cells.

On the other hand, as disclosed in Patent Document 1, 2, in the control shown in the first FIG. 2, during the refresh period of the selected proc side memory cell is always a control signal for separating the gate of the unselected flop-locking side " keep a low "level. Therefore, the bi Uz preparative lines of the sense amplifier S / A and the non-selected block side not connected during Ikoraizu period selection Proc. Each Ikoraizu selection proc, unlike the case of the first 1 view unselected proc is connected, unselected plot that sweep rate Tsuchingu operation of separation gate Ichito connected to click is performed rather than charge and discharge reduction of the current can be achieved.

In the semiconductor memory device disclosed in Patent Document 3, 4, for each Memoripurodzuku separated sense amplifier pit line isolation gate one bets is provided with a bit line Ikora I's circuit. Therefore, even in a period in which bit lines between the unselected memory block and Sensua pump is non-conductive, is Ikora I's operation using the bit line Ikoraizu circuit provided in Hisen-option memory Proc to be done, it is possible to prevent the shift of electric position due to floating of the bi Uz preparative line potential.

In the first 0 views, a bit line Ikoraizu control signal BRS, and the Ikoraizu control signal BRSS of cell Nsuanpu active line PSA / NSA, are both controlled with the boosted voltage V p and the ground voltage V ss. Increasing the driving capability of the Ikorai's transistor by driving the boost voltage V pp boosted from an external power supply voltage V dd, that with the aim of shortening the Ikoraizu time.

Further, in recent semiconductor memory devices, for improve the sensitivity of the relative speed or the accumulated charges of the list § operation by the sense amplifier, which may constitute short bit line length. Thus small wiring capacitance of bit Bok line no longer, with a reduction in current consumption during restore, shorter Ikoraizu time can be achieved.

Incidentally, illustrating the prior art documents below.

Patent Document 1 JP-A-9- 1 6 1 4 7 7 No.

Patent Document 2 JP-A-1 0 2 2 2 9 7 7 No.

Patent Document 3 JP-8 - 1 5 3 3 9 1 JP

Patent Document 4 JP 9 one 4 5 8 7 9 No.

As a problem, problems related to the control of bi Uz preparative line isolation gates of the unselected proc First include issues Ikoraizu control in the second.

It describes the problems related to the control of the bit line isolation gate Ichito. First 0 views, in the first 1 view, in the case of the memory proc BLK 1 a self-refresh operation of a selected block, / RAS is at an interval of Ikoraizu operation as a high level, the unselected Purodzuku BLK 2 side isolation gate one DOO control signal sb 1 trx of BTR becomes high. Thus for sweep rate Uz quenching operation of the separation gate BTR is repeated every Ikoraizu period, a discharge current increases problem.

Further, in the semiconductor Symbol billion device is provided with bit lines Ikoraizu circuit for each Memoripurodzu click separated the sense amplifier bit line isolation gate, the isolation gates of the unselected proc as shown in the first 2 FIG non as is also maintained in the conductive state, bit line potential of the non-selected proc never deviate potential becomes Furotei ring state. But like the Ikoraizu circuit 1 5 0 of the first 0 view, compared to the circuit configuration Ikoraizu circuit is provided in the sense amplifier, components in the circuit configuration that are equipped with bi Uz preparative line Ikoraizu circuit for each memory Plock the number is increased. In the semi-conductor memory device includes a plurality of bit lines, increase in the chip area occupied by that by the components increase in bit line Ikoraizu circuit is problematic.

Then describe the problems with the Ikoraizu control. In the circuit of the first 0 views, bi Uz preparative line Ikoraizu control signal BRS and the sense amplifier reduces the current consumption by the driving amplitude of Ikoraizu control signal BRSS active lines PSA / NSA, and the booster circuit for generating a boosted voltage V pp (not order to lower the reduction of current consumption in the illustrated), the drive amplitude and the boosted voltage V pp from between the ground voltage V ss, it is also conceivable to change the internal step-down voltage V cc to the inter-ground voltage V ss. However, while as shown in this case the first FIG. 3, a lack of I co-rise transients scan evening of i-ku, dynamic capability, between the sense amplifier activation line PSA and NSA, between the bit lines BLZ and BLX Ikoraizu end time is likely to arise as extending from T 1 to T 2. As a result, not Ryose End is Ikoraizu operation cycle time, a possibility is a problem that destruction of data occurs. In order not to cause the destruction of Isseki de, it is necessary to relax the specifications of the cycle time in accordance with the decrease in Ikoraizu speed access operation speed is an issue to decrease.

Therefore, consider a case where the speed of Ikora I's rate wiring capacitance and low capacity by shortening the bit line length. In this case the sense amplifier line PS

A, since the wiring capacitance of the NSA is unchanged, as shown in the first 4 figures, Sen Suanpu active line P SA, and between N SA, bit lines BLZ, time difference of I Koraizu operation of the inter BLX is generated , there is a possibility that short circuit abnormal current flows through the evening transistors of the sense amplifier. Compared to the sense amplifier lines PSA, NSA voltage Repe Le is the source terminal voltage of the sense amplifier transistors, bit lines BLZ a gate terminal voltage, the voltage level of BLX, apart than the threshold voltage and thus there is a period of time. As a result, a problem not Hakare to reduce the current consumption.

In the first 0 views, instead of the sense amplifier S / A, and it describes the problem when using alternative Sensua pump SZA s. If the memory block BLK 1 is a selected proc, bi Uz preparative lines BLLZ in the memory block BLK 1, and Ikoraizu end time of BLLX, and Ikoraizu end time bicycloalkyl Uz preparative lines BL Zs BLX connected sense amplifier there are cases where the time difference arising between.

Bit lines BLLZ, BL LX is Ikoraizu is via isolation gate one preparative BTL. Moreover, the separation gate BTL is sometimes requested either et transistor sizes on integration of devices is limited, due to the influence of the on resistance, it may take time to Ikoraizu through the isolation gate. Then, because the specifications of the cycle time in accordance with the slowest Ikoraizu time is determined, when Ikoraizu time difference exists, which is the original performance is difficult becomes the problem of originating volatilizing the semiconductor memory device.

The present invention has been Do to eliminate one at least of problems of the prior art, while maintaining the normal access operation speed and chip area is Ikoraizu operation of bit lines with low current consumption a semiconductor memory device capable of, and an object thereof to provide a control method thereof. Disclosure of the Invention

In the semiconductor memory device according to claim 1 which has been made in order to achieve the object, the stored information is read out to the bit line in accordance with Wado lines selected, and the first and second memory blocks, the first and and a sense amplifier is shared by every second memory proc first and second bit lines in a first separation gate Bok for controlling the connection and separation between the first bit line and the sense amplifier , and a Ikoraizu unit for Ikoraizu the second bi Uz preparative line.

In the semiconductor memory device according to claim 1, when § access operation is performed on the second memory proc, in k times a given number of (k-1) times or less of Wado line selection of successive, selected word line the active period of Ikoraizu portion after, Ru first separation gate and the first bi Uz preparative line and the sense amplifier is in a connected state.

Further, in the control method of the semiconductor memory device according to claim 1 3, when the access operation is performed on the second memory Purodzuku, the second bi Uz DOO line, the subsequent squirrel Ta operation and thereafter Wado line selection Ikoraizu a selection proc accessing step operation is repeated continuously, in the k times of (k _ l) times following I Koraizu operation of a predetermined number of times in the selected block accessing step, and a first bi Uz preparative line and the sense amplifier and a non-selected block I copolymers rise step shall be the connected state.

Thus, by decreasing the first Sui etching times of separation gates of the unselected blocks, the reduction of the charging and discharging current due sweep rate Tsuchingu operation may FIG Rukoto.

In the semiconductor memory device according to claim 2, in the apparatus according to claim 1, also in the control method of the semiconductor memory device according to claim 1 4, in the control method of the semiconductor memory device of the mounting serial to claim 1 3, a second isolation gate for connecting the second bit Bok line and the sense amplifier in response to the access operation time period for said second memory proc, Ikoraizu section, the second main Moripurokku side or the sense amplifier to the second separation gate characterized in that it is arranged on one or both the sides less. Thus, the second isolation gate by performing the placement of Ikoraizu portion in accordance with the period for connecting the second bit line and the sense amplifier, can Ikoraizu the first bit line by Ikoraizu unit. That is, lever is connected and a second bi Uz preparative line and the sense amplifier in the I Koraizu period in addition to Wado line selection, other Ikoraizu unit sense amplifier side, even if placed in the second memory Proc side good.

In the semiconductor memory device according to claim 3 is the device of claim 1, activation of the first isolation gate, in the second Memoripurodzuku, § address identifies the k book Wado rays selected consecutively but it characterized in that it is performed in response to a predetermined logical combination. In the control method of the semiconductor memory device according to claim 1 5, in the control method of the semiconductor memory device according to claim 1 3, connection between the first bit line and the sense amplifier, the selected pro click access step of Adoresu identify the word line selecting consecutive k times, characterized by being performed in accordance with predetermined logic combination. The apparatus according to claim 1 in the semiconductor memory device according to claim 4, activation of the first separation gate, the Adoresu identify the first 2 k book Wa one word line to be selected in succession in a memory block in contrast, 1-bit upper § dress characterized by being performed in response to a transition of the logic state. Further, in the control method of the semiconductor memory device according to claim 1 6, in the control method of the semiconductor memory device according to claim 1 3, connection between the first bit line and Sensua pump is selected pro brute access stearyl Uz 1 bit higher Adoresu against identifies Adoresu the k times Wa one word line selected in a continuous in-flop, characterized in that takes place in response to changes logic states.

Accordingly, the first isolation gate one Bok of sweep rate Tsuchingu number of unselected proc above, or the number of connections between the first bit line and the sense amplifier can be set to a desired number of times.

In the semiconductor memory device according to claim 5, in the semiconductor memory device according to least what Re one wherein also of claims 1 to 4, and the control method for semi-conductor memory device according to claim 1 7, claim 1 a method of controlling a semiconductor memory device according to least any one even of 3 to 1 6, the access operation of the second memory block is a re full les Mesh operation, the address for selecting a word line of k the consecutive it is characterized in that it is a refresh address. In the semiconductor memory device according to claim 6, in the semiconductor memory device according to least any one also of claims 1 to 4, and the control method of the engagement Ru semiconductor memory device according to claim 1 8, claim a method of controlling a semiconductor memory device according to 1 3 to 1 6 least what Re one paragraph also show, the access operation of the second memory pro click is a continuous Akusesu operation including the switching of Wado line, continuous k Adoresu selecting a book Wado line is characterized by mouth one address or a part thereof.

Thus, the sweep rate Tsuchingu number or the first isolation gate for controlling the number of connections between the first bit line and the sense amplifier unselected proc, there is no need to enter or generate dedicated Yui timing signal .

In the semiconductor memory device according to claim 7, when amplifying a plurality of sense amplifiers provided a storage information to be read bit line for each bit line, the two power supply connected in common to a plurality of sense amplifiers It includes a sense amplifier unit for supplying a power voltage to the supply line, a first Ikoraizu unit for Ikoraizu activity turned into the power supply line by a first voltage, bit line and by Ri activated in the second voltage the that have a second Ikoraizu unit for Ikoraizu.

In Ikoraizu operation after amplification, as well as cutting off the power voltage supply to the power supply line by the sense amplifier section, in activating the first and second Ikorai's unit, as compared with the wiring load components of the power supply line , when the wiring load component of bit lines is small, the first voltage, a higher voltage level than the second voltage, as compared with the wiring load components of the power supply line, the bit line wiring load formed If the amount is a dog, the first voltage, by the voltage level lower than the second voltage, the power supply line and bit 1, and a line, Ru is Ikoraizu equivalent time.

Control method of the semiconductor memory device according to claim 1 9, when amplified by a plurality of sense amplifiers provided with stored information to be read bit line for each bit line are connected in common to a plurality of sense amplifiers that the supply voltage is the control method of the semiconductor memory device is supplied to the two power supply lines.

A voltage supply interrupting step for interrupting the supply voltage supply to the power supply line, bi Uz wiring load component bet line becomes small if compared to the wiring load components of the power supply line, power supply line is controlled by the first voltage while being has been Ikoraizu, bit lines are controlled by a second voltage lower voltage level than the first voltage is Ikoraizu while wiring bit lines than the wiring load components of the power supply line If the load component is a dog, with the power supply line is controlled by the first voltage Ikoraizu, human 'Tsu preparative line is Ikoraizu is controlled by a second voltage of a voltage level higher than the first voltage it, the power supply line and bit line, and having an I co rise steps are Ikoraizu in comparable time.

Thus, in accordance with the respective wiring load components, first, because it is I Koraizu by the second voltage, it is not a deviation occurs in Ikoraizu time. For this reason, it is possible to solve the problem through my Rungis evening of the sense amplifier is Ruosore flow is abnormal current of show me, it can reduce current consumption. Further, the voltage value of the first voltage and the second voltage than when the same, in the present invention it is possible to further reduce either the voltage of the first voltage and the second voltage, high have control voltage it is possible to reduce power consumption as compared with the case of.

In the semiconductor memory device according to claim 8, in the device according to claim 7, the bit line, to the outer bit line portion and the storage information inside bit line portion is Desa read connected to the sense amplifier comprising a separation gate that separates, second Ikora I's section is arranged Te either one cities and small outer Ikoraizu unit provided inside Ikoraizu portion provided on the inner bit line portion or outside bit line portion, it is characterized in.

Ikoraizu operation is performed inside bit line portion, or the outer bit line portion least either one as a starting point.

In the control method of the semiconductor memory device according to claim 2 0, in the control method of the semiconductor memory device according to claim 1 9, and the inner bit line section bit line is connected to the sense amplifier, stored information If read configured with an outer bit line section is, it co rise step, characterized that you performed inner bit line portion, or one outer bi Uz DOO line of least either as a starting point to.

Thus, Ru der can be appropriately combined arrangement of Ikoraizu portion. In this case, it is possible to select the combination to reduce the area occupied by the Ikoraizu section, thereby is reducing the chip area.

In the semiconductor memory device according to claim 9, amplified by a plurality of sense amplifiers provided a storage information to be read bit line for each bit line, the sense amplifier section for controlling the supply of power supply voltage for each sensor Suanpu It is equipped with a.

Then, the bit line, and a separation gate that separates the outer bit line portion and memorize information inside bit line portion is read out to be connected to the sense amplifier, the inner bit line section activated by the first voltage an inner Ikoraizu unit for Ikoraizu a activated by the second voltage, and a outer side Ikoraizu unit for Ikoraizu the outer bit line portion.

In Ikoraizu operation after amplification, as well as cutting off the power voltage supply by the sense amplifier section, in activating the inner and outer Ikoraizu portion, as compared with the wiring load components of the inner bit line portion, the outer bit line If the wiring load ingredient parts becomes small, the first voltage, a voltage level higher than the second voltage, as compared with the wiring load components of the inner bit line portion, the outer bit line portion wiring load If Ingredient becomes large, the first voltage, by the voltage level lower than the second voltage, the inner and outer bit line portion, are Ikoraizu in comparable time.

Further, in the control method of the semiconductor memory device according to claim 2 1, after connecting the outer bit line portion and the inner bit line portion, a storage information Ru read outside bit line portion, the inner bit with amplification step you amplified propagates to the sense amplifier through the door line portion. Furthermore, have you to Ikoraizu operation after amplification step, as compared with the wiring load components of the inner bit line portion, when the wiring load component of the outer bit line portion becomes small, the inner bit line portion, the first voltage is controlled by the while being Ikoraizu, outer bit line section is controlled by a second voltage of a low voltage level than the first voltage is Ikoraizu, whereas, the wiring load components of the inner bit line section compared, if the wiring load component of the outer bit line portion dogs ing, the inner bit line section is controlled by the first voltage Ikoraizu is Rutotomoni, the outer bit line portion, a ratio to the first voltage by being Ikoraizu it is controlled by the second voltage of the higher voltage level and, the inner and outer bit line portion, and I co rise step is Ikoraizu at comparable time, characterized by having a to.

Thus, by inner and outer bit line portion is Ikoraizu in comparable time, it is possible to solve the problems that may not be realized original operation performance is rate-limiting the longer the the Ikoraizu time. Further, the voltage value of the first voltage and the second voltage than when the same, in the present invention it is possible to further reduce either the voltage of the first voltage and the second voltage, high have control voltage it is possible to reduce power consumption as compared with the case of. In the semiconductor memory device according to claim 1 0, in the semi-conductor memory device according to claim 8 or 9, bit lines is more differential amplifier in the sense amplifier to two as a pair, the inner and outer Ikoraizu portion It is provided with a short section of the short inner and outer bit line portion the pair, the inside or either one also less of the outer Ikoraizu section, the inner or outer bit line portion Ikoraizu voltage and it features further comprising a bias unit for Baiasu.

Further, in the control method of the semiconductor memory device according to claim 2 2, short in the control method of the semiconductor memory device according to claim 2 0 or 2 1, the Ikoraizusu step, the inner and outer bit line portion pairs and having a short step, and a bias step of biasing the least Ikoraizu voltage either be of the inner or outer bit line section for. Thus, the short portion or short step, in terms of the short bit lines forming a pair, Baiasu unit provided as appropriate, or by bi Asusuteppu, maintain a short has been bi Uz preparative line pair Ikoraizu voltage can do.

In the semiconductor memory device according to claim 1 1, in the semiconductor memory device according to claim 7, the first Ikoraizu unit comprises a least one M 0 S transistors Sennyo between the power supply line, the M 0 S transistor is characterized in that the first voltage is activated to conduct by being applied to the gate one bets terminal.

In the semiconductor memory device according to claim 1 2, in the semiconductor memory device according to least one of claims either be of claims 7 to 1 0, second Ikoraizu portion, or inner Ikoraizu portion and outer Ikoraizu unit, bit line or to connect between the inner bit lines and a source of outside bit lines and Ikoraizu voltage, one MOS transistor at least, or bit line, or the inner bi Uz preparative lines and outer bit, DOO line connecting the line if configured as two pair of one of the MOS transistors at least less and comprise either even, the MOS transistor, the second voltage is applied to the gate terminal It conducts by being characterized in that it is activated.

Thus, according to the first or the second voltage is applied to the gate terminal, it is possible to adjust the driving power required Ikoraizu. It is also possible to combine appropriately the MOS transistors evening number and arrangement of the Ikorai's part. In this case, it is possible to select a combination to reduce the area occupied by the Ikoraizu section, thereby is reducing the chip area. BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a semiconductor memory device of the first embodiment, and shows a part of the shared sensor Suanpu scheme.

Figure 2 is a control circuit diagram of the isolation gate of the unselected memory proc in the first embodiment. Figure 3 is a tie Minguchi yer Bok representing the operation of the semiconductor memory device of the first embodiment.

Figure 4 is a Ikoraizu time between the bit lines of the first embodiment, and shows the relationship between Ikoraizu time between Sensua pump activity line.

Figure 5 is a semiconductor memory device of the second embodiment, showing a part of the shared sensor Suanpu scheme.

Figure 6 is a semiconductor memory device of the third embodiment, showing a part of the shared sensor Suanpu scheme.

Figure 7 is a semiconductor memory device of the fourth embodiment, showing a portion of a share one Dosen Suanpu scheme.

FIG. 8 is a semiconductor memory device of the fifth embodiment, showing a part of the shared sensor Suanpu scheme.

Figure 9 is a Ikoraizu time between the inner bit line of the sixth embodiment, showing a relationship between Ikoraizu time between the outer bit line.

First 0 is a diagram showing a part of a share one de sense amplifier system of the prior art.

The first 1 figure timing represents the operation of a prior art semiconductor memory device Chiya - a preparative.

The first FIG. 2 is a second timing Guchiyato showing the operation of the prior art semiconductor memory device.

The first 3 figures and Ikoraizu time between prior art bit line, a diagram showing the relationship between Ikoraizu time between Sensuan flop actinic.

The first 4 figures and Ikoraizu time between prior art bit line, a second graph showing the relationship between Ikoraizu time between Sensuan flop actinic. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, the semiconductor memory device of the present invention, and embodying an embodiment for the control method in detail with reference to the drawings in Figure 1 to Figure 9 described

_ 9 Ru. Figure 1 is a semiconductor memory device of the first embodiment, and shows a part of the shared sensor Suanpu scheme. Control of separation gate one preparative unselected memory proc, and is an embodiment relating Ikoraizu control bits lines. First method of controlling bit line isolation gate Ichito will be described. In share one de sense amplifier system, in order to separate the bi Uz Doo line is peak Uz preparative lines and cell Nsuanpu in the memory block not selected lead is provided with a bi Uz preparative line isolation gate. Isolation gate BTL connects the memory proc BLK 1 bit line BLLZ ヽ BLLX and pit lines BLZ connected to the sense amplifier S / A, and B LX. Similarly separation gate Bok BTR connects bit line B LR Z, B LRX and bit lines BLZ, and B LX. Here, bit line isolation gate B TL- BTR bit lines BLZ sandwiched between an inner bit line portion BLX, bit lines BLL Z, BL LX and B LR Z, the outer bit and B LRX and it may be referred to as bets line portion.

The BLT generating circuit 1 03 address Ad d identifying the memory block, the signal BT and nZk activation control signal ø for controlling the bit line isolation gate one: it is inputted, bit line isolation gate control signal as an output sbitlx and sblt rx is output. Separating gate one preparative B TL, B TR is, NMO S preparative Rungis is composed of evening, conductive when the bit line isolation gate Ichito control signal of high level SBLT lx and Sbltr X is input to the separation gate is a mouth first level bit line isolation gate control signal is a non-conductive state when the input.

Accessing a stage before the memory cell, between bi Uz preparative line B LX- BLZ, BLLZ- BLLX and between BLRZ- B LRX I co rise voltage and short-circuit between Vp: must be initialized to r , This is called I co-rise operation of the bit line. Also, it must be initialized similarly Ikoraizu voltage V pr is also between the sense amplifier lines PSA-NS A, which Sensua pump actinic PSA, that NSA of Ikoraizu operation.

Bit line BLX and BLZ are separated Memoripu lock B LK 1, BLK 2 by bit line isolation gate one bets. Its bit line Ikoraizu circuit 1 0 7 bit lines BLZ and BLX are provided, and a NM 0 S transistor T r 6 to T r 8. Bi Uz intercluster line BLZ- BLX are connected via a transistor T r 6, Ikoraizu voltage V pr is connected to the transistor T r 7, via a T r 8 bicycloalkyl Uz preparative lines BLZ and B LX . The gate of the transistor T r 6 to T r 8 is peak Uz preparative line Ikoraizu control signal BR S is connected.

Here, the may be called inner Ikorai's part Ikoraizu circuit provided inside bicycloalkyl Uz DOO line portion, the Ikoraizu circuit provided outside bit line portion and the outer Ikoraizu unit.

PSA / NSA Ikoraizu circuit 1 1 1 is composed of NM_〇 S transistor T r 3 to T r 5, the circuit configuration is the same as bi Uz preparative line Ikoraizu circuit 1 0 7. And gate one Bok transistor T r 3 to T r 5 are, PSA / NSA line Ikoraizu control signal BRSS is connected.

Ikoraizu control signal EQ which is the output of the EQ generator 1 0 8, Inba - evening through the gate 1 0 9 and 1 1 0, the PSA / NSA Ikoraizu circuits 1 1 1 and bit line Ikoraizu circuit 1 0 7 It is input. The sense amplifier activation signal LE from LE generator 1 1 5 is inputted to the S transistor evening T r 2 shed NM, inverted / LE by Invar evening gate is input to the PMOS transistor T r 1.

From EQ generator 1 08, is input to the Ikoraizu control signals mouth first level EQ Gai members evening gate 1 0 9, 1 1 0, Inba Yuge Ichito 1 0 9 high level of the boosted voltage Vp p from the PSA / NSA line Ikoraizu control signal BRSS is, from Inba Isseki gate one sheet 1 1 0 high level bit line Ikoraizu control signal BRS of the boosted voltage V pp or the internal step-down voltage V cc is outputted. Is input to a high level of bit line Ikoraizu control signal BRS Gabi Uz preparative line Ikoraizu circuit 1 0 7, when the NMO S transistor T r 6 conducts bi Uz preparative line BLX and BLZ are shorted simultaneously, NM OS transistor evening T r 7, bit line is initialized by T r 8 is charged to a conductive fine Uz preparative line B LX and BLZ Gai Koraizu voltage Vp r. Similarly, the high level of PSA / NSA line Ikoraizu control signal BRSS is, is input to the PS AZN SA Ikoraizu circuit 1 1 1, the sense amplifier activity line P SA, NSA is initialized to Ikoraizu voltage Vp r .

If memory Proc BLK 1 is selected, the word line sw 10 ... sac Chi any one selected Wa one word line to the connected memory cell charge of the (information), bit line BLLZ or BLLX transmitted to. At this time, the voltage difference between the bit lines BLLZ and BLLX because very small, it is necessary to differentially amplified by Sensuan flop SZA. Sensuan the sense amplifier flop actinic P SA, NS A is connected, it is connected respectively via the transistor T r 1 and T r 2 to the internal step-down voltage V cc and the ground voltage V ss.

The word line swl 0 ... any one selected charge of the memory cells selected Ri by the Wado line of, for reading and differentially amplified by the sense amplifier S / A, and first separation gate BTL is conductive state, isolation gate B TR is non-conductive. Next, the sense amplifier activation signal LE of the high level from the LE generator 1 1 5 is output, the transistor T rl, T r 2 is conductive. Thus with an internal step-down voltage V cc to the sense amplifier lines PSA is supplied, the ground voltage V ss to the sense amplifier line NSA is supplied, the sense amplifier S / A is the Akutibu state. The bit line BLLZ, after restore the BLLX the sense amplifier activation signal LE of the low level from the LE generator 1 1 5 is outputted, Trang Soo evening T rl, T r 2 is nonconductive. Also, the selected word line is between is BLZ- bit lines from BLX inactive, and Ikoraizu between Sensuan flop actinic P SA - NSA is performed by the Ikoraizu control signal EQ at a low level, the next memory reading preparation of the cell charge is completed. In this case, it is necessary to bi Uz preparative line B LRZ- B LRX in Memoriburodzuku BLK 2 unselected is maintained in Ikoraizu voltage Vp r.

Figure 2 is a control circuit of the isolation gate of the unselected memory blocks. Figure 3 is a tie Minguchiya one bets on applying control circuit isolation gate Ichito of FIG. 2 in Figure 1.

Proc BLK 1 in Figure 1 is selected, when the self refresh operation is performed, the word line swl O ... are across the Ikoraizu operation of bit lines B LL Z and BL LX therebetween are sequentially activated . nZk activation control signal ø is, k times bicycloalkyl Uz preparative line Ikoraizu n times of the operation (n ^ k - 1) for the non-selected Proc BLK 2 side of the bi Uz Bok line isolation gate - by activating the Bok BTR is a control signal for bit line BLRZ, the Ikoraizu of BLRX. Plock of the word line sw 10 ... is BLK 1, "m-th Wa - de line of activation → bit line BLLZ and B LLX and Ikoraizu m + 1 knots of Wa one word line activation bit line BLLZ and BL LX of Ikoraizu ... "as that, are sequentially activated while repeating the activation and Ikoraizu of the word line between. Among them, every time the k / n word lines is activated, in Ikoraizu period of the immediately following bit lines, separated gate one preparative BTR is turned. Block: performing an operation on SL and opposite when the BLK 2 performs the selected re deflection Mesh operation. That is, every time the kZn of word lines of the block BLK 2 are activated, in Ikoraizu period of the immediately following bit line isolation gate BTL is conducted.

In Figure 2, showing a generation control circuit of n / k activation control signal ų. In the configuration example of FIG. 2, each isolation gate 1 2 1, BT control circuit 1 23 comprises a logic unit 1 24. In the second figure shows a case of n = k / 2 3, a configuration example in which separate gate one sheet 1 2 1 conducts for each activation of eight Wado lines. From the BT control circuit 1 2 3 when n / k activation control signal ø of Roreperu is input to the bit line isolation gate 1 2 1, the separation gate 1 2 1 is nonconductive, high-level n / k activity when the control signal ø is inputted to the bit line isolation gate 1 2 1, isolation gate 12 1 it is conductive.

The BT control circuit 1 23 is provided is Radzuchi circuit 1 25, the Ryonoichido N 1 ヽ in N 2 NM 0 S transistor is connected between the ground voltage V ss. Node N 1 side of NM 0 S set signal set to have, the NMOS node N 2 side of the series connection is reset signal rst and the control signal norstx is input. Signal ø is when the node N 1 becomes set signal set is a high level of the mouth one level is the ground voltage V ss, a time of access operation in the selected memory Proc. Separation gate Ichito to unselected proc becomes non-conductive. On the other hand the signal becomes high level is when both Risedzu preparative signal rst and control signals norstx is the node N 2 or the ground voltage V ss to the high level. At this time, bit 1 of the selection Memoripurodzu click, a time line Ikoraizu operation, and a timing which matches the control condition at logic 1 2 4 below. Then, the separation gate 1 2 1 to unselected proc becomes conductive.

The lower three logical bits of reflation Uz Gerhard address rfaz 1 to rfaz 3 is Ru is inverted and output from the logic unit 1 2 4 Nan Dogeto 1 2 6. Also from the NOR gate 1 2 7, the logical sum of the Rifuretsushu operation control signals REN and Nan Dogeto 1 2 6 output signal of the control signal is inverted nor S t X is output.

Refresh control signal REN during the refresh operation is mouth first level. In this operating state, the refresh address: rfaz 1 to rfaz 3 is control signal norstx high level from seeing Noageto 1 2 7 when all the high level is outputted. The output of the logic unit 1 2 4 means that the refresh address only once out of eight times going transition is at high level. Control signal NORST X of logic unit 1 2 4 is input to the BT control circuit 1 2 3. Although Risedzu DOO signal rst is set to a high level every Ikoraizu period in the selection Memoripurodzuku, since the control signal norst is not the only high once among the previously described eight Ikoraizu period, (^ signal even in 8 times only once it is not a high level. Thus, only eight Ikoraizu operation diary once isolation gate 1 2 1 is conductive.

Also there is a case where the logic unit 1 2 8 instead of the logic unit 1 2 4 is used. The logical unit 1 2 8 provided with edge detection circuit 1 2 9, refresh operation control signal REN and the refresh address rfaz 4 is input. Refresh operation control signal REN during re off threshold operation Ri mouth first level der, this time the edge detection circuit 1 2 9 is in an operating state.

Refresh address rfaz 4 is a 1-bit upper address against Li full Resshua dress rfaz 1 to rfaz S, rfazl to a logic combination for each of Te to Baie rfaz 3, mouth first level from the high level or state transitions from a low level to a high level. The state according to a transition of a pulse wave of high level from Ejji detecting circuit 1 2 9 is output and input into the BT control circuit 1 2 3 as a control signal Norstx. When both Risedzu bets signal rst and the control signal norstx is node N 2 becomes the high level is the ground voltage V ss, n / k activation control signal ø is the High Level, the separation gate 1 2 1 conductive state It is. Therefore, even if the logic unit 1 2 8 is used, only separated Gate 1 2 1 once every eight Ikoraizu operation is conductive.

In this manner, by using the refresh address to the control of the separation gate, there is no need to enter or generate new dedicated evening Lee timing signal. It shows a timing chart in Figure 3. Self reflation Dzushu operation is performed in response to "high" level of self refresh rice one enable signal SREFE (active). During the block BLK 1 is self-refresh, the control signal sb 1 t 1 X is maintained at a "high" level, the separation gate - DOO BTL is conductive, the bit line BLLZ block BLK 1, and BLLX bit lines BLZ, continue to be connected and BLX. That period, / RA "low" in response to the level transition Wa one lead wire sw 1 0 ... are sequentially activated S is accessing the memory cell, BLLZ, squirrels BL LX Thoas Rutotomoni, / RA S is a "high" level transition in response Wado lines sw 1 0 ... are sequentially inactivated of bit lines BLLZ, BLLX is Ru is Ikoraizu.

Each activation of the eight Wado lines contiguous ends, in subsequent Ikoraizu period, bit line isolation gate control signal sb 1 tr X is a single "high" level, the separation gate BTR conduction is a state, bit line B LR Z, BLRX are connected bit lines BLZ, the B LX. Then, the selected block: B LK 1 bits lines BLLZ, with BLLX is Ikora I's, unselected Purodzuku B LK 2 bits lines BLR Z, BL

RX is also Ikoraizu.

Each Ikoraizu period selected Purodzuku B LK 1, as compared with the prior art of the first 1 view control signal sb 1 tr X isolation gate Ichito unselected Purodzuku BLK 2 side is set to the "high" level, the 3 in the first embodiment shown in FIG, more reducing the Suidzuchingu number of separate gate Ichito unselected proc 1/8, reduction of the charge and discharge current by sweep rate Tsuchingu operation it is Ru divided to achieved.

Also the use of the control method of separating the gate of the first embodiment shown in FIG. 3, without providing the bi Uz preparative line Ikoraizu circuit to both the memory block BLK 1, BLK 2, as in Figure 1 be a circuit configuration including the bit line I Koraizu circuit to the sense amplifier S / a-side, it is possible to solve the problem by floating bicycloalkyl Uz preparative line potential. Therefore the low current consumption operation while suppressing the increase in chip area, it is possible and child solve floating bits line potential problem.

Of course, the activation frequency of the activation control signal ø separation gate is not limited to 1/8 of the value used in the first embodiment form state, it is possible appropriately optimized according to each of the semiconductor memory device needless to say.

The Adoresu is not limited to Li Furetsushua dress, for example, during continuous access burst operation or the like to be input to the edge detection circuit 1 2 9 of NAND gate 1 2 6 and logical unit 1 28 of the logic section 1 24 of FIG. 2 of Adoresu it can also be used. a. At this time, the signal input to the Noage Ichito 1 27 and the edge detecting circuit 1 2 9 instead of the Li-off threshold operation control signal REN, a continuous access control signals.

Next, in the first embodiment, a description will be given of a control method of Ikoraizu circuit.

And the voltage of the control signal BR S that controls the bit line Ikoraizu circuit 107, and a voltage of the control signal BRSS for controlling the P SAZNSA Ikoraizu circuit 1 1 1, be set according to the wiring capacitance should each Ikoraizu, suppressed and between bit lines BL Z-B LX, the occurrence of I co rise time difference between the between the sense amplifier activation line P SA - NSA.

In Figure 1, the Inba evening gate 1 09 which outputs the Ikoraizu control signal BRSS of the sense amplifier line P SAZNSA is provided with a voltage level conversion function of converting the internal step-down voltage Vc c to the boosted voltage Vp p It is supplied is. On the other hand, the inverter Isseki gate 1 1 0 for outputting the bit line Ikoraizu control signal BR S, the internal step-down voltage VCC without a voltage level conversion is supplied.

While shorter bit line length, sense amplifier lines PSA, for line length of N SA is unchanged, the wiring capacitance of the bit line is reduced and the wiring capacity of the sense amplifier activity line is unchanged. Therefore, when Ikoraizu time bit line Oyopi sense amplifier lines you do not change before and after the change of the bit line length, compared to capable of driving transistors used in the bit line Ikoraizu circuit 1 07 Te, must be increased bets Rungis evening drivability used in PSA / NSA Ikoraizu circuit 1 1 1.

In the first embodiment, using the boosted voltage Vpp to the P SA / NSA line Ikoraizu control signal BRSS, it uses an internal step-down voltage Vc c to bit line Ikoraizu control signal BRS. As a result, as shown in solid line of FIG. 4, to reduce the Ikoraizu time between bit lines BLZ- B LX, the time difference between Ikoraizu time between Sensua amplifier active line P SA - NSA as a first effect be able to. By the inter BLZ- B LX between the P SA - NSA is Ikoraizu equivalent Thai Mi in g, abnormal current reduction is possible current consumption possible to prevent the short circuit in the sense amplifier S / A associated with Ikoraizu it can. As a second effect, the control signal by using the internal step-down voltage Vc c instead boosted voltage Vp p in BRS, BLZ- without Ikoraizu time between B LX and between P SA - N SA increases, the boosted voltage Vpp reduce the driving current consumption of the transistor of Ikorai's circuit by. In addition, the current consumption of the booster circuit (not shown) can also be reduced.

Of course, when the wiring capacity of the bit line is because, for example to increase than the wiring capacitance of the sense amplifier line, the relationship Ikoraizu time difference between the inter-BL Z- B LX between the P SA - N SA is reversed the voltage used for the control signal BRS from the internal step-down voltage V cc to the boosted voltage Vp p, more changing the internal low voltage V cc the voltage used for the control signal BR SS from the boosted voltage Vp p, and reduction of Ikoraizu time difference similar effect for reducing the current consumption can be obtained.

The value of the power supply voltage for driving the Ikoraizu circuit 107, 1 1 1, the boosted voltage Vp p used in this tool body embodiment is not limited to the internal step-down voltage V cc. For example, depending on each of the semiconductor memory device, an external voltage Vd d, using any appropriate combination of the boosted voltage Vp p and internal low voltage V cc, to drive the Ikoraizu circuit 107, 1 1 1 possible it is.

Further, a control method for the separation gate used in the first embodiment, be carried together control method of Ikorai's circuit, while suppressing an increase and § click Seth operating speed reduction of the memory cell area, further lower current consumption it can be achieved. In the second embodiment of FIG. 5, instead of the bit line I Koraizu circuit 1 07 of the first embodiment shown in FIG. 1, with two bit lines Ikoraizu circuit 1 32, 1 33, it it bit between the door line BLLZ and BLLX, are connected between the bit line BLRZ and BL RX. The BRS generator 1 3 1 is input Ikoraizu control signal EQ, the voltage converted bit line Ikora I's control signal BRS L, BR SR is output, it it bit line Ikora I's circuit 1 32, 1 33 is input to. Construction and operation of the bit line Ikoraizu circuit 1 32, 1 33 is similar to Ikoraizu circuit 107 (FIG. 1). Even if maintaining the bit line isolation gate of the unselected memory proc non-conductive, a circuit configuration which can solve your it like the destruction of data due to floating of the bit line potential problems.

And even in the circuit configuration of FIG. 5, it is possible to obtain the same effect as the first embodiment using the control method of Ikoraizu circuit of the first embodiment. That is, bit line BLLZ, BLLX, BLRZ, when configured shorter than before bit line length BL RX, with boosted voltage Vp p to PS AZN SA line Ikoraizu control signal BRSS, bit line Ikoraizu control signal BRSL and it may be used internal step-down voltage V cc to BRSR.

Thus, the reduced time difference of both Ikoraizu time, it is possible to prevent short-circuiting of the abnormal current in the sense amplifier SZ A accompanying the Ikorai's, it reduces the current consumption. In addition by using the internal step-down voltage V cc to Ikoraizu control signal BRSL and BRSR, without Ikoraizu time bicycloalkyl Uz preparative lines and Sen Suanpu active line is increased, the driving transistors of Ikoraizu circuit according boosted voltage V pp current consumption can be reduced. Current consumption of pressurized forte booster circuit (not shown) can also be reduced. Further, when the wiring capacity of the bit line is larger than the wiring capacitance of the sense amplifier line, the voltage used for the control signal BRSL and BRSR from the internal step-down voltage V cc to the boosted voltage Vp p, PSA / NSA line by changing the voltage used for Ikoraizu control signal BRSS from the boosted voltage Vp p to the internal step-down voltage V cc, the same effect can be obtained.

In the third embodiment of FIG. 6, in place of the second bit line I embodiment Koraizu circuit 1 3 2, 1 3 3 shown in FIG. 5, three bit line Ikoraizu circuit 1 3 4 1 3 5, 1 3 6 are used, between which it pit line BLLZ and BLLX, between the bit lines BLZ and BLX, is connected between the bit line BLRZ and BL RX. It also it bit line Ikoraizu control signal BRSL, BRS, BRSR is input. Bit line Ikoraizu circuit 1 3 4, 1 3 5 1 3 6 configuration and operation of is the same as Ikoraizu circuit 1 0 7 (Figure 1). Even if maintaining the bit line isolation gate of the unselected memory proc non-conductive, a circuit configuration capable of solving the fear such destruction of data that by the floating bit line potential problem.

Also in the circuit arrangement of FIG. 6, it is possible to obtain the same effect as the first embodiment using the control method of Ikoraizu circuit of the first embodiment. Ie, bit line BLLZ, BL LX, and BLRZ, when configured shorter than before Bitsu bets line length BL RX, with boosted voltage V pp to the control signal BRSS, control signal BRS, BRSL and BRSR it may be used inside the internal step-down voltage V cc to.

Thus, the time difference of both Ikoraizu time is reduced, thereby reducing the can can current consumption to prevent short-circuiting of the abnormal current in the sense amplifier S / A associated with the Ikorai scan. In addition, without Ikoraizu time bit lines and sense amplifier line is increased, the current consumption of the transistor evening drive current consumption and booster circuit Ikora I's circuit by the boosted voltage V pp can be decreased cutting. Further, when the wiring capacity of the bit line is larger than the wiring capacitance of the sense amplifier line, bit line Ikoraizu control signal BRS, the boosted voltage Vp p to BRSL Contact and BRSR, the internal step-down voltage V cc to the control signal BRSS the use, the same effect can be obtained.

In the fourth embodiment of Figure 7, instead of the bit line Ikora I's circuit of the third embodiment of FIG. 6, using three bit line Ikoraizu circuit 1 3 7 1 3 8, 1 3 9 and, between it it bit line BLLZ and BLLX, between the bit lines BLZ and BLX, is connected between the bi Uz preparative lines BLRZ and BL RX. It also it bit line Ikoraizu control signal BRSL, BRS, BRSR are connected. Bit line Ikoraizu circuit 1 3 7 1 3 9 consists NM_〇 S transistor evening 2 elements, having a function of supplying a Ikoraizu voltage V pr to bit lines. The Ikoraizu circuit 1 3 8 consists NMO S transistor 1 element, and a bi Uz preparative lines BLZ and BLX sucrose - having a function of bets.

In this circuit configuration, even when maintaining the bit line isolation gate of the unselected memory proc non-conductive, fear, etc. destruction of Isseki de by floating the bit line potential does not occur. In addition, it is possible to reduce than the transistor evening number of elements Ru using the bit line Ikoraizu the second and third embodiments (5, 6 diagram), it is possible to reduce the chip area. Ie the second embodiment (FIG. 5), the bi Uz preparative line Ikoraizu circuit 1 3 2 and 1 3 3 in 6 elements are required, the third embodiment (FIG. 6), the bit line Ikoraizu circuit 1 3 4 to 1 3 5 and 1 3 of the 6 Ru 9 elements needed der, the circuit configuration in the seventh bit line Ikoraizu circuit 1 3 7 in FIG, 1 3 8, a total of five elements 1 3 of 9 possible it is. And even if the circuit smell of FIG. 7, it is possible to obtain the same effect as the first embodiment using the control method of Ikoraizu circuit of the first embodiment.

In the fifth embodiment of Figure 8, bit line of the fourth embodiment of Figure 7 Ikora I's circuit 1 3 7 1 3 8, 1 3 9 3 Ikoraizu circuit 1 4 0 instead of 1 4 1, 1 4 2 are provided, between which it pit line BLLZ and BLLX, between the bit lines BLZ and BLX, is connected between the bit line BLRZ and BL RX. It also it bit line Ikoraizu control signal BRSL, BRS, BRSR is input. The Ikoraizu circuit 1 4 1 and Ikoraizu circuit 1 of FIG. 7 3 7 and 1 3 9 have the same circuit configuration, the Ikoraizu circuit 1 3 8 I co Rise circuit 1 4 0 and 1 4 2 and Figure 7 it is the same circuit configuration.

In this circuit configuration, in Ikoraizu circuit 1 4 0-1 4 2, it is possible circuit a total of 4 transistor elements. On the other hand, the Ikoraizu circuit 1 3 7 to 1 3 9 in the fourth embodiment of Figure 7, it is necessary total of 5 elements. Thus compared to Ikoraizu circuit of the fourth embodiment, further can be reduced in chip area in the circuit of the fifth embodiment.

And also in the circuit of the fifth embodiment, as described in the fourth embodiment (FIG. 7), to obtain the same effect as the first embodiment using the control method of Ikoraizu circuit of the first embodiment possible it is. Similar to the first embodiment (FIG. 1), order to prevent the floating of the non-selected proc side of bit lines, it is preferable to use further combined control method for separating gate Ichito. In the sixth embodiment, it has you in the third to fifth embodiments (FIG. 6 to FIG. 8), in place of the sense amplifier S / A, and illustrating a case where alternate sense amplifier S / A s is used . Alternatively the sense amplifier S / A s, when signal of low level and high level respectively inputted to the sense amplifier control signals LEX and LEZ, alternate sense amplifier S / A s to the internal step-down voltage V cc and the ground voltage V ss is supplied, is configured to become active. The difference in or the wiring capacitance, the outer bit line pair BLLZ- BL LX in the selected memory proc, BLRZ- B time which LRX is completed Ikoraizu, connected inside bicycloalkyl Uz preparative line pairs of alternate sense amplifier BLZ- BLX there is a case where time and two hours difference to end Ikorai's results. Then Ikoraizu time is limited by the the longer, it can not realize the original performance of the semiconductor memory device.

In a sixth view of a third embodiment, composing shorter than the conventional bit lines BLLZ in the memory block BLK 1, BL LX, and bit lines B LR Z in memory proc BLK 2, line length of B LRX the it allows alternate cell Nsuanpu S / a s is connected bit lines BLZ, compared to the wiring capacitance of BLX, consider the case wiring capacity of the memory proc in bit line is small. At this time, the control signal line BRS bits line Ikoraizu circuit 1 3 4 control signal lines BRSL and I Koraizu circuit 1 3 5, if both the internal step-down voltage V cc is used, as shown in FIG. 9 in the Ikoraizu time between bit lines BLLZ-BL LX, bit line BLZ- BLLZ compares the between at Ikoraizu between B LX - found the following Ikoraizu time between BLLX faster. Therefore, the control signal BR SL of Ikoraizu circuit 1 34 is used internal step-down voltage V cc, the control signal BRS of Ikoraizu circuit 1 3 5 boosted voltage Vp p is used, by controlling a different voltage, such as , the time difference of Ikoraizu of said Ryobi Tsu bets line is reduced. That is, in FIG. 9, by the Ikoraizu time between BLZ -B LX is shortened (reduced from Figure 9 in broken line portion to the solid line), a time difference of Ikoraizu of both bit lines are small shrinkage. Of course when the memory block BLK 2 is selected, the internal step-down voltage V cc to the control signal BR SR, control if signal BRS to the boosted voltage Vp p is used the same effect is obtained.

Of course, alternative sense amplifier S / A s is connected bit lines BLZ, compared to the wiring capacitance of BLX, bit lines BLLZ in memory proc, for reasons such as wiring capacitance BL LX increases, BLZ - If the relationship Ikoraizu time difference between between between B LX and BLLZ- BLLX is reversed, the internal control voltage for use in control signal BRS from the boosted voltage V pp to the internal step-down voltage V cc, the voltage used for the control signal BRSL by reducing the Ikoraizu time difference between the change from the step-down voltage V cc to the boosted voltage V pp, the same effect can be obtained. The value of the power supply voltage for driving the Ikoraizu circuit, the boosted voltage V pp used in the sixth embodiment is not limited to the internal step-down voltage V cc. For example, in response to each of the semiconductor memory device, using any suitable combination of external voltage V dd, the boosted voltage V p P and the internal step-down voltage V cc, it is possible to drive the I co Rise circuit .

The fourth embodiment (FIG. 7), also in the fifth embodiment (FIG. 8), the use of Ikoraizu circuit using an alternate sense amplifier S / A s in the control method shown in the sixth embodiment can.

The present invention is not limited to the above embodiments, and various improvements without departing from the scope of the present invention, it goes without saying that variations are possible. The method of bit line isolation gate, the control method of the bit lines and the sense amplifier activity line Ikoraizu circuit arrangement and circuit configuration of Ikoraizu circuit is naturally the combination therewith it appropriately. Industrial Applicability

According to the present invention, a control method of the bit line isolation gate, the control method of Ikoraizu circuit, by appropriately combining a placement and circuit configuration of Ikoraizu circuit, while maintaining the operating speed and chip area at the time of normal access operation , it is possible to provide a control method for low current operation the semiconductor memory device capable of, and semiconductors memory device.

Claims

The scope of the claims
1. Storage information in bit line in accordance with Wado line selected is read, and the first and second memory proc, each first and second bit lines in said first Oyopi second Memoripurodzuku in the semiconductor memory device and a sense amplifier shared,
A first isolation gate for controlling the connection and separation between the sense amplifier and the first bi Uz DOO line,
And a Ikoraizu portion for Ikoraizu the second bit line,
The second when the access operation to the memory block is performed, in to that k times of the word line selection (k-1) times or less of the predetermined number of consecutive, the activity of the Ikoraizu portion after Wa time line selection period, the semiconductor memory device, wherein the first isolation gate is a connected state and said sense amplifier and said first bit line.
2. In response to said second access operation period for the memory block, the previous SL second bit line comprises a second isolation gate for connecting the sense amplifier, the Ikoraizu section, with respect to the second isolation gate the semiconductor memory device according to claim 1, characterized in that disposed on at least one of said second memory block side or the sense amplifier side.
3. The first activation of the isolation gate, the Te second memory Proc smell, the address identifying the word lines of k the selected consecutively is performed in response to a predetermined logical combination the semiconductor memory device according to claim 1, wherein the. '
4. Activation of the first isolation gate, the Te second memory Proc odor, 1 peak. Of Uz bets upper Adoresu is the address that identifies the Wa one word line of k this is continuously selected, the semiconductor memory device according to claim 1, characterized that you performed in response to a transition of the logic state.
5. The access operation of the second memory block is a refresh operation, address to select the Wado line of k book consecutive, of claims 1 to 4, characterized in that a re-off threshold address least the semiconductor memory device of the mounting serial to any one also.
6 access operation of the second memory proc is a continuous access operation including the switching of the word lines,
Address for selecting the k word lines which communicate Nyo A semiconductor memory device according to least any one also of claims 1 to 4, characterized in that a Lore dress or a portion thereof.
7. Gay when the stored information to be read preparative line is amplified by multiple sense amplifiers provided for each bit line, the power supply voltage to the two power supply lines connected in common to said plurality of sense amplifiers in the semiconductor memory device comprising a sense amplifier section for supplying,
A first co rise portion for Ikoraizu the power supply line and activated by the first voltage,
The semiconductor memory device characterized by comprising a second Ikoraizu unit for Ikora I's the bit lines are activated by different second voltage from the first voltage.
8. While cutting off the power voltage supply to the power supply line by said sense amplifier unit, when activating said first and second Ikoraizu portion,
Wherein as compared with the wiring load components of the power supply line, when the wiring load Ingredients of the bit line is small, the first voltage, a higher voltage level than the second voltage,
Than the wiring load component of said power supply line, when the wiring load Ingredients of the bit line is large, the first voltage, to a low voltage level than the second voltage the semiconductor memory device according to claim 7, characterized.
9. Bei the isolation gate to separate the bit lines, the outer bit line portion, wherein the stored information inside bit line portion connected to the sense amplifier is read
A- second Ikoraizu unit, being arranged as a least either be of the inner I co rise portion provided on the inner bit line portion, or the outer bit line outer Ikoraizu unit provided in section the semiconductor memory device of the serial placement in claim 7,.
1 0. The stored information to be read bit line in the semiconductor memory for amplifying a plurality of sense amplifiers provided for each bit line comprises a sense amplifier unit for controlling the supply of power supply voltage for each Sensua amplifier in semiconductors memory device,
Said bit lines, and separation gate one you want to separate into an outer bit line portion and memorize information inside bit line portion is read out to be connected to the sense amplifier, the inner bit and activated by the first voltage and an inner Ikoraizu unit that Ikoraizu the door line portion,
The first voltage is activated by a different second voltage, the semiconductor 曰己 ¾ ti o, characterized in that it comprises an outer Ikoraizu unit for Ikoraizu the outer bit line section
1 1. In the Ikoraizu operation, as well as cutting off the power voltage supply by the sense amplifier section, when the activity of the inner and outer Ikoraizu unit,
Than the wiring load component of the inner bit line portion, when the wiring load component of the outer bit line portion is small, the first voltage, high have a voltage level than the second voltage,
Than the wiring load component of the inner bit line portion, when the wiring load component of the outer bit line portion is a dog, the first voltage, and low have voltage level than the second voltage the semiconductor memory equipment according to claim 1 0, characterized in that.
1 2. The bit lines are differential amplification by the sense amplifier two as a pair,
It said inner and outer Ikoraizu unit is provided with a short section shorting the inner and outer bit line portion paired,
Either to as least one of the inner or outer Ikoraizu unit, before Symbol semiconductor memory according to the inner or outer bit line section to claims 9 to 1 1, characterized in that it comprises a bias unit for biasing the Ikoraizu voltage apparatus.
1 3. The first Ikoraizu unit comprises a single MOS transistor even rather small connecting between the power supply line,
The MOS transistor is, semiconductors memory device according to claim 7, wherein the first voltage to the gate terminal is activated to conduct by the this applied.
1 4. The second Ikoraizu portion, or the inner Ikoraizu portion and front Kisotogawa Ikoraizu unit connects the source of the bit lines, or the inner bit line and the outer bit line and Ikoraizu voltage to, one of the MOS transistor at least, or,
Connecting the line if configured as the bit lines or the inner bit line and the outer bit line are two pair at least one M
The OS transistor also comprises either a small,
The MOS transistor includes a semiconductor memory according to any one even without least of claims 7 to 1 2, wherein the second voltage to the gate terminal is activated to conduct by the this applied apparatus.
1 5. Store information in bit line in response to the word line selected is Ru read, the semiconductor memory device cell Nsuanpu is shared for each first and second bit lines of the first and second memory blocks in the control method of,
For the second bit line, a selection Purokkuaku Seth steps squirrel Ta operation following the Wado line selection and subsequent Ikoraizu operation is repeated continuously,
In Ikoraizu operation a predetermined number of following one (k one 1) times of k times in said selected block access step, and a non-selection proc I co Rise step of the said said first bit line cell Nsuanpu a connected state control method of the semiconductor memory device characterized by having.
1 6. The selection Proc access step comprises a connection Sutedzupu which connects the second bi Uz preparative line before Symbol sense amplifier, said Ikoraizu operation of the second bit lines, was or the second memory Proc side control method of the semiconductor memory device according to claim 1 5, characterized in that it is carried out starting from one or both the least of the sense amplifier side.
1 7. The connection between the first bi Uz bets lines in unselected Proc equalizing step and the Sensuanpu is the k times Adoresu identifying the Wado line selecting successive Oite the selection proc access step, predetermined the method of semiconductors memory device according to claim 1 5, characterized in that it is performed according to the logical combination.
1 8. The unselected pro brute equalizing connection between said first bit line and the sense amplifier in step is Adoresu identifies the Wa one word line selected in k times continuous Oite the selected block accessing step 1 Adoresu bits higher-order control method of the semiconductor memory device according to claim 1 5, characterized in that it is performed in response to changes logic states for.
1 9. Access operation in said selected block access step is a refresh operation,
Adoresu the control method of the semiconductor memory device according to least any one also of claims 1 5 to 1 8, characterized in that the refresh § drain scan for selecting k book Wado line successive.
2 0. Access operation in said selected block access step is a continuous access operation including the switching of Wa lead wire,
Adoresu is Roadoresu or control method of the semiconductor memory device according to least any one also of claims 1 5 to 1 8, characterized in that the a part for selecting the k book Wado line successive.
2 1. The stored information to be read bit line when amplifying a plurality of sense amplifiers provided for each bit line, with respect to two power supply lines connected to the common to said plurality of sense amplifiers a method of controlling a semiconductor memory device to which a power supply voltage is supplied,
In Ikoraizu operation,
A voltage supply interrupting Sutetsu flop to cut off the power voltage supply to the power supply line,
Wherein with the power supply line is controlled by the first voltage Ikoraizu, to have a I co Rise steps has been I co Rise controlled by a different second voltage and the bit line is the first voltage control method of a semiconductor Symbol 憶 device comprising.
In 2 2. The Ikoraizu operation,
Than the wiring load component of said power supply line, when the wiring load Ingredients of the bit line is small, the power supply lines, while being Ikora I's are controlled by a first voltage, the bit line, which is Ikoraizu controlled by the second voltage of a low voltage level than the first voltage,
Than the wiring load component of said power supply line, when the wiring load Ingredients of the bit line is large, the power supply lines, while being Ikora I's are controlled by a first voltage, the bit line, is controlled by being Ikoraizu by a second voltage of a higher voltage level than the first voltage, the power supply line and said bit line, Ikora Izusuteppu is Ikoraizu in comparable time control method of the semiconductor memory device according to claim 2 1, wherein a.
2 3. If the bit line is configured to include an inner bit line to be connected to the sense amplifier, and the outer bit line section stored information is read out, and
The I co rise step, the semiconductor memory device according to claim 2 1 you comprises carrying out the inner bit line portion, or the least either be of the outer bit line portion starting control method.
In 2 4. The storage information read in bit line, a control method of the semiconductor memory device for amplifying in terms of power supply voltage supplied to each sense amplifier is performed at a plurality of sense amplifiers that provided for each bit line,
The bi Uz DOO line, when the outer bit line section stored information is read, and provided with an inner bit line to be connected to the cell Nsuanpu in Ikoraizu operation, the inner bit line characterized but by having a co Once Ikoraizu is controlled by the first voltage, the I co rise steps are controlled by a different second voltage Ikoraizu outer bit line portion and the first voltage control method for a semiconductor memory device.
In 5 2 5 - the Ikoraizu operation,
Than the wiring load component of the inner bit line portion, when the wiring load component of the outer bit line portion becomes small, the inner bit line portion, while being Ikoraizu is controlled by the first voltage the outer bit line portion, being the first voltage to be controlled by a second voltage lower voltage level than by Ikoraizu, than the wiring load components of 10 the inner bit line portion, the outer If the bit line portion, wiring load component is a dog, the inner bit line portion, while being Ikoraizu is controlled by the first voltage, the outer bit line portion, a ratio to the first voltage the method of semi-15 conductor memory device according to claim 2 4, characterized in that it comprises a I co rise steps that will be Ikoraizu is controlled by the second voltage of the higher voltage level to.
2 6. The bit lines are differential amplification by the sense amplifier two as a pair,
Said I co-rise stearyl Uz-flop,
And short stearyl 0 Uz flop shorting the inner and outer bit line portion paired,
The semiconductor according to least any one also of claims 2 3 to 2 5, characterized in that it comprises a bias step of biasing the at least one in Ikora I's voltage of said inner or outer bit line section control method of a storage device.
Five
PCT/JP2003/003128 2003-03-14 2003-03-14 Semiconductor storage device and semiconductor storage device control method WO2004081945A1 (en)

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JP2004569365A JP4358116B2 (en) 2003-03-14 2003-03-14 Control method for a semiconductor memory device, and a semiconductor memory device
US11058302 US7245549B2 (en) 2003-03-14 2005-02-16 Semiconductor memory device and method of controlling the semiconductor memory device
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000100171A (en) * 1998-09-24 2000-04-07 Fujitsu Ltd Memory device with speeded up reset operation
JP2000195258A (en) * 1998-12-30 2000-07-14 Hyundai Electronics Ind Co Ltd Memory circuit, the memory circuit and operation method of element, reduction method for bit-line control switching, and bit-line selection controller for reducing the bit-line control switching in the memory circuit
JP2000298984A (en) * 1999-04-15 2000-10-24 Oki Electric Ind Co Ltd Semiconductor memory

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000100171A (en) * 1998-09-24 2000-04-07 Fujitsu Ltd Memory device with speeded up reset operation
JP2000195258A (en) * 1998-12-30 2000-07-14 Hyundai Electronics Ind Co Ltd Memory circuit, the memory circuit and operation method of element, reduction method for bit-line control switching, and bit-line selection controller for reducing the bit-line control switching in the memory circuit
JP2000298984A (en) * 1999-04-15 2000-10-24 Oki Electric Ind Co Ltd Semiconductor memory

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