US20110249516A1 - Internal voltage generation device - Google Patents

Internal voltage generation device Download PDF

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Publication number
US20110249516A1
US20110249516A1 US13/086,018 US201113086018A US2011249516A1 US 20110249516 A1 US20110249516 A1 US 20110249516A1 US 201113086018 A US201113086018 A US 201113086018A US 2011249516 A1 US2011249516 A1 US 2011249516A1
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voltage
internal voltage
node
level
generation device
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US13/086,018
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Jong Won Lee
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SK Hynix Inc
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Hynix Semiconductor Inc
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/462—Regulating voltage or current wherein the variable actually regulated by the final control device is dc as a function of the requirements of the load, e.g. delay, temperature, specific voltage/current characteristic
    • G05F1/465—Internal voltage generators for integrated circuits, e.g. step down generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/402—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh

Definitions

  • the present disclosure relates to a semiconductor memory device, and more particularly to an internal voltage generation device.
  • a semiconductor memory device receives a supply voltage VDD, and generates and uses internal voltages required within a chip, including a core voltage Vcore and a high voltage VPP.
  • the core voltage Vcore is used in a core area of the memory device, and is generated by down-converting the supply voltage VDD.
  • the high voltage VPP is used to drive word lines of the memory device, and is generated by boosting the supply voltage VDD.
  • a refresh operation of the DRAM includes an auto-refresh mode and a self-refresh mode. In each mode, word lines are refreshed in the order of internally controlled addresses at a certain period corresponding to a refresh retention time of each cell.
  • the self-refresh mode is an operation mode where the DRAM internally performs the refresh operation by itself for retention of information stored therein when a system including the DRAM carries out no operation for a certain period of time. For this reason, the DRAM consumes a large amount of current in the self-refresh mode.
  • One approach to reducing current consumption in the self-refresh mode which is called a multi-word line refresh technique, is to refresh cells connected to two or more word lines at the same time while the refresh operation is performed once and control a refresh period to twice or more of the refresh period of a conventional approach.
  • an internal voltage generation device comprises an internal voltage generator operated in response to an enable signal, the internal voltage generator generating an internal voltage using a reference voltage, and a sub-voltage generator for driving an output terminal of the internal voltage generator to a predetermined voltage level in response to a control signal.
  • the control signal may drive the sub-voltage generator in a multi-word line self-refresh operation.
  • an internal voltage generation device comprises an internal voltage generator operated in response to an enable signal, the internal voltage generator generating an internal voltage using a reference voltage a sub-voltage generator for driving an output terminal of the internal voltage generator to a predetermined voltage level in response to a control signal and a logic circuit for generating the control signal in response to a multi-word line enable signal and a drive signal in the internal voltage generator.
  • the control signal may drive the sub-voltage generator when a voltage level of the drive signal falls and the multi-word line enable signal is activated.
  • an internal voltage generation device comprises a voltage pump for generating an internal voltage in response to an oscillation signal, and a sub-voltage pump for generating the internal voltage in response to the oscillation signal and a control signal and outputting the internal voltage to an output terminal of the voltage pump.
  • the control signal may drive the sub-voltage pump in a multi-word line self-refresh operation.
  • FIG. 1 is a circuit diagram showing the configuration of an internal voltage generation device according to an exemplary embodiment of the present invention
  • FIG. 2 is a block diagram of a multi-word line enable signal generator shown in FIG. 1 ;
  • FIG. 3 is a detailed circuit diagram of the multi-word line enable signal generator of FIG. 2 ;
  • FIG. 4 is a circuit diagram showing the configuration of an internal voltage generation device according to another embodiment of the present invention.
  • FIG. 5 is a block diagram showing the configuration of an internal voltage generation device according to another embodiment of the present invention.
  • FIG. 6 is a circuit diagram of a sub-voltage pump shown in FIG. 5 .
  • An internal voltage generation device is configured to increase the driving capability of an internal voltage in a multi-word line self-refresh operation period so as to improve stability and reliability of a semiconductor memory device.
  • FIG. 1 is a circuit diagram showing the configuration of an internal voltage generation device according to an exemplary embodiment of the present invention.
  • the internal voltage generation device comprises an internal voltage generator 10 operated in response to an enable signal Enable for generating a core voltage Vcore using a reference voltage VREF, and a sub-voltage generator 20 for driving an output terminal A of the internal voltage generator 10 to a supply voltage VDD level in response to a control signal Control.
  • the control signal Control drives the sub-voltage generator 20 in a multi-word line self-refresh operation.
  • the internal voltage generator 10 includes a first pull-down device N 11 connected between a first node and a second node and configured to pull the second node down in response to the reference voltage VREF, a second pull-down device N 12 connected between the first node and a third node and configured to pull the third node down in response to a divided voltage of the internal voltage, or core voltage Vcore, a switch N 13 connected between the first node and a ground voltage VSS terminal and configured to perform a switching operation in response to the enable signal Enable, a first pull-up device P 11 connected between a supply voltage VDD terminal and the second node, a second pull-up device P 12 connected between the supply voltage VDD terminal and the third node, a third pull-up device P 16 for pulling a fourth node up in response to a signal at the third node, and a fourth pull-up device P 18 for pulling the output terminal A up in response to a signal at the fourth node.
  • a first pull-down device N 11 connected between a first node and
  • the internal voltage generator 10 further includes a voltage divider (N 16 and N 17 ) connected between the output terminal A and the ground voltage VSS terminal and configured to divide the internal voltage, or core voltage Vcore, and outputting the divided voltage.
  • a voltage divider N 16 and N 17
  • FIG. 2 is a block diagram of a multi-word line enable signal generator in FIG. 1
  • FIG. 3 is a detailed circuit diagram of the multi-word line enable signal generator of FIG. 2
  • a multi-word line enable signal Multi_w 1 _en is made active in a self-refresh mode Sref to activate the control signal Control. That is, the control signal Control is activated in the multi-word line self-refresh operation to drive the sub-voltage generator 20 connected with the output terminal A of the internal voltage generator 10 .
  • the internal voltage generation device acts to supply the core voltage Vcore as an internal voltage in the example of FIG. 1 .
  • the multi-word line enable signal generator receives a self-refresh signal and a test mode signal, performs a logic operation with respect to the received signals, and generates the multi-word line enable signal Multi_w 1 _en as a result of the logic operation.
  • the control signal in FIG. 1 is an inverted version of the multi-word line enable signal Multi_w 1 _en. Namely, the control signal makes a transition to a low level through an inverter when the multi-word line enable signal Multi_w 1 _en becomes active.
  • the internal voltage generator 10 generates an internal voltage and outputs the generated internal voltage to the output terminal A.
  • the switch N 13 which is an n-channel metal oxide semiconductor (NMOS) transistor, is turned on and p-channel metal oxide semiconductor (PMOS) transistors P 13 , P 15 and P 17 are turned off, thereby causing the internal voltage generator 10 to be enabled.
  • the internal voltage generator 10 supplies an internal voltage of a predetermined level to the output terminal A through comparison between a voltage at a node B, which is a divided version of the voltage at the output terminal A, and the reference voltage VREF.
  • the voltage at the output terminal A becomes lower than the predetermined level
  • the voltage at the node B which is a divided version of the voltage at the output terminal A
  • the reference voltage VREF so that the second pull-down device N 12 , which is an NMOS transistor, is turned on to a level lower than that of the first pull-down device N 11 , which is an NMOS transistor. Accordingly, the turn-on resistance of the NMOS transistor N 12 becomes higher than that of the NMOS transistor N 11 .
  • the voltage at the node B which is a divided version of the voltage at the output terminal A, becomes higher than the reference voltage VREF, so that the NMOS transistor N 12 is turned on to a level higher than that of the NMOS transistor N 11 .
  • the turn-on resistance of the NMOS transistor N 12 becomes lower than that of the NMOS transistor N 11 .
  • the voltage at the node C falls, so that the turn-on resistance of the PMOS transistor P 16 becomes lower, thereby causing the voltage at the node D to rise.
  • the turn-on resistances of the PMOS transistor P 18 and PMOS transistor P 19 are increased, so that the voltage at the output terminal A falls. Consequently, the internal voltage falls.
  • the internal voltage generator 10 can maintain the voltage at the output terminal A constant through the comparison operation as stated above, so as to supply the internal voltage, or core voltage Vcore, of the predetermined level through the output terminal A.
  • the multi-word line enable signal Multi_w 1 _en is made active, so that a low signal is outputted through the inverter as the control signal Control. That is, in the multi-word line self-refresh operation, the control signal Control drives the sub-voltage generator 20 connected with the output terminal A of the internal voltage generator 10 .
  • the internal voltage generation device can increase the driving capability of the driver in the multi-word line self-refresh operation period so as to reduce noise in the internal voltage.
  • FIG. 4 is a circuit diagram showing the configuration of an internal voltage generation device according to another embodiment of the present invention.
  • the internal voltage generation device comprises an internal voltage generator 10 operated in response to an enable signal Enable and configured to generate a core voltage Vcore using a reference voltage VREF, a sub-voltage generator 20 for driving an output terminal A of the internal voltage generator 10 to a level of a supply voltage VDD in response to a control signal Control, and a logic circuit for performing an OR operation with respect to a multi-word line enable signal Multi_w 1 _en and a signal Feed at a fourth node of the internal voltage generator 10 and generating the control signal Control as a result of the OR operation.
  • the control signal Control drives the sub-voltage generator 20 when a voltage level at the fourth node falls under the condition that the multi-word line enable signal Multi_w 1 _en is activated.
  • the operation of the internal voltage generator 10 in the internal voltage generation device with the above-stated configuration according to this embodiment is generally the same as that according to the first embodiment.
  • a voltage at a node B which is a divided version of the core voltage Vcore
  • an NMOS transistor N 12 is turned on to a level lower than that of an NMOS transistor N 11 , so that the turn-on resistance of the NMOS transistor N 12 becomes higher than that of the NMOS transistor N 11 .
  • a voltage at a node C rises, so that the turn-on resistance of a PMOS transistor P 16 becomes higher, thereby causing a voltage at a node D to fall.
  • a low signal is outputted as the control signal Control in response to the voltage at the node D.
  • the control signal Control drives the sub-voltage generator 20 connected with the output terminal A of the internal voltage generator 10 .
  • the internal voltage generation device can increase the driving capability of the driver in the multi-word line self-refresh operation period so as to reduce noise in the internal voltage.
  • FIG. 5 is a block diagram showing the configuration of an internal voltage generation device according to another embodiment of the present invention.
  • the internal voltage generation device comprises a voltage detector 40 , an oscillator 50 , a voltage pump 60 , a control signal generation unit 65 and a sub-voltage pump 70 .
  • the voltage detector detects a high voltage VPP fed back thereto and generates a voltage pumping enable signal OSC_EN when the detected high voltage VPP falls below a reference voltage.
  • the oscillator 50 generates an oscillation signal OSC in response to the enable signal OSC_EN, and the voltage pump 60 generates the high voltage VPP in response to the oscillation signal OSC and feeds it back to the voltage detector 40 .
  • the control signal generation unit 65 buffers the oscillation signal OSC, and generates a control signal CNT.
  • the control signal CNT is activated when a multi-word line enable signal Multi_w 1 _en is enabled as a high level in a multi-word line self-refresh operation, and deactivated as a low level when the multi-word line enable signal Multi_w 1 _en is disabled as a low level.
  • the sub-voltage pump 70 pumps the high voltage VPP when the control signal CNT is activated.
  • the sub-voltage pump 70 may include one or more sub-voltage pumps.
  • the sub-voltage pump 70 comprises a first transfer unit D 71 , a second transfer unit D 72 , and a coupling unit 700 .
  • the first transfer unit D 71 transfers a supply voltage VDD into a node nd 71 when a level of the supply voltage VDD is larger than a level of the node nd 71 .
  • the second transfer unit D 72 transfers a level of the node nd 71 into the high voltage VPP when the level of the node nd 71 is larger than a level of high voltage VPP.
  • the coupling unit 700 comprises a buffer 701 for buffering the control signal CNT, and a capacitor coupling between an output terminal of the buffer 701 and the node nd 71 .
  • the coupling unit 700 increases the level of the node nd 71 by the level of the control signal CNT when the control signal CNT has a high level.
  • the internal voltage generation device acts to supply the high voltage VPP as an internal voltage in the example of FIG. 5 .
  • the oscillator 50 If the voltage detector 40 detects a high voltage VPP fed back from the voltage pump 60 and generates a high voltage pumping enable signal OSC_EN as a result of the detection, the oscillator 50 generates the oscillation signal, or pulse signal, OSC in response to the high voltage pumping enable signal OSC_EN. Then, the voltage pump 60 pumps a high voltage VPP of a predetermined level in response to the pulse signal OSC.
  • the multi-word line enable signal Multi_w 1 _en is activated as a high level.
  • the control signal generation unit 65 buffers the oscillation signal OSC, and generates a control signal CNT.
  • the control signal CNT is activated when a multi-word line enable signal Multi_w 1 _en is enabled as a high level.
  • the sub-voltage pump 70 pumps the high voltage VPP when the control signal CNT is activated.
  • the first transfer unit D 71 transfers a supply voltage VDD into a node nd 71
  • the coupling unit 700 increases the level of the node nd 71 by a high level of control signal CNT
  • the second transfer unit D 72 transfers the level of the node nd 71 into the high voltage VPP.
  • the internal voltage generation device can increase the high voltage pumping capability in the multi-word line self-refresh operation period so as to reduce noise in the internal voltage.

Abstract

An internal voltage generation device is disclosed which includes an internal voltage generator operated in response to an enable signal, the internal voltage generator generating an internal voltage using a reference voltage, and a sub-voltage generator for driving an output terminal of the internal voltage generator to a predetermined voltage level in response to a control signal.

Description

  • This application is a divisional of U.S. Ser. No. 11/823,182, filed Jun. 27, 2007, which claims priority of Korean Patent Application No. 10-2006-0138796, filed Dec. 29, 2006, the contents of which are hereby incorporated by reference into this application.
    • BACKGROUND
  • The present disclosure relates to a semiconductor memory device, and more particularly to an internal voltage generation device.
  • In general, a semiconductor memory device receives a supply voltage VDD, and generates and uses internal voltages required within a chip, including a core voltage Vcore and a high voltage VPP. The core voltage Vcore is used in a core area of the memory device, and is generated by down-converting the supply voltage VDD. The high voltage VPP is used to drive word lines of the memory device, and is generated by boosting the supply voltage VDD.
  • Meanwhile, an amount of refresh current consumption becomes an important issue in a dynamic random access memory (DRAM). A refresh operation of the DRAM includes an auto-refresh mode and a self-refresh mode. In each mode, word lines are refreshed in the order of internally controlled addresses at a certain period corresponding to a refresh retention time of each cell.
  • The self-refresh mode is an operation mode where the DRAM internally performs the refresh operation by itself for retention of information stored therein when a system including the DRAM carries out no operation for a certain period of time. For this reason, the DRAM consumes a large amount of current in the self-refresh mode.
  • One approach to reducing current consumption in the self-refresh mode which is called a multi-word line refresh technique, is to refresh cells connected to two or more word lines at the same time while the refresh operation is performed once and control a refresh period to twice or more of the refresh period of a conventional approach.
  • Application of the multi-word line refresh technique makes it possible to reduce the amount of current to be used in a refresh control circuit as compared with that when cells are refreshed one by one.
  • However, application of the multi-word line refresh technique to a DRAM is disadvantageous in that there is a shortage of driving capabilities of internal voltages used for refresh operation as DRAM capacity increases.
    • BRIEF SUMMARY
  • In an aspect of the present invention, an internal voltage generation device comprises an internal voltage generator operated in response to an enable signal, the internal voltage generator generating an internal voltage using a reference voltage, and a sub-voltage generator for driving an output terminal of the internal voltage generator to a predetermined voltage level in response to a control signal.
  • The control signal may drive the sub-voltage generator in a multi-word line self-refresh operation.
  • In another aspect of the present invention, an internal voltage generation device comprises an internal voltage generator operated in response to an enable signal, the internal voltage generator generating an internal voltage using a reference voltage a sub-voltage generator for driving an output terminal of the internal voltage generator to a predetermined voltage level in response to a control signal and a logic circuit for generating the control signal in response to a multi-word line enable signal and a drive signal in the internal voltage generator.
  • The control signal may drive the sub-voltage generator when a voltage level of the drive signal falls and the multi-word line enable signal is activated.
  • In yet another aspect of the present invention, an internal voltage generation device comprises a voltage pump for generating an internal voltage in response to an oscillation signal, and a sub-voltage pump for generating the internal voltage in response to the oscillation signal and a control signal and outputting the internal voltage to an output terminal of the voltage pump.
  • The control signal may drive the sub-voltage pump in a multi-word line self-refresh operation.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The above and other aspects, features and other advantages of the subject matter of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
  • FIG. 1 is a circuit diagram showing the configuration of an internal voltage generation device according to an exemplary embodiment of the present invention;
  • FIG. 2 is a block diagram of a multi-word line enable signal generator shown in FIG. 1;
  • FIG. 3 is a detailed circuit diagram of the multi-word line enable signal generator of FIG. 2;
  • FIG. 4 is a circuit diagram showing the configuration of an internal voltage generation device according to another embodiment of the present invention;
  • FIG. 5 is a block diagram showing the configuration of an internal voltage generation device according to another embodiment of the present invention; and
  • FIG. 6 is a circuit diagram of a sub-voltage pump shown in FIG. 5.
    •  DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
  • Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
  • An internal voltage generation device according to the present invention is configured to increase the driving capability of an internal voltage in a multi-word line self-refresh operation period so as to improve stability and reliability of a semiconductor memory device.
  • FIG. 1 is a circuit diagram showing the configuration of an internal voltage generation device according to an exemplary embodiment of the present invention.
  • As shown in FIG. 1, the internal voltage generation device according to this embodiment comprises an internal voltage generator 10 operated in response to an enable signal Enable for generating a core voltage Vcore using a reference voltage VREF, and a sub-voltage generator 20 for driving an output terminal A of the internal voltage generator 10 to a supply voltage VDD level in response to a control signal Control. The control signal Control drives the sub-voltage generator 20 in a multi-word line self-refresh operation.
  • The internal voltage generator 10 includes a first pull-down device N11 connected between a first node and a second node and configured to pull the second node down in response to the reference voltage VREF, a second pull-down device N12 connected between the first node and a third node and configured to pull the third node down in response to a divided voltage of the internal voltage, or core voltage Vcore, a switch N13 connected between the first node and a ground voltage VSS terminal and configured to perform a switching operation in response to the enable signal Enable, a first pull-up device P11 connected between a supply voltage VDD terminal and the second node, a second pull-up device P12 connected between the supply voltage VDD terminal and the third node, a third pull-up device P16 for pulling a fourth node up in response to a signal at the third node, and a fourth pull-up device P18 for pulling the output terminal A up in response to a signal at the fourth node.
  • The internal voltage generator 10 further includes a voltage divider (N16 and N17) connected between the output terminal A and the ground voltage VSS terminal and configured to divide the internal voltage, or core voltage Vcore, and outputting the divided voltage.
  • FIG. 2 is a block diagram of a multi-word line enable signal generator in FIG. 1, and FIG. 3 is a detailed circuit diagram of the multi-word line enable signal generator of FIG. 2. A multi-word line enable signal Multi_w1_en is made active in a self-refresh mode Sref to activate the control signal Control. That is, the control signal Control is activated in the multi-word line self-refresh operation to drive the sub-voltage generator 20 connected with the output terminal A of the internal voltage generator 10.
  • The operation of the internal voltage generation device with the above-stated configuration according to the present embodiment will hereinafter be described in detail with reference to FIGS. 1 to 3.
  • The internal voltage generation device according to the present embodiment acts to supply the core voltage Vcore as an internal voltage in the example of FIG. 1.
  • As shown in FIGS. 2 and 3, the multi-word line enable signal generator receives a self-refresh signal and a test mode signal, performs a logic operation with respect to the received signals, and generates the multi-word line enable signal Multi_w1_en as a result of the logic operation. The control signal in FIG. 1 is an inverted version of the multi-word line enable signal Multi_w1_en. Namely, the control signal makes a transition to a low level through an inverter when the multi-word line enable signal Multi_w1_en becomes active.
  • First, the internal voltage generator 10 generates an internal voltage and outputs the generated internal voltage to the output terminal A. In detail, when the enable signal Enable is enabled to a high level, the switch N13, which is an n-channel metal oxide semiconductor (NMOS) transistor, is turned on and p-channel metal oxide semiconductor (PMOS) transistors P13, P15 and P17 are turned off, thereby causing the internal voltage generator 10 to be enabled. As a result, the internal voltage generator 10 supplies an internal voltage of a predetermined level to the output terminal A through comparison between a voltage at a node B, which is a divided version of the voltage at the output terminal A, and the reference voltage VREF.
  • If the voltage at the output terminal A becomes lower than the predetermined level, the voltage at the node B, which is a divided version of the voltage at the output terminal A, becomes lower than the reference voltage VREF, so that the second pull-down device N12, which is an NMOS transistor, is turned on to a level lower than that of the first pull-down device N11, which is an NMOS transistor. Accordingly, the turn-on resistance of the NMOS transistor N12 becomes higher than that of the NMOS transistor N11.
  • As a result, a voltage at a node C rises, so that the turn-on resistance of the third pull-up device P16, which is a PMOS transistor, becomes higher, thereby causing a voltage at a node D to fall. Then, in response to the voltage at the node D, the turn-on resistance of the fourth pull-up device P18, which is a PMOS transistor, and the turn-on resistance of a PMOS transistor P19 are reduced, so that the voltage at the output terminal A rises. Consequently, the internal voltage rises.
  • Conversely, if the voltage at the output terminal A becomes higher than the predetermined level, the voltage at the node B, which is a divided version of the voltage at the output terminal A, becomes higher than the reference voltage VREF, so that the NMOS transistor N12 is turned on to a level higher than that of the NMOS transistor N11. Thus, the turn-on resistance of the NMOS transistor N12 becomes lower than that of the NMOS transistor N11. As a result, the voltage at the node C falls, so that the turn-on resistance of the PMOS transistor P16 becomes lower, thereby causing the voltage at the node D to rise. Then, in response to the voltage at the node D, the turn-on resistances of the PMOS transistor P18 and PMOS transistor P19 are increased, so that the voltage at the output terminal A falls. Consequently, the internal voltage falls.
  • In this manner, the internal voltage generator 10 can maintain the voltage at the output terminal A constant through the comparison operation as stated above, so as to supply the internal voltage, or core voltage Vcore, of the predetermined level through the output terminal A.
  • At this time, if the self-refresh mode is entered, the multi-word line enable signal Multi_w1_en is made active, so that a low signal is outputted through the inverter as the control signal Control. That is, in the multi-word line self-refresh operation, the control signal Control drives the sub-voltage generator 20 connected with the output terminal A of the internal voltage generator 10. In this manner, the internal voltage generation device according to the present embodiment can increase the driving capability of the driver in the multi-word line self-refresh operation period so as to reduce noise in the internal voltage.
  • FIG. 4 is a circuit diagram showing the configuration of an internal voltage generation device according to another embodiment of the present invention.
  • As shown in FIG. 4, the internal voltage generation device according to this embodiment comprises an internal voltage generator 10 operated in response to an enable signal Enable and configured to generate a core voltage Vcore using a reference voltage VREF, a sub-voltage generator 20 for driving an output terminal A of the internal voltage generator 10 to a level of a supply voltage VDD in response to a control signal Control, and a logic circuit for performing an OR operation with respect to a multi-word line enable signal Multi_w1_en and a signal Feed at a fourth node of the internal voltage generator 10 and generating the control signal Control as a result of the OR operation.
  • The control signal Control drives the sub-voltage generator 20 when a voltage level at the fourth node falls under the condition that the multi-word line enable signal Multi_w1_en is activated.
  • The operation of the internal voltage generator 10 in the internal voltage generation device with the above-stated configuration according to this embodiment is generally the same as that according to the first embodiment. However, in the internal voltage generation device according to the present embodiment, when a voltage at a node B, which is a divided version of the core voltage Vcore, becomes lower than the reference voltage VREF, an NMOS transistor N12 is turned on to a level lower than that of an NMOS transistor N11, so that the turn-on resistance of the NMOS transistor N12 becomes higher than that of the NMOS transistor N11. As a result, a voltage at a node C rises, so that the turn-on resistance of a PMOS transistor P16 becomes higher, thereby causing a voltage at a node D to fall. At this time, a low signal is outputted as the control signal Control in response to the voltage at the node D.
  • That is, when the voltage at the node B, which is a divided version of the core voltage Vcore, becomes lower than the reference voltage VREF in a multi-word line self-refresh operation, the control signal Control drives the sub-voltage generator 20 connected with the output terminal A of the internal voltage generator 10. In this manner, the internal voltage generation device according to the present embodiment can increase the driving capability of the driver in the multi-word line self-refresh operation period so as to reduce noise in the internal voltage.
  • FIG. 5 is a block diagram showing the configuration of an internal voltage generation device according to another embodiment of the present invention.
  • As shown in FIG. 5, the internal voltage generation device according to this embodiment comprises a voltage detector 40, an oscillator 50, a voltage pump 60, a control signal generation unit 65 and a sub-voltage pump 70.
  • The voltage detector detects a high voltage VPP fed back thereto and generates a voltage pumping enable signal OSC_EN when the detected high voltage VPP falls below a reference voltage.
  • The oscillator 50 generates an oscillation signal OSC in response to the enable signal OSC_EN, and the voltage pump 60 generates the high voltage VPP in response to the oscillation signal OSC and feeds it back to the voltage detector 40.
  • The control signal generation unit 65 buffers the oscillation signal OSC, and generates a control signal CNT. The control signal CNT is activated when a multi-word line enable signal Multi_w1_en is enabled as a high level in a multi-word line self-refresh operation, and deactivated as a low level when the multi-word line enable signal Multi_w1_en is disabled as a low level.
  • The sub-voltage pump 70 pumps the high voltage VPP when the control signal CNT is activated. The sub-voltage pump 70 may include one or more sub-voltage pumps.
  • Referring to FIG. 6, the sub-voltage pump 70 comprises a first transfer unit D71, a second transfer unit D72, and a coupling unit 700. The first transfer unit D71 transfers a supply voltage VDD into a node nd71 when a level of the supply voltage VDD is larger than a level of the node nd71. The second transfer unit D72 transfers a level of the node nd71 into the high voltage VPP when the level of the node nd71 is larger than a level of high voltage VPP.
  • The coupling unit 700 comprises a buffer 701 for buffering the control signal CNT, and a capacitor coupling between an output terminal of the buffer 701 and the node nd71. The coupling unit 700 increases the level of the node nd71 by the level of the control signal CNT when the control signal CNT has a high level.
  • The operation of the internal voltage generation device with the above-stated configuration according to the present embodiment will hereinafter be described with reference to FIGS. 5 and 6.
  • The internal voltage generation device according to the present embodiment acts to supply the high voltage VPP as an internal voltage in the example of FIG. 5.
  • If the voltage detector 40 detects a high voltage VPP fed back from the voltage pump 60 and generates a high voltage pumping enable signal OSC_EN as a result of the detection, the oscillator 50 generates the oscillation signal, or pulse signal, OSC in response to the high voltage pumping enable signal OSC_EN. Then, the voltage pump 60 pumps a high voltage VPP of a predetermined level in response to the pulse signal OSC.
  • At this time, if the multi-word line self-refresh operation is entered, the multi-word line enable signal Multi_w1_en is activated as a high level. The control signal generation unit 65 buffers the oscillation signal OSC, and generates a control signal CNT. The control signal CNT is activated when a multi-word line enable signal Multi_w1_en is enabled as a high level.
  • The sub-voltage pump 70 pumps the high voltage VPP when the control signal CNT is activated. In detail, the first transfer unit D71 transfers a supply voltage VDD into a node nd71, the coupling unit 700 increases the level of the node nd71 by a high level of control signal CNT, and the second transfer unit D72 transfers the level of the node nd71 into the high voltage VPP.
  • In this manner, the internal voltage generation device according to the present embodiment can increase the high voltage pumping capability in the multi-word line self-refresh operation period so as to reduce noise in the internal voltage.
  • Although preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the disclosure and the accompanying claims.

Claims (14)

1-14. (canceled)
15. An internal voltage generation device comprising:
a voltage pump for pumping an internal voltage in response to an oscillation, signal; and
a first sub-voltage pump for pumping the internal voltage in response to a control signal being activated when a multi-word line self-refresh operation is entered.
16. The internal voltage generation device according to claim 15, wherein the first sub-voltage pump comprises:
a first transfer unit configured to transfer a supply voltage into a node;
a coupling unit configured to increase a level of the node by a level of the control signal when the control signal is activated; and
a second transfer unit configured to transfer the level of the node into the internal voltage.
17. The internal voltage generation device according to claim 16, wherein the first transfer unit transfers the supply voltage into the node when a level of the supply voltage is larger than the level of the node.
18. The internal voltage generation device according to claim 16, wherein the second transfer unit transfers the level of the node into the internal voltage when the level of the node is larger than a level of the internal voltage.
19. The internal voltage generation device according to claim 16, wherein the coupling unit comprises:
a buffer configured to buffer the control signal; and
a capacitor configured to couple between an output terminal of the buffer and the node.
20. The internal voltage generation device according to claim 15, wherein the internal voltage is a high voltage which is used to drive word lines of a semiconductor memory device.
21. The internal voltage generation device according to claim 15, further comprising:
a second sub-voltage pump for pumping the internal voltage in response to the control signal.
22. The internal voltage generation device according to claim 21, wherein the second sub-voltage pump comprises:
a first transfer unit configured to transfer a supply voltage into a node;
a coupling unit configured to increase a level of the node by a level of the control signal when the control signal is activated; and
a second transfer unit configured to transfer the level of the node into the internal voltage.
23. The internal voltage generation device according to claim 22, wherein the first transfer unit transfers the supply voltage into the node when a level of the supply voltage is larger than the level of the node.
24. The internal voltage generation device according to claim 22, wherein the second transfer unit transfers the level of the node into the internal voltage when the level of the node is larger than a level of the internal voltage.
25. The internal voltage generation device according to claim 22, wherein the coupling unit comprises:
a buffer configured to buffer the control signal; and
a capacitor configured to couple between an output terminal of the buffer and the node.
26. The internal voltage generation device according to claim 15, further comprising:
a voltage detector configured to detect the internal voltage, and generate a voltage pumping enable signal;
an oscillator configured to generate the oscillation signal in response to the voltage pumping enable signal; and
a voltage pump configured to pump the internal voltage in response to the oscillation signal.
27. The internal voltage generation device according to claim 26, wherein the voltage pumping enable signal is enabled when a level of the internal voltage falls below a reference voltage.
US13/086,018 2006-12-29 2011-04-13 Internal voltage generation device Abandoned US20110249516A1 (en)

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US8653883B2 (en) * 2012-05-15 2014-02-18 Nanya Technology Corporation Voltage doubler and oscillating control signal generator thereof
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