JPH09319459A - Clock phase control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To automatically generate a hold circuit for holding the value of a counter inside a clock phase control circuit. SOLUTION: A phase comparator circuit 11 compares the phase of an output clock COUT with that of a reference clock REF and based on a count-up instruct signal (u) and a count-down instruct signal (d) outputted from the phase comparator circuit 11, an optimum counter value detection circuit 12 outputs a hold signal HOLD. When the phases of the output clock COUT and reference clock REF get closer, a counter 13 holds its value based on the count-up instruct signal (u), count-down instruct signal (d) outputted from the phase comparator circuit 11 and the hold signal HOLD outputted from the optimum counter value detection circuit 12. Corresponding to the value of the counter 13, a delay circuit 14 increases/decreases the delay quantity of an input clock CIN and controls the phase of the output clock COUT back and forth.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock phase control circuit, and more particularly to a clock phase control circuit for a computer device.

[0002]

2. Description of the Related Art Conventionally, as this type of clock phase control circuit, there is, for example, the "clock skew automatic adjustment circuit" disclosed in Japanese Patent Laid-Open No. 5-100768. In this clock phase control circuit, the reference clock as the phase reference and the output clock are compared in phase, and the counter increases or decreases the value according to the result to increase or decrease the delay amount of the delay circuit. If the phase control is always performed during the operation of the system, the fluctuation of the clock edge (hereinafter referred to as jitter) caused by the noise of the power source or the like becomes large. Therefore, in the conventional clock phase control circuit,
In order to prevent an increase in jitter, a hold signal input terminal for holding the value of the counter is provided, and the counter is controlled by operating or holding the counter as necessary.

FIG. 5 is a circuit block diagram showing an example of a conventional clock phase control circuit. The clock phase control circuit includes a phase comparison circuit 11, a counter 13, and a delay circuit 14 as its main components.

The phase comparison circuit 11 has an output clock COU.
The phases of T and the reference clock REF are compared, and when the phase of the output clock COUT is before the phase of the reference clock REF, the count-up instruction signal u is output as 1 and the count-down instruction signal d is output as 0, When the phase of the output clock COUT is after the phase of the reference clock REF, the count-up instruction signal u is set to 0 and the count-down instruction signal d is set to 1.

The counter 13 has a phase comparison circuit 11 when the hold signal HOLD supplied from the input terminal is 0.
Is counted up when the count-up instruction signal u is 1 and the count-down instruction signal d is 0, and is counted down when the count-up instruction signal u is 0 and the count-down instruction signal d is 1, and is supplied from the input terminal. When the hold signal HOLD is 1, the value is held.

The delay circuit 14 increases or decreases the delay amount of the input clock CIN according to the value of the counter 13, and adjusts the phase of the output clock COUT back and forth.

Next, the operation of such a conventional clock phase control circuit will be described.

When the power supply noise is small when the system is stopped or the like, if 0 is supplied to the input terminal of the hold signal HOLD, the phase comparison circuit 11 causes the phase of the output clock COUT to be the phase of the reference clock REF during that period. In contrast to the above, the count-up instruction signal u is output as 1 and the count-down instruction signal d as 0, and the output clock C
When the phase of OUT is after the phase of the reference clock REF, the count-up instruction signal u is set to 0 and the count-down instruction signal d is set to 1.

The counter 13 counts up when the count-up instruction signal u output from the phase comparison circuit 11 is 1 and the count-down instruction signal d is 0, and the count-up instruction signal u is 0 and the count-down instruction signal d is 1.
Count down when.

The delay circuit 14 increases or decreases the delay amount according to the value of the counter 13 to bring the phase of the output clock COUT closer to the phase of the reference clock REF.

Next, 1 is supplied to the input terminal of the hold signal HOLD when the clock phase control is performed for a certain period,
The value of the counter 13 is held and the delay amount of the delay circuit 14 is fixed.

[0012]

The first problem in the above-mentioned prior art is that it is necessary to generate and supply a hold signal externally by manual operation or the like. The reason is that it does not have a function of automatically generating a hold signal.

The second problem is that when the system is constructed, hardware is required to externally supply the hold signal to each clock phase control circuit. The reason is that each clock phase control circuit does not have a function of generating a hold signal.

A first object of the present invention is to automatically generate a hold signal for holding the value of the counter in the clock phase control circuit, thereby eliminating the trouble of generating and supplying the hold signal externally by a manual operation. It is to provide a phase control circuit.

A second object of the present invention is that each clock phase control circuit has a function of generating a hold signal so that the hold signal is externally supplied to each clock phase control circuit even when the system is configured. The purpose of the present invention is to provide a clock phase control circuit that does not require any hardware.

[0016]

The clock phase control circuit of the present invention compares the phases of the output clock and the reference clock and adjusts the delay amount so that the phase of the output clock approaches the phase of the reference clock. In the circuit
It is characterized by detecting that the phase of the output clock approaches the phase of the reference clock and automatically fixing the delay amount at that time. More specifically, a hold that holds the value of a counter that adjusts the delay amount of the delay circuit by detecting that the phase of the output clock and the phase of the reference clock are close to each other from the phase comparison result of the output clock and the reference clock. It has means for automatically generating a signal.

The clock phase control circuit of the present invention is
The phases of the output clock after the phase adjustment and the reference clock are compared, and when the phase of the output clock is before the phase of the reference clock, the count-up instruction signal is output as 1 and the count-down instruction signal is output as 0, When the phase of the output clock is later than that of the reference clock, a phase comparison circuit that outputs a count-up instruction signal as 0 and a count-down instruction signal as 1, and a count-up instruction signal and a count-down output by this phase comparison circuit When receiving the input of the instruction signal and the reset signal, when the reset signal is 1, the count-up instruction signal changes from 0 to 1 and 1 is taken in, and when the reset signal is 0, the value is 0.
The first flip-flop to be reset and 1 is taken in when the countdown instruction signal changes from 0 to 1 when the reset signal is 1, and the value is 0 when the reset signal is 0.
A second flip-flop to be reset and an OR circuit that logically ORs the outputs of the first flip-flop and the second flip-flop, and both the count-up instruction signal and the count-down instruction signal are 0 at least once. When a counter optimum value detection circuit that outputs 1 as a hold signal when it changes from 1 to 1 and a hold signal that the counter optimum value detection circuit outputs are input,
When the hold signal is 0, the count-up instruction signal output from the phase comparison circuit is 1, and when the count-down instruction signal is 0, the count-up instruction signal is counted up. When the count-up instruction signal is 0, the count-down instruction signal is 1, the count-down instruction signal is counted down. It has a counter that holds the value when the hold signal is 1, and a delay circuit that adjusts the phase of the output clock back and forth by increasing or decreasing the delay amount of the input clock according to the value of the counter.

Furthermore, the clock phase control circuit of the present invention compares the phases of the output clock after the phase adjustment and the reference clock, and when the phase of the output clock is before the phase of the reference clock, the first phase A phase comparison circuit for outputting the count-up instruction signal as 1 and outputting the first count-up instruction signal as 0 when the phase of the output clock is later than the phase of the reference clock; The first count-up instruction signal and the reset signal output from the comparator circuit are received, and the first count-up instruction signal output from the phase comparator circuit is taken in at the rise of the reference clock to obtain the second count-up instruction signal. And a second flip-flop output by the first flip-flop at the rise of the reference clock. A second flip-flop that receives the count-up instruction signal and outputs a third count-up instruction signal; a count-up instruction signal that the phase comparator circuit outputs; and a count-up instruction signal that the first flip-flop outputs. A first exclusive-OR circuit that performs an exclusive-OR and outputs a first exclusive-OR signal;
Of the second count-up instruction signal output from the second flip-flop and the third count-up instruction signal output from the second flip-flop, and outputs a second exclusive OR signal. An exclusive OR circuit and the first
A logical sum of the first exclusive logical sum signal output from the exclusive logical sum circuit and the second exclusive logical sum signal output from the second exclusive logical sum circuit to output a logical sum signal Circuit and when the reset signal is 1, when the OR signal output from the OR circuit changes from 0 to 1, 1 is taken in and output as a hold signal, and when the reset signal is 0, the value is reset to 0. And a third optimum flip-flop, which detects the change of the first count-up instruction signal as 1 → 0 → 1 or 0 → 1 → 0 and outputs 1 as a hold signal. When the hold signal output from the counter optimum value detection circuit is input and the hold signal is 0, the count up instruction signal output from the phase comparator circuit is 1 and the count down instruction signal is 0. A counter that counts down when the count-up instruction signal is 0 and the count-down instruction signal is 1 and holds a value when the hold signal is 1 and the delay amount of the input clock is increased or decreased according to the value of the counter And a delay circuit for adjusting the phase of the output clock back and forth.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a clock phase control circuit according to the first embodiment of the present invention.
The clock phase control circuit according to the present embodiment is mainly composed of a phase comparison circuit 11, a counter optimum value detection circuit 12, a counter 13, and a delay circuit 14.

The phase comparison circuit 11 compares the phases of the output clock COUT after the phase adjustment and the reference clock REF, and the phase of the output clock COUT is the reference clock REF.
If it is before the phase, the count-up instruction signal u is output as 1 and the count-down instruction signal d is output as 0, and the phase of the output clock COUT is the reference clock REF.
If it is after the phase of, the count-up instruction signal u is output as 0 and the count-down instruction signal d is output as 1.

The counter optimum value detection circuit 12 receives the count-up instruction signal u and the count-down instruction signal d output from the phase comparison circuit 11 and the reset signal RESET, and when the reset signal RESET is 1, the count-up instruction signal is received. A flip-flop H ₁₁ that takes in 1 when u changes from 0 to 1 and resets the value to 0 when the reset signal RESET is 0, and a reset signal RES
When ET is 1, the countdown instruction signal d is 0 to 1
Flip-flop H that takes in 1 when it changes to 0 and resets the value to 0 when the reset signal RESET is 0
₁₂ and an OR circuit A ₁₁ that ORs the outputs of the flip-flops H ₁₁ and H ₁₂ , and is 1 when both the count-up instruction signal u and the count-down instruction signal d change from 0 to 1 at least once. Hold signal HO
Output as LD. The symbol I ₁₁ indicates an inverter.

The counter 13 receives the hold signal HOLD output from the counter optimum value detection circuit 12, and when the hold signal HOLD is 0, the count up instruction signal u output from the phase comparison circuit 11 is 1 and the count down instruction signal d. When the count is 0, the count-up instruction signal u is 0, and the count-down instruction signal d is 0.
Count down when is 1, hold signal HOLD
When is 1, the value is retained.

The delay circuit 14 increases or decreases the delay amount of the input clock CIN according to the value of the counter 13 and adjusts the phase of the output clock COUT back and forth.

FIG. 2 is a time chart showing the operation of the clock phase control circuit according to the first embodiment shown in FIG.

Next, the operation of the clock phase control circuit according to the first embodiment configured as described above will be described with reference to FIG.
And it demonstrates in detail with reference to FIG.

The waveform 2-1 is input to the input clock CIN, and the waveform 2-3 is input to the reference clock REF. At this time, the rising edge R ₀ (waveform 2-3) of the reference clock REF is input.
In contrast, the rising edge of the output clock COUT is C
_{If it} is at the position of ₀ (waveform 2-2), the phase comparison circuit 11 outputs the count-up instruction signal u to 1 (waveform 2-
4) The countdown instruction signal d is output as 0 (waveform 2-5).

In this state, the flip-flop H in the optimum counter value detection circuit 12 is reset by the reset signal RESET.
Once ₁₁ and H ₁₂ are reset, counter 13 will
The number of stages is counted up, and the delay circuit 14 increases the delay amount by one stage. Thereby, the phase relationship between the output clock COUT and the reference clock REF is C _{1 of} the waveform 2-2 and the waveform 2-.
Although the third relationship of R _1, since the phase of the output clock COUT does not change state in front with respect to the phase of the reference clock REF, the phase comparator circuit 11 continues 1 count up instruction signal u, count down instruction signal d is output as 0, the counter 13 counts up by one stage, and the delay circuit 14 increases the delay amount by one stage.

When this series of operations is repeated, when the output clock COUT is C _{4 of} the waveform 2-2 and the reference clock REF is R ₄ of the waveform 2-3, the phase of the output clock COUT is relative to the phase of the reference clock REF. Then, the phase comparison circuit 11 outputs 0 as the count-up instruction signal u and 1 as the count-down instruction signal d. At this time,
Since the countdown instruction signal d changes from 0 to 1 as shown in the waveform 2-5, the flip-flop H ₁₂ in the counter optimum value detection circuit 12 becomes 1 as shown in the waveform 2-7.
Since the flip-flop H ₁₁ remains 0 as shown in the waveform 2-6, the hold signal H which is the output of the OR circuit A ₁₁
OLD remains 0 as in waveform 2-8.

Therefore, the counter 13 counts down by one stage, the delay circuit 14 reduces the delay amount by one step, and the phase relationship between the output clock COUT and the reference clock REF is C ₅ of the waveform 2-2 and R of the waveform 2-3. _{As in 5} , the phase of the output clock COUT is earlier than the phase of the reference clock REF, so the phase comparison circuit 11 outputs the count-up instruction signal u as 1 and the count-down instruction signal d as 0. At this time, the count-up instruction signal u changes from 0 to 1 like the waveform 2-4, so that the flip-flop H ₁₁ in the counter optimum value detection circuit 12 has the waveform 2-
6, the value of the flip-flop H ₁₂ is originally 1, so that the hold signal HOLD which is the output of the OR circuit A ₁₁ changes to 1 as in the waveform 2-8. Therefore, the counter 13 holds the value and the delay circuit 14
The delay amount is fixed.

When 0 is input as the reset signal RESET, the values of the flip-flops H ₁₁ and H ₁₂ are both reset to 0, and the hold signal HOLD which is the output of the OR circuit A ₁₁ becomes 0, so that the clock phase is changed. The control circuit starts the phase control of the output clock COUT again.

FIG. 3 is a block diagram showing the configuration of a clock phase control circuit according to the second embodiment of the present invention.
The clock phase control circuit according to the present embodiment replaces the counter optimum value detection circuit 12 in the clock phase control circuit according to the first embodiment shown in FIG. 1 with a counter optimum value detection circuit 12 ′. It was done. Therefore, the phase comparison circuit 11, the counter 13, and the delay circuit 14 are configured and operate in the same manner as in the clock phase control circuit according to the first embodiment.
The same reference numerals are given and detailed description thereof is omitted.

The counter optimum value detection circuit 12 'receives the reference clock REF and the count-up instruction signal u output from the phase comparison circuit 11 and the reset signal RESET, and outputs the phase comparison circuit 11 at the rising edge of the reference clock REF. flip and flop F _31, the count-up instruction signal captures the count-up instruction signal u ₁ output from the flip-flop F ₃₁ at the rising edge of the reference clock REF to output a count up instruction signal u ₁ takes in the count-up instruction signal u to An exclusive OR signal e is formed by exclusive ORing the flip-flop F ₃₂ that outputs u ₂ , the count-up instruction signal u output by the phase comparison circuit 11 and the count-up instruction signal u ₁ output by the flip-flop F _31. an exclusive OR circuit E ₃₁ for outputting a _1, output of the flip-flop F ₃₁ Count up instruction signal u to
An exclusive OR circuit E ₃₂ that outputs an exclusive OR signal e ₂ by exclusive ORing ₁ and the count-up instruction signal u ₂ output by the flip-flop F ₃₂ , and an exclusive logic output by the exclusive OR circuit E _31. A logical sum circuit A ₃₁ that logically sums the sum signal e ₁ and the exclusive logical sum signal e ₂ output by the exclusive logical sum circuit E ₃₂ and outputs a logical sum signal h, and a logical sum when the reset signal RESET is 1. The logical sum signal h output from the circuit A ₃₁ is 0.
Hold signal H when 1 is fetched when changing from 1 to 1
And a flip-flop H ₃₁ that outputs as OLD and resets the value to 0 when reset RESET is 0,
The count-up instruction signal u is 1 → 0 → 1 or 0 → 1 →
The change of 0 is detected and 1 is output as the hold signal HOLD. Reference numeral I ₃₁ denotes an inverter.

FIG. 4 is a time chart showing the operation of the clock phase control circuit according to the second embodiment shown in FIG.

[0035] In the clock phase control circuit according to the second embodiment, the counter optimum value detecting circuit 12 ', the count-up instruction signal u to the output of the phase comparator circuit 11 at the rising flip-flop F ₃₁ is the reference clock REF
Captures and outputs a count-up instruction signal u _1, and outputs a count-up instruction signal u ₂ takes in the count-up instruction signal u ₁ output from the flip-flop F ₃₁ on the rising flip-flop F ₃₂ is the reference clock REF. The exclusive OR circuit E ₃₁ outputs a count-up instruction signal u output from the phase comparison circuit 11 and a flip-flop F _31.
The exclusive OR circuit e outputs the exclusive OR signal e ₁ with the count-up instruction signal u ₁ output from the exclusive OR circuit E 1.
₃₂ performs an exclusive OR of the count-up instruction signal u ₁ output by the flip-flop F ₃₁ and the count-up instruction signal u ₂ output by the flip-flop F ₃₂ , and outputs an exclusive-OR signal e ₂ . The OR circuit A ₃₁ outputs the exclusive OR signal e ₁ output from the exclusive OR circuit E ₃₁ and the exclusive OR circuit E _31.
The exclusive OR signal e ₂ output from ₃₂ is ORed and a logical OR signal h is output. The flip-flop H ₃₁ takes in 1 and outputs it as a hold signal HOLD when the OR signal h output from the OR circuit A ₃₁ changes from 0 to 1 when the reset signal RESET is 1. This allows
When the count-up instruction signal u changes from 1 → 0 → 1 or 0 → 1 → 0, the counter optimum value detection circuit 12 ′ detects this and outputs 1 as a hold signal HOLD. In addition, the flip-flop H ₃₁ has a reset RESE
When T is 0, the value is reset to 0.

[0036]

EXAMPLES Next, examples of the clock phase control circuit according to the first embodiment shown in FIG. 1 will be described.

In the clock phase control circuit of this embodiment, the counter 13 is a 4-bit counter which counts 16 steps from 0000 to 1111.

The delay circuits 14 are respectively 1600 ps,
It is composed of delay gates of 800 ps, 400 ps, and 200 ps, and a selector that selects either a clock that has passed each delay gate or a clock that has not passed each delay gate, and the input clock CI depending on the value of the counter 13.
The delay amount of N is adjusted from 0 ps to 3000 ps in 200 ps steps.

In operation, the input clock CIN (waveform 2-
1) is input, and the reference clock REF (waveform 2-3) delayed by about 4 ns in the same cycle is input to the input terminal of the reference clock REF. At this time, the value of the 4-bit counter 13 is 0100, and the delay amount of the delay circuit 14 is 80.
If the rising edge C _{0 of the} output clock COUT (waveform 2-2) is 650 ps before the rising edge R ₀ of the reference clock REF, the phase comparison circuit 11 outputs the count-up instruction signal u. Is output as 1, and the countdown instruction signal d is output as 0.

In this state, when the reset signal RESET is once set to 0 and the values of the flip-flops H ₁₁ and H ₁₂ in the counter optimum value detection circuit 12 are set to 0, the 4-bit counter 13 counts up by one stage and the value is increased. Then, the delay circuit 14 increases the delay amount by one step (200 ps) to 1000 ps. As a result, the output clock C
The phase difference between the rising edge C _{1 of} OUT and the rising edge R ₁ of the reference clock REF is 450 ps, but the state in which the phase of the output clock COUT is before the phase of the reference clock REF does not change. The circuit 11 continues to output the count-up instruction signal u as 1 and the count-down instruction signal d as 0, and the counter 13 counts up by 1 stage to become the value 0110.
4 increased the delay amount by 200 ps to 1200 ps,
The phase difference between the rising edge C ₂ of the output clock COUT and the rising edge R ₂ of the reference clock REF is 250 p.
s.

When this series of operations is repeated, the counter 1
The value of 3 is 0111 and the delay amount of the delay circuit 14 is 1400p.
rising edge C ₃ of the output clock COUT at s
And the rising edge R ₃ of the reference clock REF is 50 ps, the rising edge C ₄ of the output clock COUT and the rising edge of the reference clock REF when the value of the counter 13 is 1000 and the delay amount of the delay circuit 14 is 1600 ps. phase difference between R ₄ becomes -150 ps.
Here, for the first time, the phase of the output clock COUT becomes later than the phase of the reference clock REF, and the phase comparison circuit 11
Outputs the count-up instruction signal u as 0 and the count-down instruction signal d as 1.

At this time, since the countdown instruction signal d changes from 0 to 1 as shown in the waveform 2-5, the flip-flop H ₁₂ in the counter optimum value detection circuit ₁₂ has the waveform 2-.
Although 1 is taken in as in 7, the flip-flop H ₁₁ remains 0 as in the waveform 2-6, and therefore the OR circuit A ₁₁
The hold signal HOLD, which is the output of, remains at 0 as in the waveform 2-8. Therefore, the counter 13 counts down by one stage to the value 0111, the delay circuit 14 reduces the delay amount by 200 ps to 1400 ps, and the rising edge C ₅ of the output clock COUT is the reference clock R.
Since it is 50 ps before the rising edge R ₅ of EF, the phase comparison circuit 11 again sets the count-up instruction signal u to 1,
The countdown instruction signal d is output as 0.

At this time, the count-up instruction signal u changes from 0 to 1 as shown in the waveform 2-4, so that the flip-flop H ₁₁ in the counter optimum value detection circuit 12 has the waveform 2-.
6, the value of the flip-flop H ₁₂ is originally 1, so that the hold signal HOLD which is the output of the OR circuit H ₁₃ changes to 1 as shown in the waveform 2-8.
Therefore, the counter 13 holds the 4-bit value 0111, and the delay amount of the delay circuit 14 is fixed at 1400 ps.

[0044]

As described above, the first effect of the present invention is that the phase of the output clock and the phase of the reference clock are close to each other from the phase comparison result of the output clock and the reference clock in the clock phase control circuit. The hold signal is automatically generated by detecting this fact and holding the value of the counter that increases or decreases the delay amount of the delay circuit.Therefore, it is not necessary to supply the hold signal from the outside, and the hold signal is generated externally by manual operation etc. That is, the trouble of supplying it becomes unnecessary.

The second effect is that each clock phase control circuit has a function of generating a hold signal, so that the hold signal can be externally supplied to each clock phase control circuit even when the system is configured. The hardware is unnecessary.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a configuration of a clock phase control circuit according to a first embodiment of the present invention.

FIG. 2 is a time chart showing the operation of the clock phase control circuit according to the first embodiment.

FIG. 3 is a circuit block diagram showing a configuration of a clock phase control circuit according to a second embodiment of the present invention.

FIG. 4 is a time chart showing the operation of the clock phase control circuit according to the second embodiment.

FIG. 5 is a circuit block diagram showing an example of a conventional clock phase control circuit.

[Explanation of symbols]

11 phase comparison circuit 12, 12 'counter optimum value detection circuit 13 counter 14 delay circuit A ₁₁ , A ₃₁ logical sum circuit E ₃₁ , E ₃₂ exclusive logical sum circuit F ₃₁ , F ₃₂ flip-flop H ₁₁ , H ₁₂ flip-flop I ₁₁ , I ₃₁ inverter

Claims (3)

[Claims] 1. A clock phase control circuit that compares the phases of an output clock and a reference clock and adjusts the delay amount so that the phase of the output clock approaches the phase of the reference clock. To detect that the phase of the output clock and the phase of the reference clock are close to each other, and to automatically generate a hold signal for holding the value of the counter that adjusts the delay amount of the delay circuit. circuit. 2. The phase of the output clock after the phase adjustment is compared with that of the reference clock, and when the phase of the output clock is before the phase of the reference clock, the count-up instruction signal is 1, and the count-down instruction signal is Output as 0,
A phase comparison circuit that outputs a count-up instruction signal as 0 and a count-down instruction signal as 1 when the phase of the output clock is later than the phase of the reference clock, and the count-up instruction signal and the count-down output by this phase comparison circuit. A first flip-flop that receives an instruction signal and a reset signal, takes in 1 when the count-up instruction signal changes from 0 to 1 when the reset signal is 1, and resets the value to 0 when the reset signal is 0. And a second flip-flop that takes in 1 when the countdown instruction signal changes from 0 to 1 when the reset signal is 1, and resets the value to 0 when the reset signal is 0, the first flip-flop, and the It consists of a logical sum circuit that logically sums the outputs of the second flip-flops, and A counter optimum value detection circuit that outputs 1 as a hold signal when both the indicating signal and the countdown instruction signal change from 0 to 1 at least once, and the input of the hold signal output by this counter optimum value detection circuit, When the hold signal is 0, the count-up instruction signal output from the phase comparison circuit is 1, and when the count-down instruction signal is 0, the count-up instruction signal is counted up. When the count-up instruction signal is 0, the count-down instruction signal is 1, the count-down instruction signal is counted down. A clock having a counter that holds a value when the hold signal is 1 and a delay circuit that increases or decreases the delay amount of the input clock according to the value of the counter and adjusts the phase of the output clock back and forth. Phase control circuit. 3. The phase of the output clock after the phase adjustment and the phase of the reference clock are compared, and the first count-up instruction signal is output as 1 when the phase of the output clock is before the phase of the reference clock. If the phase of the output clock is later than the phase of the reference clock, the phase comparator circuit that outputs the first count-up instruction signal as 0, and the reference clock and the first count that the phase comparator circuit outputs A first flip-flop for receiving the input of the up instruction signal and the reset signal, taking in the first count-up instruction signal output from the phase comparator circuit at the rise of the reference clock, and outputting the second count-up instruction signal; A second count-up instruction signal output from the first flip-flop at the rising edge of the reference clock Second outputting a Ntoappu instruction signal
Of the flip-flop, the count-up instruction signal output from the phase comparison circuit, and the count-up instruction signal output from the first flip-flop are exclusive-ORed to output a first exclusive-OR signal. The exclusive OR circuit of 1, the second count-up instruction signal output from the first flip-flop, and the third count-up instruction signal output from the second flip-flop
A second exclusive-OR circuit that outputs the exclusive-OR signal, a first exclusive-OR signal that the first exclusive-OR circuit outputs, and a second exclusive-OR circuit that outputs the second exclusive-OR signal Two
And an exclusive OR signal of the exclusive OR signal of 1 to output an OR signal, and 1 when the OR signal output from the OR circuit changes from 0 to 1 when the reset signal is 1. And a third flip-flop for resetting the value to 0 when the reset signal is 0, and the first count-up instruction signal is 1 →
A counter optimum value detection circuit that detects a change from 0 → 1 or 0 → 1 → 0 and outputs 1 as a hold signal, and a hold signal that is received when the hold signal output from this counter optimum value detection circuit is input When it is 0, the count-up instruction signal output from the phase comparison circuit is 1, and when the count-down instruction signal is 0, it counts up. When the count-up instruction signal is 0 and the count-down instruction signal is 1, it counts down, and the hold signal is A clock phase control circuit having a counter that holds a value when it is 1 and a delay circuit that increases or decreases the delay amount of the input clock according to the value of the counter and adjusts the phase of the output clock back and forth. .