JPH09312977A - Current command clamping circuit of power converting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to control an output current in accordance with a command even if a current command value is being clamped. SOLUTION: When a current command value iv* exceeds a clamp value, the output iv**(=b) of a function generator 2b becomes iv**= iv*-Δiv*=-(a+c)-Δiv*. Thus, the output d of 1/2 circuit 12 becomes d=(a+iv**+c)/2=-Δiv*/2. Therefore, each output iu**, iv** and iw** of a clamp circuit 10 becomes iu**=a-d=a+Δiv*/2, iv**=-(a+ c)-Δiv**, iw**=c-d=c+Δiv*/2 respectively. In this instance, the total output (iu**+iv**+iw**) of the clamp circuit 10 becomes zero and cuts the zero-phase current included in the current commands iu**, iv**, iw**. As a result, even when current commands iu*, iv*, iw* are clamped, the three-phase condition (total of three phases becomes zero) always holds so that output currents iu, iv, iw are controlled in accordance with the commands.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current command clamp circuit of a power converter suitable for use in a clamp circuit for limiting an output current based on a current command value to a preset clamp value. .

[0002]

2. Description of the Related Art Conventionally, in a three-phase AC power converter, when controlling an output current based on a current command value, an excessive current is applied in order to reduce a current stress applied to a main switch of an inverter to a design value or less. A clamp circuit is provided to limit the clamp value even if a command value is input.

Here, FIG. 4 is a block diagram showing the configuration of an inverter using a conventional current command clamp circuit. In the figure, an inverter 1 is composed of a clamp circuit 2, a control circuit 3, a main switch circuit 4, and the like. The control circuit 3 outputs the outputs iu ^** , iv ^** , iw of the clamp circuit 2.
^The pulse width of the main switch 4 is controlled so that the deviation between ^** and the inverter output currents iu, iv, and iw becomes zero. The output currents iu and iw are detected by the current detectors 5a and 5b and fed back to the input of the control circuit 3, that is, the outputs iu ^** and iw ^** of the clamp circuit 2. The V-phase feedback is iv =-(iu + iw). At this time, the clamp circuit 2 receives the excessive current command values iu ^* , iv ^* , and iw ^* in order to reduce the current stress applied to the main switch 4 of the inverter 1 to the design value or less, and then the function generator 2a. , 2b, 2c limit the clamp value set in advance. The V phase current command is iv ^* =
- it is the ^{(iu * * + iw **)} .

[0004]

However, in the above-mentioned conventional apparatus, when the current command value iv ^* exceeds the clamp value, iv ^** = iv ^* -Δiv ^* , and the three-phase condition: iu
^** + iv ^** + iw ^** = 0 will not hold. That is, iu
^** + iv ^** + iw ^** =-Δiv ^* , and a zero-phase current is generated. In the three-phase three-wire circuit as shown in FIG. 4, the zero-phase current does not actually occur, and a current different from the command flows so that the above three-phase condition is satisfied, and the control is performed according to the current command value. There was a problem that I could not do it. For this reason, a current larger than the clamp value is generated, resulting in an overcurrent, and a protection circuit (not shown) of the inverter operates, causing an abnormal stop. FIG. 5 is a waveform diagram when iv ^** is clamped at 100%. In the figure, the output current i
v reaches a peak value of 170%. Therefore, the rating of the main switch must be 170% or more.

The present invention has been made in view of the above-mentioned circumstances, and provides a current command clamp circuit for a power converter capable of controlling an output current as commanded even when a current command value is clamped. It is an object.

[0006]

In order to solve the above-mentioned problems, in the invention of claim 1, the current command value for the output current of each phase of the polyphase AC is limited to a predetermined clamp value. Means, adding means for adding the current command values limited by the limiting means for each phase, and 1 / n-1 (n) of the addition result added by the adding means.
= Number of phases) and a current command value limited by the limiting means, at least the current command value of the (n-1) phase is subtracted by the division result by the dividing means, and the excluded phase is calculated. And subtracting means for outputting each as a final current command value of each phase including the output of the limiting means.

Further, in the invention according to claim 2,
Limiting means for limiting the current command value for the output current of each phase of the multi-phase alternating current to a predetermined clamp value, adding means for adding the current command value limited by the limiting means for each phase, and addition by the adding means 1 /
n-1 (n = number of phases) and a final current command value of each phase by subtracting the division result of the dividing means from the current command value of each phase limited by the limiting means. And a subtraction unit for outputting as.

Further, in the invention described in claim 3,
The current command clamp circuit of the power converter according to claim 1 or 2, wherein the number of phases n of the polyphase alternating current is three.

The current command value for the output current of each phase of the multi-phase alternating current is limited to a predetermined clamp value by the limiting means, and then added by the adding means. The addition result is 1 /
It is divided by n−1 (n = the number of phases) and subtracted from at least the (n−1) -phase current command value out of the current command values limited by the limiting means. Then, the subtraction result including the output of the limiting means for the excluded phase is supplied to the control circuit at the subsequent stage as the final current command value of each phase.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will now be described with reference to the drawings.

A. Configuration FIG. 1 is a block diagram showing a configuration of a current command clamp circuit of a power converter according to an embodiment of the present invention. The parts corresponding to those in FIG. 4 are designated by the same reference numerals and the description thereof will be omitted. The current command clamp circuit 10 of this embodiment is
It is composed of the same function generators 2a, 2b and 2c as the conventional device, an adder 11, a 1/2 circuit 12 and subtractors 13 and 14. The control circuit, main switch and the like not shown are the same as those of the conventional device. The adder 11 includes a function generator 2a,
The outputs a, b, c of 2b, 2c are added, and (a + b + c)
Is supplied to the 1/2 circuit 12. 1/2 circuit 12
After halving the added value (a + b + c), (a + b
+ C) / 2 is supplied to the adders 13 and 14. The adder 13 receives the output (a + b +) from the output a of the function generator 2a.
c) / 2 is subtracted and supplied to a control circuit (not shown) as the output iu ^** of the clamp circuit 10. The adder 14
Is the above (a + b + c) / from the output c of the function generator 2c.
2 is subtracted and the output iw ^** of the clamp circuit 10 is supplied to a control circuit (not shown).

B. Operation of Embodiment The current command value iv ^* is the same as the conventional device.
Outputs a, c of the function generators 2a, 2c corresponding to u ^* , iw ^*
Is calculated as iv ^* =-(a + c). here,
When the current command value iv ^* exceeds the clamp value, the function generator 2
The output iv ^** (= b) of b is iv ^** = iv ^* −Δiv ^* = −
(A + c) -Δiv ^* . Therefore, 1/2 circuit 1
The output d of 2 is d = (a + iv ^** + c) / 2 = -Δiv ^*
/ 2.

Therefore, each output i of the clamp circuit 10 is
u ^** , iv ^** , and iw ^** are as follows. iu ^** = a-d = a + Δiv ^* / 2 iv ^** =-(a + c) -Δiv ^* iw ^** = c-d = c + Δiv ^* / 2

At this time, the total output (iu ^** + iv ^** + iw ^** ) of the clamp circuit 10 becomes zero, and the current command i
The zero-phase current contained in u ^** , iv ^** , and iw ^** disappears.
As a result, even if the current commands iu ^* , iv ^* , iw ^* are clamped, the three-phase condition (the sum of the three phases becomes zero) is always satisfied, so that the output currents iu, iv, iw are as specified. Controlled by. Here, FIG. 2 shows the output iv of the clamp circuit 10.
It is a waveform diagram of ^** (= b) and output current iv. In the figure, according to the present embodiment, the output iv of the clamp circuit 10
It can be seen that the output current iv is controlled as instructed even when ^** is clamped at 100%.

C. Modified Example Next, FIG. 3 is a block diagram showing a configuration of a current command clamp circuit of a power conversion device according to a modified example of the embodiment of the present invention. Note that the same reference numerals are given to portions corresponding to FIG. In the figure, all current commands iu ^* , iv ^* , iw ^* are input to the clamp circuit 15 from the outside. Further, the 1/3 circuit 16 is provided in place of the 1/2 circuit 12 described above, and after the addition value (a + b + c) is reduced to 1/3, the subtractor 17 for each phase is set to (a + b + c) / 3. Supply to 18 and 19. The subtractor 17 subtracts the above (a + b + c) / 3 from the output a of the function generator 2a and supplies it as the output iu ^** of the clamp circuit 15 to a control circuit (not shown). The subtractor 18 subtracts the above (a + b + c) / 3 from the output b of the function generator 2b, and supplies it as an output iv ^** of the clamp circuit 15 to a control circuit (not shown). Further, the subtractor 19 outputs the output c of the function generator 2c.
The above (a + b + c) / 3 is subtracted from
The output iw ^** of 5 is supplied to a control circuit (not shown).

D. Operation of Modification In the above-described configuration, if the three-phase condition is not satisfied at the outputs a, b, c of the function generators 2a, 2b, 2c, a
+ B + c ≠ 0. However, each current command i
u ^** , iv ^** , and iw ^** are as follows: iu ^** = ad = a- (a + b + c) / 3 iv ^** = bd = b- (a + b + c) / 3 iw ^{* *} = C-d = c- (a + b + c) / 3.

Therefore, the sum of each current command (iu ^** +
iv ^** + iw ^** ) becomes zero, and the three-phase condition is satisfied. That is, according to this modification, the input current command iu ^* ,
Even if the three-phase condition of iv ^* and iw ^* is not satisfied, the current command iu
^Since the three-phase condition of ^** , iv ^** , and iw ^** is established, the output current can be controlled as commanded even if the current command value is clamped.

[0018]

As described above, according to the present invention, the advantage that the output current can be controlled according to the command even if the current command value is clamped is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a waveform diagram of an output iv ^** and an output current iv of the clamp circuit of the embodiment.

FIG. 3 is a block diagram showing a configuration of a current command clamp circuit of a power conversion device according to a modification of the embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of an inverter using a conventional current command clamp circuit.

FIG. 5 is a waveform diagram of an output iv ^** and an output current iv of a conventional clamp circuit.

[Explanation of symbols]

iu ^* , iv ^* , iw ^* current command value 2a, 2b, 2c function generator (limiter) 11 adder (adder) 12 1/2 circuit (divider) 13, 14 subtractor (subtractor) 16 1 / 3 circuit (division means) 17, 18, 19 Subtractor (subtraction means)

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[Procedure amendment]

[Submission date] June 26, 1996

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claim 2

[Correction method] Change

[Correction contents]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0007

[Correction method] Change

[Correction contents]

Further, in the invention according to claim 2,
Limiting means for limiting the current command value for the output current of each phase of the multi-phase alternating current to a predetermined clamp value, adding means for adding the current command value limited by the limiting means for each phase, and addition by the adding means 1 /
n (n = number of phases) and subtracting the division result by the dividing means from the current command value of each phase limited by the limiting means, and outputting each as the final current command value of each phase. And a subtraction unit for performing the subtraction.

Claims (3)

[Claims] 1. A limiting means for limiting a current command value for an output current of each phase of a polyphase alternating current to a predetermined clamp value, and an adding means for adding the current command value limited by the limiting means for each phase. The addition result obtained by the addition means is 1 / n-1
(N = number of phases), and among the current command values limited by the limiting means, at least the (n-1) -phase current command value is subtracted from the division result by the dividing means and excluded. A current command clamp circuit for a power conversion device, comprising: subtraction means for outputting each as a final current command value for each phase, including the output of the phase limiting means. 2. Limiting means for limiting the current command value for the output current of each phase of the polyphase alternating current to a predetermined clamp value, and adding means for adding the current command values limited by the limiting means for each phase. The addition result obtained by the addition means is 1 / n-1
(N = number of phases), and subtracts the division result by the dividing means from the current command value of each phase limited by the limiting means, and outputs each as a final current command value of each phase. A current command clamp circuit for a power converter, comprising: a subtraction unit. 3. The current command clamp circuit for a power converter according to claim 1, wherein the number of phases n of the polyphase alternating current is three.