JPH09312382A - Nonvolatile semiconductor memory device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device corresponding to a fine process by using a low-stem difference double-layer polysilicon structure. SOLUTION: The semiconductor memory device has two channel regions L1 and L2 between a source region 2 and a drain region 3. The channel region L1 on the drain region side is formed under a floating gate electrode 24 via a gate insulating film 23, and the channel region L2 on the source region side is formed under a control gate electrode 30 via the gate insulating film 23. The control gate 30 is provided on the floating gate 24 via an insulating film 31, and further, the control gate 30 is formed in line in a channel length direction of the two channel regions. The source region 2 and the drain region 3 are arranged in line in a channel width direction such that these regions are owned in common by a plurality of semiconductor memory devices. Further, the source region 2 and the drain region 3 are alternately arranged in the channel length direction such that these regions are owned in common by adjacent semiconductor memory devices.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable and erasable nonvolatile semiconductor memory device having a floating gate and a method for manufacturing the same.

[0002]

2. Description of the Related Art Among electrically-rewritable and erasable non-volatile semiconductor memory devices (hereinafter referred to as EEPROMs), flash EEPROMs (hereinafter referred to as flash memories) have attracted attention.

[0005] Conventional EEPROMs are generally based on single-bit erasure, whereas flash memories are premised on erasing in blocks. For this reason, the flash memory is more difficult to use than the conventional EEPROM, but by adopting a 1-bit single element or block erasing, the flash memory is equal to or more than a DRAM (dynamic random access memory). Has attracted attention as a next-generation memory (ROM) that can be expected to have a high degree of integration,
The size of the market is immeasurable.

Various structures and methods have been proposed for flash memories. Of these, the most general structure is the so-called ETO shown in FIGS.
It is called X type. 6 is a plan view and FIG. 7 is FIG.
8 is a sectional view taken along the line AA ′ of FIG. 8, and FIG. 8 is a sectional view taken along the line BB ′ of FIG. 6.

This ETOX type flash memory is shown in FIG.
As shown in FIG. 8, a floating gate 5 is provided via a gate insulating film 10 on the channel forming region between the source region 2 and the drain region 3 provided in the substrate 1 or the well, and the floating gate 5 is further provided. A control gate 6 is provided on the gate electrode 5 via an interpoly insulating film 13. Each memory cell (semiconductor memory element) is element-isolated by the field oxide film 15, but the control gate 6 is connected to adjacent memory cells to form a word line.

Generally, in a floating gate type non-volatile memory, charges are held in a floating gate surrounded by an insulator,
Data is stored using the fact that the threshold voltage at which a channel is formed between the source and drain changes when the control gate is biased, depending on the amount of charge in the floating gate. Different for each method.

In the case of the above-mentioned ETOX type memory cell, data is written by injecting hot electrons generated on the drain side of the channel into the floating gate 5 when a current is passed through the channel. Further, data is erased by removing electrons held in the floating gate 5 by a current (F-N current) flowing through a tunnel in the gate insulating film 10 when a high electric field is applied between the floating gate 5 and the source region 2. This is done by pulling out to the source region 2.

The characteristic of this ETOX type memory cell is that the structure is simple, but as a drawback, since writing is performed by hot electrons on the drain side,
The ratio of the current injected into the floating gate to the channel current, that is, the writing efficiency is low, and thus it is difficult to realize a single power source. It is necessary to keep the variation of the above in a very narrow range, and a very high process and circuit are required.

Next, FIG. 6 shows a state in which the ETOX type memory cells are arranged in an array. Each cell is element-isolated by a field oxide film 15, a source region is formed of a diffusion layer extending in the channel width direction, is connected by a source line 22, and has a common potential. The control gate 6 also extends linearly in parallel with the source line 22 and is a word line common to cells in this direction. Further, the drain is connected to the metal electrode 24 through the contact hole 21, and the metal electrode 24 extends linearly in a line perpendicular to the word line and serves as a bit line common to cells in this direction.

The selection of a specific cell among the cells arranged in an array is performed by matrix-selecting these word lines and bit lines.

As described above, in the ETOX type memory cell, since the drain needs to have a contact hole,
This portion requires an area, and there is a drawback that the element area becomes large in spite of the simple cell structure.

As one of the methods for solving the above-mentioned drawbacks, there is a structure / system proposed in US Pat. No. 5,280,446. 9 to 11 show memory cells of this system. 9 is a plan view, and FIG. 10 is C- in FIG.
FIG. 11 is a sectional view taken along the line C ′ of FIG. 9, and FIG. The structure of this type of memory cell is shown in FIGS.
As shown in FIG. 3, the channel region L formed between the source region 2 and the drain region 3 formed in the substrate 1 or the well is composed of two regions L1 and L2, and the gate insulating layer is formed on the source side channel region L2. The select gate 28 is formed through the film 20, and the drain side channel region L1 is formed.
A floating gate 24 is formed on the gate insulating film 23. Further, a control gate 26 is formed on the floating gate 24 with an interpoly insulating film 25 interposed therebetween. Further, the select gate 28 crosses over the control gate 26 with the insulating film 27 interposed therebetween, and is connected to the select gates 28 of the adjacent memory cells in the channel length direction as described later. The select gate 28 is covered with a silicide layer 29 to reduce the resistance.

With such a structure, for writing, channel hot electron injection from the substrate channel region on the source side to the floating gate electrode, so-called SSI (Source Side Injecti) is performed.
n) method is possible, and high electron injection efficiency is realized as compared with channel hot electron injection on the drain side. With regard to erasing, the problem of overerase is solved by having the select gate 28.

FIG. 9 shows a state in which memory cells of this system are arranged in an array. A gate insulating film (tunnel insulating film) is formed on the drain side channel region of each memory cell.
The control gate 26, which is covered with the floating gate 24 of each cell via the interpoly insulating film, is formed so as to cover the floating gate 24 through the interpoly insulating film. It extends in a line in a direction perpendicular to the direction toward and is common to a plurality of cells. Adjacent cells in that direction are separated from each other by the field insulating film 15.

On the other hand, the select gate 2 which covers the source-side channel region of each memory cell via the gate insulating film 20.
8 is over the control gate 26, in the channel length direction,
That is, it extends linearly in the direction from the source region 2 to the drain region 3 and is common to a plurality of cells in that direction. As a result, a specific cell can be selected by matrix selection of the control gate 26 and the selection gate 28, and the drain can be shared in the channel width direction. Therefore, the drain line 3 is formed by a diffusion layer. By making contact holes unnecessary for each cell, the device area can be reduced. However, a drawback of this method is that the use of the three-layer polysilicon may not be able to cope with a miniaturization process in which the level difference is about 0.35 μm or less.

[0016]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and a sub half μm
In the following non-volatile semiconductor memory device, it is an object of the present invention to provide a non-volatile semiconductor memory device that can cope with a miniaturization process by using a two-layer polysilicon structure having a low step in order to further reduce the area.

Further, the present invention provides a non-volatile semiconductor memory device which eliminates a field oxide film for element isolation and a contact of a diffusion layer, more specifically, an electrically erasable memory element array. It is intended.

[0018]

A nonvolatile semiconductor memory device according to the present invention has two channel regions between a source region and a drain region, and the channel region on the drain region side has a floating gate via a gate insulating film. The channel region on the source region side is formed under the electrode and is formed under the control gate via the gate insulating film, and the control gate rides on the floating gate with the insulating film in between and the channel length of the two channel regions. While being arranged in a line in the direction,
The source region and the drain region linearly extend in the channel width direction of the two channel regions so as to share the source region and the drain region of the plurality of semiconductor memory devices, respectively, and extend in the channel length direction of the two channel regions. The semiconductor memory devices are alternately arranged and shared by adjacent semiconductor memory elements.

In the above-described nonvolatile semiconductor memory device of the present invention, a specific cell can be selected by matrix selection of the control gate and the drain region. Then, the drain can be shared in the channel width direction, and the drain line is formed by the diffusion layer, so that the contact hole for each semiconductor memory element is not necessary, and the element area can be reduced.

The control gates are arranged in parallel in the channel length direction of the two channel regions, and the source region and the drain region are alternately arranged so as to be shared by the adjacent semiconductor memory elements. It is not necessary to provide a field oxide film for element isolation between semiconductor memory elements. Therefore, the field oxide film for separating the semiconductor memory element between the control gates can be omitted.

Further, it is preferable that an isolation region in which an impurity of the same conductivity type as that of the substrate is introduced in a self-aligned manner is formed between the control gates using the control gate as a mask.

A method of manufacturing a non-volatile semiconductor memory device according to the present invention is a method of manufacturing a non-volatile semiconductor memory device having two channel regions between a source region and a drain region. A step of forming a floating gate disposed on the gate insulating film via a gate insulating film, and a mask covering the floating gate and the channel region on the source region are used to share the source region and the drain region of the plurality of semiconductor memory elements, respectively. As described above, a source region and a drain region which extend linearly in the channel width direction of the two channel regions and are alternately arranged in the channel length direction of the two channel regions and which are shared by adjacent semiconductor memory elements are formed. And a step of forming the gate insulating film via the gate insulating film and sandwiching the insulating film. In and ride on the floating gate,
Forming a control gate in a line shape in the channel length direction of the two channel regions.

Furthermore, after the control gates are formed, impurities of the same conductivity type as the substrate are introduced in a self-aligned manner between the control gates,
It is preferable that the control gates are configured so as to separate elements.

With the above-described structure, even if the substrate is dug by etching during the formation of the control gate, ions of the same conductivity type as the substrate are injected in a self-aligned manner to improve the element isolation characteristics. .

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to the drawings. 1 is a plan view, and FIG. 2 is A in FIG.
It is a sectional view taken on line -A '.

In the structure of the memory cell of this embodiment, as shown in FIG. 2, the channel region L between the source region 2 and the drain region 3 formed in the substrate 1 or the well is composed of two regions L1 and L2. The select gate 30 is formed on the source-side channel region L2 via the gate insulating film 20, and the drain-side channel region L is formed.
A floating gate 24 is formed on the gate electrode 1 via a gate insulating film (tunnel oxide film) 23.

Further, the control gate 30 is the floating gate 24.
Insulating film (interpoly insulating film or interpoly insulating film and sidewall insulating film) 31 on the side surface and the upper part thereof
And the two channel regions L1,
The memory cells are arranged in a line in the channel length direction of L2 and are shared by a plurality of memory cells.

Further, the source region 2 and the drain region 3 are arranged linearly in the channel width direction of the two channel regions L1 and L2, and are alternately arranged so as to be shared by adjacent memory cells. ing.

With the above structure, a specific cell can be selected by matrix selection of the control gate 30 and the drain region 2. Then, the drain can be shared in the channel width direction, and the drain line is formed of the diffusion layer, so that the contact hole for each memory cell is unnecessary and the element area can be reduced.

The control gate 30 is arranged in a line in the channel length direction of the two channel regions L1 and L2, and the source region 2 and the drain region 3 are alternately arranged so as to be shared by adjacent memory cells. Therefore, it is not necessary to provide a field oxide film for element isolation between the memory cells. Therefore, the field oxide film is not provided on the substrate 1 in this embodiment.

Further, in the case of this memory cell, since the control gate 30 has a structure that crawls on the diffusion layers of the source region 2 and the drain region 3 formed on the substrate 1, insulation between the two is a problem especially during erasing. Become. Therefore, in this embodiment, the oxide film on the source region 2 and the drain 3 is accelerated to be thicker than the gate insulating film 20 to enhance the insulating property.

With such a structure, writing can be performed by injecting hot electrons generated in the channel. At this time, by controlling the thickness in the channel direction of the oxide film on the side wall of the floating gate 24 on the source side, the position where hot electrons are generated can be controlled on the source side or the drain side of the floating gate 24. For erasing, electrons are extracted to the drain region 3 side.

In FIG. 1 and FIG. 2, Table 1 shows an example of voltage conditions for writing, erasing and reading data in one selected memory cell (SB in the drawings).

[0034]

[Table 1]

Here, FIG. 3 shows a field oxide film 15 for element isolation using the memory cell of the present invention shown in FIG.
2 shows a memory cell array configuration in the case of providing. As can be seen by comparing FIG. 1 and FIG. 3, the memory area in the case of FIG. 1 can be made smaller by the alignment margin of each part than in the case of FIG. In addition, in the sub-half micron generation or less, the dimension thereof is about the optical wavelength of the current stepper, so that the finished field oxide film has a more round shape and requires a further alignment margin.

Further, since the field oxide film 15 has a level difference of not less than one layer of the gate electrode, it directly affects the effective depth of focus in the photolithography process, which eventually becomes a major obstacle to miniaturization. That is, the structure without the field oxide film greatly contributes to the reduction of the alignment margin and the reduction of the element area in terms of the step difference.

As described above, the present invention adopts the contactless structure in which the wiring is performed by the diffusion layer, so that it is more effective in reducing the area.

Further, in the present invention, since the split gate (gate formed on the gate insulating film 20) is provided, there is little problem of excessive erasing, and it is stable and less susceptible to variations in device characteristics due to processes. A storage device can be obtained.

Next, an example of a method of manufacturing the semiconductor memory device of the present invention described above will be described with reference to FIGS.

First, a well or a field oxide film for peripheral circuits is formed on the substrate 1 by using a known substrate forming technique, and then a gate insulating film 2 to be a tunnel oxide film is formed on the substrate 1.
3 to form a polysilicon film 24a for the floating gate 24
To form Here, the introduction of impurities into the polysilicon layer 24a is performed by using a known appropriate method before the next insulating film is formed.

Next, a bottom oxide film which is the lowermost layer film of the inter-poly insulating laminated film 31 is formed by surface oxidation of polysilicon. In the example of the present embodiment, the dry oxidation, which is easy to control the film thickness, is used, but the present invention is not limited to this. Subsequently, a nitride film 31n to be an intermediate layer of the interpoly insulating film 31 is formed (see FIG. 4A).

Then, using the known photoengraving technique and etching technique, the above laminated film, nitride film / bottom oxide film /
The polysilicon layer 24 is patterned to form a floating gate pattern 24 (see FIG. 4B).

Next, using a known photoengraving technique, as shown in FIG.
As shown in (c), a resist mask 40 is formed, and impurity ions of, for example, arsenic (As) ions are implanted into the portions to be the source region 2 and the drain region 3 to form the source region 2 and the drain region 3. .

Subsequently, an insulating sidewall is formed on the side surface of the floating gate 24. In the example of the present embodiment, the gate insulating film 20 serving as the gate oxide film for the split gate and the interpoly laminated film ( In the case of this embodiment, O
The top oxide film of the NO laminated film 31, the insulating sidewall, and the accelerated oxide film on the diffusion layer (source / drain) were simultaneously formed by wet oxidation (FIG. 5D).
reference). The accelerated oxidation refers to a phenomenon in which oxidation is promoted in a portion into which an impurity is injected as compared with a portion without the impurity.

In the case of this method, the number of steps is small and it is simple, but oxygen is diffused in the floating gate edge portion, and the tunnel oxide film at the edge portion becomes thicker than that at the beginning, so-called gate bird's beak occurs. There is also.

The gate insulating film 2 for the split gate
0, the interpoly laminated film 31, and the insulating sidewall are formed differently depending on the driving method of the element or the biasing method. Therefore, the order and method of forming the above are not limited to this. .

Next, a polysilicon layer for the control gate is formed, and known photolithography and etching (for convenience, hereinafter,
This etching is called stack gate etching.)
As shown in FIGS. 5E and 5F, the control gate 30 is processed to obtain the device of the present invention. here,
In the portion indicated by reference numeral 32 in the drawing, the polysilicon layer 30 for the floating gate is not provided in advance, so that the substrate may be dug when the stack gate is etched.

In the example of the above embodiment, the element isolation characteristic is not good in the portion where the substrate is dug. Therefore, in the present invention, immediately after performing the above-described stack gate etching, by self-alignment (self-aligning), impurities of the same conductivity type as the substrate are ion-implanted to improve the element isolation characteristics. Good to configure.

[0049]

As described above, according to the present invention, by adopting the structure without the field oxide film, it is possible to reduce the element area from the viewpoint of reducing the alignment margin and reducing the step. Further, since the contactless diffusion layer structure is adopted, the area can be further reduced.

In addition, since the present invention has a split gate, it is possible to obtain a stable memory device that has less problems such as excessive erasing and is less susceptible to variations in element characteristics due to processes.

[Brief description of drawings]

FIG. 1 is a plan view showing an embodiment of a nonvolatile semiconductor memory device of the present invention.

FIG. 2 is a sectional view taken along the line A-A ′ in FIG.

FIG. 3 is a plan view showing an embodiment of a nonvolatile semiconductor memory device for comparison of the present invention.

FIG. 4 is a process chart showing an example of a method for manufacturing a nonvolatile semiconductor memory device according to the present invention.

FIG. 5 is a process chart showing an example of a method for manufacturing a nonvolatile semiconductor memory device according to the present invention.

FIG. 6 is a plan view showing a so-called ETOX type and a memory cell.

7 is a cross-sectional view taken along the line B-B ′ of FIG.

8 is a sectional view taken along line A-A 'of FIG.

FIG. 9 is a plan view showing a conventional nonvolatile semiconductor device.

10 is a cross-sectional view taken along the line C-C ′ of FIG.

11 is a cross-sectional view taken along the line S-S ′ of FIG.

[Explanation of symbols]

 1 substrate 2 source region 3 drain region 20 gate oxide film 23 gate oxide film 24 floating gate 30 control gate 31 interpoly insulating film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 29/792 (72) Inventor Koji Mori 1-3-6 Nakamagome, Ota-ku, Tokyo Stock company In Ricoh (72) Inventor Masanori Kusunoki 1-3-6 Nakamagome, Ota-ku, Tokyo Within Ricoh Co., Ltd. (72) Inventor Shuya Abe 1-3-6 Nakamagome, Ota-ku, Tokyo In Ricoh Co., Ltd. ( 72) Inventor Naoto Shatani 1-3-6 Nakamagome, Ota-ku, Tokyo Within Ricoh Co., Ltd.

Claims (5)

[Claims] 1. A channel region on the drain region side is formed under a floating gate via a gate insulating film, and a channel region on the source region side is gate insulated. Is formed below the control gate electrode through a film, the control gate rides on the floating gate with an insulating film interposed, and is arranged in a line in the channel length direction of the two channel regions,
The source region and the drain region linearly extend in the channel width direction of the two channel regions so as to share the source region and the drain region of the plurality of semiconductor memory devices, respectively, and extend in the channel length direction of the two channel regions. A non-volatile semiconductor memory device, which is alternately arranged and shared by adjacent semiconductor memory elements. 2. The nonvolatile semiconductor memory device according to claim 1, wherein a plurality of control gates are arranged in parallel in a channel length direction. 3. The non-volatile according to claim 2, wherein an isolation region is formed between the control gates, in which an impurity of the same conductivity type as that of the substrate is introduced in a self-aligned manner using the control gate as a mask. Semiconductor memory device. 4. A method for manufacturing a non-volatile semiconductor memory device having two channel regions between a source region and a drain region, wherein a floating region is disposed on the drain region side channel region with a gate insulating film interposed therebetween. Using a step of forming a gate and a mask covering the floating gate and the channel region on the source region, the channel width direction of the two channel regions is shared so as to share the source region and the drain region of a plurality of semiconductor memory devices. Forming a source region and a drain region that extend in a line shape and are alternately arranged in the channel length direction of the two channel regions and shared by adjacent semiconductor memory elements; and the channel on the source region side. The floating gate is disposed on the region via the gate insulating film, and the insulating film is sandwiched between the floating gate and the floating gate. And a step of forming a control gate in a line shape in a channel length direction of the channel region, the method for manufacturing a nonvolatile semiconductor memory device. 5. The non-volatile according to claim 4, wherein after the control gate is formed, impurities having the same conductivity type as that of the substrate are introduced in a self-aligned manner between the control gates to achieve element isolation between the control gates. Of manufacturing a non-volatile semiconductor memory device.