JPH09312187A - Cpu socket - Google Patents

Cpu socket

Info

Publication number
JPH09312187A
JPH09312187A JP12687696A JP12687696A JPH09312187A JP H09312187 A JPH09312187 A JP H09312187A JP 12687696 A JP12687696 A JP 12687696A JP 12687696 A JP12687696 A JP 12687696A JP H09312187 A JPH09312187 A JP H09312187A
Authority
JP
Japan
Prior art keywords
layer
cpu
capacitor
contact
lsi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12687696A
Other languages
Japanese (ja)
Other versions
JP2856706B2 (en
Inventor
Susumu Kumakura
進 熊倉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Niigata Fuji Xerox Manufacturing Co Ltd
Original Assignee
Niigata Fuji Xerox Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Niigata Fuji Xerox Manufacturing Co Ltd filed Critical Niigata Fuji Xerox Manufacturing Co Ltd
Priority to JP12687696A priority Critical patent/JP2856706B2/en
Publication of JPH09312187A publication Critical patent/JPH09312187A/en
Application granted granted Critical
Publication of JP2856706B2 publication Critical patent/JP2856706B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Connecting Device With Holders (AREA)

Abstract

PROBLEM TO BE SOLVED: To obtain an LSI socket capable of easily being miniaturized and of improving circuit characteristics. SOLUTION: Contacts A11, B12,... are inserted into a multi-layer board 101 on which through holes A11, B12,... with their same number as all pins of an LS19 and are connected on a board on a main body extruded (not shown) by means of contact leads A19, B20,... extruded from a bottom face of the multi-layer board 101. The multi-layer board 101 has an insulation layer, a CND layer 2, a capacitor layer 3, and a Vcc layer 4, or the like between housings 1a and 1b. The capacitor layer 3 is further divided into electrode layers 6 and 8 and a dielectric layer 7.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明はCPUソケット、特
に、多ピンのパソコン用CPU等のLSIが挿入される
コンデンサ付のCPUソケットに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU socket, and more particularly to a CPU socket with a capacitor into which an LSI such as a multi-pin personal computer CPU is inserted.

【0002】[0002]

【従来の技術】CPU用のIC等が挿入されるソケット
には、ICのピンを伝わる不用信号を減衰させるため
に、デスクリートなコンデンサが搭載されていた。(例
えば、実開昭56−138488号公報参照) 通常、ICの電源端子付近には電源ノイズを除去するた
めコンデンサが必要である。多電源を必要とするIC
や、筐体外に輻射される妨害電磁波を除去する等の目的
で、ICのピンのなるべく近くに複数のコンデンサを配
置しようとするとソケットの形状が大きくなり、配線の
引き回しが必要となり浮遊インダクタンスが大きくなっ
て回路特性に影響を与える。
2. Description of the Related Art A socket into which an IC for a CPU is inserted is equipped with a discrete capacitor for attenuating an unnecessary signal transmitted through a pin of the IC. (See, for example, Japanese Utility Model Laid-Open No. 56-138488) Usually, a capacitor is required near the power supply terminal of an IC to remove power supply noise. ICs that require multiple power supplies
Also, if you try to place multiple capacitors as close as possible to the IC pins for the purpose of removing the interference electromagnetic waves radiated to the outside of the housing, the shape of the socket becomes large, and the wiring needs to be routed, and the stray inductance becomes large. Will affect the circuit characteristics.

【0003】[0003]

【発明が解決しようとする課題】上述した従来のCPU
ソケットは、小型化が困難で、回路特性が低下するとい
う欠点があった。
The conventional CPU described above.
The socket has a drawback that it is difficult to miniaturize and the circuit characteristics are deteriorated.

【0004】[0004]

【課題を解決するための手段】第1の発明のCPUソケ
ットは、CPU用のLSIのすべてのピンに対応する数
のスルーホールがあけられており電極層と誘電体層を有
する多層基板にコンタクトを挿入し、前記多層基板の下
面よりコンタクトリードを出し、前記電極層と誘電体層
を利用して形成された積層型のコンデンサに前記コンタ
クトを電気的に接続する。
The CPU socket of the first invention has a number of through holes corresponding to all pins of an LSI for a CPU, and contacts a multilayer substrate having an electrode layer and a dielectric layer. Is inserted, a contact lead is taken out from the lower surface of the multilayer substrate, and the contact is electrically connected to a laminated capacitor formed by using the electrode layer and the dielectric layer.

【0005】第2の発明のCPUソケットは、前記積層
型のコンデンサが接続されるコンタクトが、前記LSI
のVccピンとGNDピンに対応するコントクトであ
る。
In the CPU socket of the second invention, the contact to which the laminated capacitor is connected is the LSI.
This is a contract corresponding to the Vcc pin and the GND pin of.

【0006】[0006]

【発明の実施の形態】次に、本発明について図面を参照
して詳細に説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail with reference to the drawings.

【0007】図1は本発明の一実施形態を示す一部破断
側面図である。図1に示すCPUソケットは、LSI9
のすべてのピンに対応する数のスルーホールA11,B
12・・・・・があけられている多層基板101に、コ
ンタクトA17,B18・・・・・を挿入し、多層基板
101の下面より出ているコンタクトリードA19,B
20・・・・により図示省略した本体側の基板に接続さ
れる。多層基板101は、ハウジング1a〜1bの間
に、絶縁層5,GND層2,コンデンサ層3,Vcc層
4等を有する。コンデンサ層3はさらに電極層6,8と
誘電体層7とに分けられている。
FIG. 1 is a partially cutaway side view showing an embodiment of the present invention. The CPU socket shown in FIG.
Through holes A11, B corresponding to all pins of
The contacts A17, B18 ... Are inserted into the multi-layer substrate 101 in which 12 ...
.. is connected to a main body side substrate (not shown). The multilayer substrate 101 has an insulating layer 5, a GND layer 2, a capacitor layer 3, a Vcc layer 4 and the like between the housings 1a and 1b. The capacitor layer 3 is further divided into electrode layers 6 and 8 and a dielectric layer 7.

【0008】CPUとして用いられるLSI9のピン配
置は確定しているから、CPUソケットとしてはGND
ピン10に対応するスルーホールA11に内層接続ラン
ドA13を,Vccピン11に対応するスルーホールB
12に内層接続ランドB14を設け、内層接続ランドA
13と内層接続ランドB14との間に、誘電体層7を中
にはさんで電極6b,8bで形成されたコンデンサ12
を、電極層6,8を用いて接続すれば、Vccピン11
に存在するノイズをGNDピン11の方にバイパスでき
る。
Since the pin arrangement of the LSI 9 used as a CPU is fixed, the CPU socket is GND
The inner layer connection land A13 is provided in the through hole A11 corresponding to the pin 10 and the through hole B is provided in the Vcc pin 11
The inner layer connection land B14 is provided in 12 and the inner layer connection land A
A capacitor 12 formed of electrodes 6b and 8b with a dielectric layer 7 interposed between the capacitor 13 and the inner layer connection land B14.
Is connected by using the electrode layers 6 and 8, the Vcc pin 11
The noise present at 1 can be bypassed towards GND pin 11.

【0009】[0009]

【発明の効果】本発明のCPUソケットは、コンデンサ
を内蔵する多層基板にコンタクトを挿入したので、小型
化が容易で、回路特性特性を向上できるという効果があ
る。
Since the CPU socket of the present invention has the contacts inserted in the multilayer substrate containing the capacitor, it is easy to miniaturize and the circuit characteristic characteristics can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施形態を示す一部破断側面図であ
る。
FIG. 1 is a partially cutaway side view showing an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 コンタクト 2 GND層 3 コンデンサ層 4 Vcc層 5 絶縁層 6 電極層 7 誘電体層 8 電極層 9 LSI 10 GNDピン 11 Vccピン 12 コンデンサ 1 Contact 2 GND Layer 3 Capacitor Layer 4 Vcc Layer 5 Insulating Layer 6 Electrode Layer 7 Dielectric Layer 8 Electrode Layer 9 LSI 10 GND Pin 11 Vcc Pin 12 Capacitor

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 CPU用のLSIのすべてのピンに対応
する数のスルーホールがあけられており電極層と誘電体
層を有する多層基板にコンタクトを挿入し、前記多層基
板の下面よりコンタクトリードを出し、前記電極層と誘
電体層を利用して形成された積層型のコンデンサに前記
コンタクトを電気的に接続することを特徴とするCPU
ソケット。
1. A contact is inserted into a multilayer substrate having a number of through holes corresponding to all pins of a CPU LSI and having an electrode layer and a dielectric layer, and contact leads are provided from the lower surface of the multilayer substrate. The CPU is characterized in that the contact is electrically connected to a multilayer capacitor formed by utilizing the electrode layer and the dielectric layer.
socket.
【請求項2】 前記積層型のコンデンサが接続されるコ
ンタクトが、前記LSIのVccピンとGNDピンに対
応するコントクトである請求項1記載のCPUソケッ
ト。
2. The CPU socket according to claim 1, wherein the contact to which the multilayer capacitor is connected is a contact corresponding to the Vcc pin and the GND pin of the LSI.
【請求項3】 前記LSIのVccピンとGNDピンに
対応するコントクトが挿入される前記スルーホールに内
層接続ランドを設けた請求項1または2記載のCPUソ
ケット。
3. The CPU socket according to claim 1, wherein an inner layer connection land is provided in the through hole into which a contact corresponding to the Vcc pin and the GND pin of the LSI is inserted.
【請求項4】 前記内層接続ランドが前記電極層に接続
された請求項1,2または3記載のCPUソケット。
4. The CPU socket according to claim 1, wherein the inner layer connection land is connected to the electrode layer.
JP12687696A 1996-05-22 1996-05-22 CPU socket Expired - Fee Related JP2856706B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12687696A JP2856706B2 (en) 1996-05-22 1996-05-22 CPU socket

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12687696A JP2856706B2 (en) 1996-05-22 1996-05-22 CPU socket

Publications (2)

Publication Number Publication Date
JPH09312187A true JPH09312187A (en) 1997-12-02
JP2856706B2 JP2856706B2 (en) 1999-02-10

Family

ID=14946040

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12687696A Expired - Fee Related JP2856706B2 (en) 1996-05-22 1996-05-22 CPU socket

Country Status (1)

Country Link
JP (1) JP2856706B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016153796A (en) * 2016-03-31 2016-08-25 スリーエム イノベイティブ プロパティズ カンパニー Ic device testing socket
WO2023120708A1 (en) * 2021-12-24 2023-06-29 パナソニックIpマネジメント株式会社 Electrolytic capacitor and method for manufacturing electrolytic capacitor

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5788166B2 (en) 2010-11-02 2015-09-30 新光電気工業株式会社 Connection terminal structure, manufacturing method thereof, and socket

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016153796A (en) * 2016-03-31 2016-08-25 スリーエム イノベイティブ プロパティズ カンパニー Ic device testing socket
WO2023120708A1 (en) * 2021-12-24 2023-06-29 パナソニックIpマネジメント株式会社 Electrolytic capacitor and method for manufacturing electrolytic capacitor

Also Published As

Publication number Publication date
JP2856706B2 (en) 1999-02-10

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Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 19981027

LAPS Cancellation because of no payment of annual fees