JPH09311735A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect the abnormality of clocks on a data processor mounting the clocks. SOLUTION: More than two clocks are mounted on the data processor. A read means 13 reading time information that the whole clocks generate at the time of supplying power, a judgment means 14 judging whether a difference between time information that the read means 13 reads is within a prescribed allow able value or not and an output means 15 outputting the abnormality of the clocks when the judgment means 14 judges that the difference is not within the allow able value are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device equipped with a timepiece, and more particularly to a data processing device capable of detecting abnormality of a timepiece.

[0002] A data processing device may adopt a configuration in which data processing is performed according to the time generated by a clock. With this configuration, if the time generated by the clock deviates from the regular time, accurate data processing cannot be executed. From now on, it is necessary to construct a configuration that can detect whether or not a failure has occurred in the clock.

[0003]

2. Description of the Related Art In a data processing device, a battery-backed real time clock module (RTC) is used.
Uses to generate the time.

In a conventional data processing device, as shown in FIG. 9, one real-time clock module is mounted. Then, while the power is turned on, the software timer is used to check whether or not the real-time clock module is generating an accurate time.

[0005]

However, according to such a conventional technique, it is checked whether the real-time clock module is normal or not while the power of the data processing device is turned on. When a failure occurs in the real-time clock module while the power of the data processing device is not turned on, there is a problem that it cannot be detected.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a new data processing device capable of accurately detecting an abnormality of a mounted timepiece.

[0007]

FIG. 1 shows the principle configuration of the present invention. In the figure, reference numeral 1 denotes a data processing device provided with the present invention.

The data processing apparatus 1 of the present invention comprises a plurality of clocks 10 composed of hardware and a data processing means 11.
The display means 12, the reading means 13, the judging means 14, the output means 15, the specifying means 16, the resetting means 17, and the rechecking means 18 are provided.

The clock 10 generates time information. The data processing means 11, for example, treats the time information generated by the specific timepiece 10 designated in advance as valid,
Data processing is executed according to the time information. The display means 12 outputs display information.

The reading means 13 reads the time information generated by the timepiece 10. The judging means 14 judges whether or not the difference between the time information read by the reading means 13 falls within a prescribed allowable value. The output means 15 outputs the abnormality of the timepiece 10 to the display means 12.

The specifying means 16 specifies the timepiece 10 in an abnormal state according to the majority logic when three or more timepieces 10 are mounted. The resetting means 17 resets the regular time information for the clock specified by the specifying means 16.
The recheck means 18 is the timepiece 1 specified by the specifying means 16.
Check again whether 0 is abnormal.

In the data processing apparatus 1 of the present invention having the above-described structure, the reading means 13 reads the time information generated by all the clocks 10 when the power is turned on, and receives the time information.
The judging means 14 judges whether or not the difference between the time information read by the reading means 13 falls within a prescribed allowable value, and when the judging means 14 judges that the difference does not fall within the allowable value,
The output unit 15 outputs the abnormality of the timepiece to the display unit 12.

Further, when the judging means 14 judges that the time value is not within the allowable value and three or more timepieces 10 are mounted, the specifying means 16 uses the time information read by the reading means 13 to make a majority decision. According to the logic, the clock 10 in the abnormal state is specified, and in response to this, the output means 15
While outputting the identifier of the timepiece 10 specified by the specifying means 16, the timepiece abnormality is output to the display means 12.

Then, the resetting means 17 comprises the specifying means 16
The regular time information is reset for the clock 10 specified by the resetting means 18 and the resetting means 18 reads the time information generated by all the clocks 10 after the resetting processing by the resetting means 17. Then, according to the time information, it is rechecked whether or not the reset destination timepiece 10 is abnormal, and in response to this, the output means 15 is conditioned that the recheck means 18 confirms the abnormality of the timepiece. Outputs a clock error.

As described above, the data processing apparatus 1 of the present invention adopts a configuration in which a plurality of timepieces 10 are mounted, and compares the time information generated by the timepieces 10 when the power is turned on to detect the abnormality of the timepiece 10. Since the configuration for detecting is adopted, it becomes possible to accurately detect the abnormality of the mounted timepiece 10.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail according to embodiments. FIG. 2 shows an embodiment of the data processing apparatus 1 having the present invention.

In addition to the CPU 20, the data processing device 1 of the present invention according to this embodiment includes a real time clock module 21-0 indicated by RTC0, a real time clock module 21-1 indicated by RTC1, and the data processing device 1. Of the real-time clock module 21-i (i = 0,1) when the power of the
-READ control mechanism 23 for controlling reading of time information from -i and their real-time clock module 2
A clock check program 24 for detecting abnormality 1-i.

FIGS. 3 and 4 show an example of a processing flow executed by the clock check program 24 in this embodiment. Next, the operation of this embodiment will be described in detail according to these processing flows.

When the user requests the initialization of the two real-time clock modules 21-i, the clock check program 24 interacts with the real-time clock modules 21-i as shown in the processing flow of FIG. The current time information is simultaneously set in the module 21-i.

With this initial setting, the two real-time clock modules 21-i simultaneously start time counting processing from the time information of the initial setting. In this way, the two real-time clock modules 21-i
When the power of the data processing device 1 is turned on, the time counting process is executed while receiving the power supply of the device. On the other hand, when the power of the data processing device 1 is turned off, the time counting process is executed while receiving the power supply from the battery 22. become.

Then, the clock check program 24
When the power of the data processing device 1 is turned on, as shown in the processing flow of FIG.
The D control mechanism 23 is used to read the time information generated by the two real-time clock modules 21-i, and in the subsequent step 2, the difference value between the two read time information is calculated.

Subsequently, in step 3, it is judged whether or not the calculated difference value is smaller than a preset allowable value, and when it is judged that it is smaller, the process proceeds to step 4 and the real-time clock module 21. -i Outputs that i is normal to the display screen. On the other hand, if it is determined that the real time clock module 21-i is not small, the process advances to step 5 to output to the display screen that the real-time clock module 21-i has an abnormality.

In this way, the data processing apparatus 1 of the present invention according to this embodiment has a configuration in which two battery-backed real-time clock modules are mounted, and when the power is turned on, these real-time clock modules are generated. Since the time information is compared to detect whether or not there is an abnormality in the real-time clock modules, the abnormality of the mounted real-time clock modules can be accurately detected.

In this embodiment, two real-time clock modules are mounted. However, even when three or more real-time clock modules are mounted, the abnormality of the real-time clock module can be accurately detected by the same process.

FIG. 5 shows another embodiment of the data processing device 1 having the present invention. In addition to the CPU 20, the data processing device 1 of the present invention according to this embodiment includes a real time clock module 21-0 indicated by RTC0 and an RT.
Real-time clock module 21-1 indicated by C1
And the real-time clock module 21-2 indicated by the RTC 2 and the real-time clock module 21-i (i = 0,1,2) when the power of the data processing device 1 is cut off.
22, a READ control mechanism 23 for controlling the reading of the time information from the real-time clock module 21-i, and a WRITE controlling the writing of the time information to the real-time clock module 21-i. The control mechanism 25 and the clock check program 24 for detecting an abnormality of the real-time clock modules 21-i are provided.

The WRITE control mechanism 25 has two operation modes, a simultaneous write mode and an independent write mode. As shown in FIG. 6, in the simultaneous write mode, three real time clock modules 21-i are provided.
, And the time information is simultaneously written in the independent write mode. As shown in FIG. 6, the time information is written to the one selected by the address in the three real-time clock modules 21-i. It will be.

FIG. 7 and FIG. 8 show an embodiment of the processing flow executed by the clock check program 24 in this embodiment. Next, the operation of this embodiment will be described in detail according to these processing flows.

The clock check program 24 sets the WRITE control mechanism 25 to the simultaneous write mode as shown in the processing flow of FIG. 7 when the user requests the initialization of the three real-time clock modules 21-i. By interacting with the user, the current time information is simultaneously set for those real-time clock modules 21-i.

With this initial setting, the three real-time clock modules 21-i simultaneously enter the time counting process from the time of the initial setting. In this way, 3
The two real-time clock modules 21-i perform clock processing while receiving power from the data processing apparatus 1 when the data processing apparatus 1 is powered on, while receiving power from the battery 22 when the data processing apparatus 1 is powered off. While performing the timekeeping process.

Then, the clock check program 24
When the data processing device 1 is powered on, as shown in the processing flow of FIG.
Using the D control mechanism 23, the time information generated by the three real-time clock modules 21-i is read, and in the subsequent step 2, the maximum time / minimum time information of the read three time information is specified and the maximum A difference value between the time information and the minimum time information is calculated.

Subsequently, in step 3, it is judged whether or not the calculated difference value is smaller than a preset allowable value, and when it is judged that the difference value is smaller than the preset allowable value, the process proceeds to step 4 and the real time clock module 21. -i Outputs that i is normal to the display screen.

On the other hand, when it is determined in step 3 that the difference value between the maximum time information and the minimum time information is not smaller than the allowable value, the process proceeds to step 5 and abnormal time information is generated according to the majority logic. The real-time clock module 21-i that is running
Set the RITE control mechanism 25 to the independent light mode,
By interacting with the user, the current time information is set for the identified abnormal real-time clock module 21-i.

Subsequently, when the prescribed time has elapsed in step 7 and it is judged that the prescribed time has elapsed, the routine proceeds to step 8, where the READ control mechanism 23 is used to generate the time when the three real-time clock modules 21-i generate. Read the information. Subsequently, in step 9, the time information generated by the real-time clock module 21-i specified in step 5 included in the read time information and the time information generated by other real-time clock modules 21-i. The difference value of is calculated.

Subsequently, in step 10, it is judged whether or not the calculated difference value is smaller than a preset allowable value. When it is judged that the difference value is smaller than that, the process proceeds to step 4, and the real time clock module 21 is operated. -If the i is normal is output to the display screen, and if it is determined that it is not small, proceed to step 11 and output to the display screen that the real-time clock module 21-i identified in step 5 is abnormal. To do.

In this way, the data processing device 1 of the present invention according to this embodiment has a configuration in which three battery-backed real-time clock modules are mounted, and when the power is turned on, these real-time clock modules are generated. By detecting the abnormal real-time clock module by comparing the time information, and checking the real-time clock module once judged to be abnormal once, the abnormality of the mounted real-time clock module can be detected accurately. Will be able to detect.

In this embodiment, three real-time clock modules are mounted. However, even when four or more real-time clock modules are mounted, an abnormality of the real-time clock module can be accurately detected by the same process. Further, although the configuration is adopted in which the real-time clock module once determined to be abnormal is rechecked, this recheck may be omitted.

[0037]

As described above, the data processing apparatus of the present invention adopts a configuration in which a plurality of timepieces are mounted, and compares the time information generated by these timepieces when the power is turned on to detect the abnormality of the timepiece. Since the configuration for detecting is adopted, it becomes possible to accurately detect the abnormality of the mounted clock.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is an embodiment of the present invention.

FIG. 3 is a processing flow executed by a clock check program.

FIG. 4 is a processing flow executed by a clock check program.

FIG. 5 is another embodiment of the present invention.

FIG. 6 is an explanatory diagram of an operation mode of the WRITE control mechanism.

FIG. 7 is a processing flow executed by a clock check program.

FIG. 8 is a processing flow executed by a clock check program.

FIG. 9 is an explanatory diagram of a conventional technique.

[Explanation of symbols]

 1 data processing device 10 clock 11 data processing means 12 display means 13 reading means 14 judging means 15 output means 16 specifying means 17 resetting means 18 rechecking means

Claims (3)

[Claims] 1. A data processing device equipped with a timepiece, comprising two or more timepieces, and reading means for reading time information generated by all the clocks when the power is turned on, and a time read by the reading means. It is provided with a judging means for judging whether or not the difference between the information falls within a prescribed allowable value, and an output means for outputting a clock abnormality when the above judging means judges that the difference does not fall within the allowable value, Characteristic data processing device. 2. A data processing device equipped with a timepiece, comprising three or more timepieces, and a reading means for reading time information generated by all the clocks when the power is turned on, and a reading time for the reading means. A judgment means for judging whether or not the difference between the information is within a prescribed allowable value, and the time information read by the reading means is used in accordance with the logic of the majority decision when the judging means judges that the difference does not fall within the allowable value. A data processing device comprising: a specifying unit that specifies a watch in an abnormal state; and an output unit that outputs a watch error while outputting the identifier of the watch specified by the specifying unit. 3. The data processing apparatus according to claim 2, wherein a resetting means for resetting the regular time information to the clock specified by the specifying means, and a whole clock after the resetting processing of the resetting means. And a re-check means for re-checking whether or not the reset destination clock is abnormal according to the time information, the output means specifying the specifying means by the re-check means. A data processing device characterized by outputting a clock abnormality on condition that a clock abnormality is confirmed.