JPH09311163A - Test generating device and test generating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve test generating efficiency by executing, in addition to a failure simulation corresponding to every generation of test, a failure simulation to the pattern converted to a shift pattern. SOLUTION: A test generating device 10 is formed of a test generating routine 2, a failure simulation routine 3, and a shift pattern converting routine 4. A generated test pattern is used for failure simulation, and the result is accumulated in a failure detection information data base 8 of each node. This pattern is converted to a shift pattern, accumulated in a test pattern data base 11, and used for failure simulation, and the result is accumulated in the data base 8. All detectable failures in a circuit are compared with the data base 8, and when a failure non-detected node is present, the procedure is repeated from the first, and when it is absent, the test patterns accumulated in the data base 11 are collected to form a final test pattern 9. Thus, the number of failures detectable with the same pattern is increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to reduction of the number of test patterns at the time of test generation in a full scan design and improvement of test generation efficiency.

[0002]

2. Description of the Related Art In a conventional test generator in a full scan design, a fault simulation during a shift operation is not executed, and a fault that can be detected only by the shift operation is newly generated and detected. . Therefore, duplication of test generation for generating a fault that can be detected by the shift operation and an increase in the number of test patterns occur.

The system configuration and flow of a conventional test generation device will be described below with reference to the drawings. FIG.
1 shows a system configuration of a conventional test generation device. Reference numeral 1 denotes a test generation device, which includes a test generation routine 2, a fault simulation routine 3, and a shift pattern conversion routine 4.
It is composed of The function library 5 and the circuit net information 6 are input to the test generation device 1. Reference numeral 7 indicates a test pattern database in which the generated test patterns are stored, and 8 indicates a failure detection information database for each node. 9 is a final test pattern.

FIG. 11 shows a flow chart of a conventional test generator. In step S1, the test generation routine 2 is used to generate a test pattern capable of detecting a failure of a node in the circuit. In the test generation performed in step S1, all scan registers in the circuit are considered as externally accessible virtual primary input / output pins.

The test pattern generated in step S1 is once stored in the test pattern database 7,
Further, it is input to the failure simulation routine 3. In step S2, a node having a detectable fault is recognized by the test pattern and is stored in the fault detection information database 8 for each node.

In step S3, it is determined whether or not there is a node in which no fault has been detected by comparing all detectable faults in the circuit with the fault detection information database 8 for each node. In the case of Y in step S3, S1 to S3 are repeated for the node in which no failure has been detected. Step S
In the case of 3 and N, the test patterns accumulated as the test pattern database 7 in S4 are put together.

Since the summarized test pattern considers all the scan registers in the circuit as virtual primary inputs / outputs, in order to enable shift-in from the scan-in pin or shift-out from the scan-out pin of the actual circuit, S5 is selected. Test pattern conversion routine 4
Is used for shift pattern conversion. The test pattern obtained by the shift pattern conversion becomes the final test pattern 9.

[0008]

SUMMARY OF THE INVENTION A first aspect of the present invention is to provide a test generation device capable of improving test generation efficiency and reducing the number of test patterns by performing fault simulation even during shift operation. Is.

A second aspect of the invention is to improve the efficiency of test generation by applying a random pattern to a primary input pin irrelevant to the shift operation and then performing fault simulation, and to reduce the number of test patterns. It is intended to obtain a generator.

The third aspect of the present invention can improve the efficiency of test generation by performing a fault simulation even during the shift operation.
Further, the present invention aims to obtain a test generation method that can reduce the number of test patterns.

According to a fourth aspect of the present invention, a random pattern is applied to a primary input pin irrelevant to a shift operation, and then a fault simulation is performed to improve the efficiency of test generation and reduce the number of test patterns. It is intended to obtain a generation method.

[0012]

According to a first aspect of the present invention, in a test generator in a full-scan design, each time a test is generated, the test simulation device adds the pattern to a fault simulation for that pattern. The failure simulation for the shift pattern is also executed.

In the test generating apparatus of the second invention, when the fault simulation is executed for the test pattern converted into the shift pattern, the random pattern is applied to the primary input pin irrelevant to the shift operation.

In the test generating method according to the third invention, in the test generating method in the full scan design, a fault simulation is executed for the pattern each time a test is generated, and then the pattern is converted into a shift pattern. The conversion is also performed, and the failure simulation for the converted pattern is also executed.

In the test generation method of the fourth aspect of the present invention, when the failure simulation is performed on the test pattern converted into the shift pattern, the random pattern is applied to the primary input pin which is not related to the shift operation.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a system configuration of a test generation device in consideration of a shift operation. Reference numeral 10 shows a test generation device in consideration of the shift operation. The test generation device 10 includes a test generation routine 2, a failure simulation routine 3, and a shift pattern conversion routine 4.

The function library 5 and the circuit net information 6 are input to the test generator 10. Reference numeral 7 indicates a test pattern database in which the generated test patterns are stored, and 8 indicates a failure detection information database for each node. 9 is a final test pattern. Reference numeral 11 denotes a test pattern database that has undergone shift pattern conversion.

FIG. 2 shows a flow chart of the test generation apparatus in consideration of the shift operation. The test pattern generated in step S1 is used for the fault simulation in step S2. The result is stored in the failure detection information database 8 of each node.

In step S5, the result of shift pattern conversion of this test pattern is stored in the shift pattern converted test pattern database 11, and is further used for failure simulation in step S6. This result is also stored in the failure detection information database 8 of each node.

In step S3, by comparing all detectable faults in the circuit with each node fault detection information database 8, it is determined whether or not there is a fault undetected node. In the case of Y in step S3, S1, S2, S5, S6, and S3 are repeated for the node in which no failure has been detected. In the case of N in step S3, the test patterns accumulated in the test pattern database 11 that have been subjected to the shift pattern conversion in step S7 are collected to form the final test pattern 9.

In the embodiment of the present invention, by adding the fault simulation to the shift pattern converted test pattern, the number of faults that can be detected when the same pattern is used is increased.

A description will be given below with reference to FIG. FIG. 3 shows an example of a circuit designed for full scan. 12 ・ 14 ・ 15
Is an AND element, 13 is an OR element, and 16 and 17 are scan FFs. Since 16 and 17 can be regarded as virtual primary input / output pins, FIG. 3 can be divided into four combination blocks as shown in FIG. Less than,
For simplicity of explanation, attention is paid only to the output signal of each block.

In the test generation routine 2, elements 12 to 1
It is assumed that a test pattern for detecting a 0 fault for the 5 output pins is generated. An example of this test pattern is shown in FIG.

When this test pattern is converted into a shift pattern, as shown in FIG. 6, virtual primary pins E and F are generated.
The input to is input serially from the scan pin of the actual circuit by using the shift operation.

During the first shift operation, the scan FF
Therefore, 0 is assigned to 16, and in this case, a failure of 1 can be detected for the AND element 15 by performing failure simulation.

As described above, when the fault simulation is performed using the test pattern converted into the shift pattern,
The same test pattern can be used to detect faults that were not currently detected. That is, the number of repetitions of steps S1 to S3 in the conventional flow chart can be reduced, and the efficiency of test generation is improved. Further, the number of test patterns can be reduced as compared with the conventional test generation.

Embodiment 2. FIG. 7 shows a system configuration of a test generation device that applies a random pattern to a primary input pin that is not related to a shift operation when a failure simulation is performed on the test pattern after the shift pattern conversion.

Reference numeral 18 denotes a test generator for applying a random pattern to the primary input pin which is not related to the shift operation when the failure simulation is executed on the test pattern after the shift pattern conversion. Reference numeral 19 shows a random pattern insertion routine, and 20 shows a test pattern database after shift pattern conversion / random pattern insertion.

FIG. 8 is a flow chart of a test generator for applying a random pattern to a primary input pin that is not related to a shift operation when a failure simulation is performed on the test pattern after the shift pattern conversion.

Steps S1 to S5 are the same as in the first embodiment. In step S8, the random pattern insertion routine 19 is used to insert a random pattern into the primary input pin irrelevant to the shift operation, with respect to the test pattern converted into the shift pattern.

The result is stored in the test pattern database 20 after the shift pattern conversion / random pattern insertion, and is further input to the fault simulation in S9. The result is stored in the failure detection information database 8 of each node.

In step S3, as in the first embodiment,
It is determined whether there is a node for which no failure has been detected. Step S
In the case of Y in 3, the steps S1, S2, S5, S8, S9, and S3 are repeated for the node in which no failure has been detected. In the case of N in step S3, the test patterns accumulated in the test pattern database 20 after the shift pattern conversion / random pattern insertion in step S7 are collectively set as the final test pattern 9.

In the embodiment of the present invention, by applying the random pattern to the primary input pin not related to the shift operation, the test pattern can be generated more efficiently than in the first embodiment. As shown in FIG. 9 in the first shift operation of FIG. 6 described in the first embodiment, as shown in FIG. 9, when 0 is applied as a random pattern to the primary input pin A unrelated to the shift operation, the OR element 13 It is possible to detect even one failure for.

As described above, by applying the random pattern to the primary input pin irrelevant to the shift operation, the same test pattern can be used to detect a fault not detected in the first embodiment, and the efficiency of test generation can be improved. Is improved and the number of test patterns can be reduced.

As described above, according to the embodiment of the present invention, the failure simulation is performed even during the shift operation, or the failure simulation is performed by applying the random pattern to the primary input pin unrelated to the shift operation. The test generation efficiency is improved and the number of test patterns can be reduced.

[0036]

According to the first aspect of the present invention, it is possible to obtain a test generation device capable of improving the efficiency of test generation by performing fault simulation even during a shift operation and reducing the number of test patterns.

According to the second aspect of the present invention, a random pattern is applied to a primary input pin irrelevant to the shift operation, and then failure simulation is performed to improve the efficiency of test generation and reduce the number of test patterns. It is possible to obtain a test generation device that can do so.

According to the third aspect of the present invention, it is possible to obtain a test generation method capable of improving the efficiency of test generation by performing fault simulation even during the shift operation and reducing the number of test patterns.

According to the fourth aspect of the present invention, a random pattern is applied to a primary input pin irrelevant to the shift operation, and then failure simulation is performed to improve the efficiency of test generation and reduce the number of test patterns. It is possible to obtain a possible test generation method.

[Brief description of drawings]

FIG. 1 is a diagram showing a system configuration of a test generation apparatus in consideration of a shift operation according to an embodiment of the present invention.

FIG. 2 is a flow diagram of a test generation apparatus considering a shift operation according to an embodiment of the present invention.

FIG. 3 is a diagram showing an example of a circuit designed for full scan according to an embodiment of the present invention.

FIG. 4 is a diagram showing an example in which FIG. 3 is divided by virtual primary input / output pins.

5 is a diagram showing an example of a test pattern for FIG.

FIG. 6 is a diagram showing an example of shift pattern conversion of FIG. 5;

FIG. 7 is a system configuration of a test generator that applies a random pattern to a primary input pin that is not related to a shift operation when a failure simulation is performed on a test pattern after shift pattern conversion according to another embodiment of the present invention. FIG.

FIG. 8 is a flow diagram of a test generation device that applies a random pattern to a primary input pin that is not related to a shift operation when a failure simulation is performed on a test pattern after shift pattern conversion according to another embodiment of the present invention. Is.

FIG. 9 is a diagram showing an example in which a random pattern is applied to a primary input pin that is not related to a shift operation as compared with FIG.

FIG. 10 is a diagram showing a system configuration of a conventional test generation device.

FIG. 11 is a flowchart of a conventional test generation device.

[Explanation of symbols]

1 test generation device, 2 test generation routine, 3 fault simulation routine, 4 shift pattern conversion routine, 5 function library, 6 circuit net information, 7 test pattern database, 8 fault detection information database for each node, 9 final test pattern 10. Test generator considering shift operation, shift pattern converted test pattern database, 12.14.15 AND element, 13 OR element, 16.17 scan FF, 18 Failure simulation for test pattern after shift pattern conversion A test generator for applying a random pattern to the primary input pin regardless of the shift operation when executing
Random pattern insertion routine, 20 is a test pattern database after shift pattern conversion / random pattern insertion.

Claims (4)

[Claims] 1. A test generator in a full-scan design, wherein, at the time of test generation, each time a test is generated, in addition to a fault simulation for the pattern, a fault simulation for the pattern converted into a shift pattern is also executed. Characteristic test generator. 2. The test generation device according to claim 1, wherein a random pattern is applied to a primary input pin that is not related to a shift operation when a failure simulation is performed on the test pattern converted into the shift pattern. . 3. A test generation method in full-scan design, wherein each time a test is generated, a fault simulation for the pattern is executed, the pattern is then converted into a shift pattern, and the converted pattern is generated. A test generation method characterized in that it also executes a failure simulation for. 4. The test generation method according to claim 3, wherein a random pattern is applied to a primary input pin unrelated to a shift operation when a failure simulation is performed on the test pattern converted into the shift pattern. .