JP3548336B2 - Test generation device and test generation method - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to reducing the number of test patterns at the time of test generation in full scan design and improving the efficiency of test generation.
[0002]
[Prior art]
In the test generation apparatus in the conventional full scan design, a failure simulation at the time of the shift operation is not executed, and a new pattern is generated and detected even for a failure that can be detected only by the shift operation.
For this reason, there has been an occurrence of duplication of test generation for generating a fault that can be detected by the shift operation and an increase in the number of test patterns.
[0003]
Hereinafter, a system configuration and a flow of a conventional test generation device will be described with reference to the drawings.
FIG. 10 shows a system configuration of a conventional test generation device.
Reference numeral 1 denotes a test generation device, which includes a test generation routine 2, a failure simulation routine 3, and a shift pattern conversion routine 4.
The test library 1 receives a function library 5 and circuit net information 6. Reference numeral 7 denotes a test pattern database for storing the generated test patterns, and reference numeral 8 denotes a failure detection information database for each node. 9 is a final test pattern.
[0004]
FIG. 11 shows a flowchart of a conventional test generation device.
In step S1, a test pattern capable of detecting a failure of a node in the circuit is generated by a test generation routine 2.
In the test generation performed in step S1, all scan registers in the circuit are considered as virtual primary input / output pins that can be accessed from outside.
[0005]
The test pattern generated in step S1 is once stored in the test pattern database 7, and is further input to the failure simulation routine 3.
In step S2, a node having a fault that can be detected by the test pattern is recognized and stored in the fault detection information database 8 for each node.
[0006]
In step S3, it is determined whether or not there is a node where no failure has been detected by comparing all detectable failures in the circuit with the failure detection information database 8 for each node.
In the case of Y in step S3, S1 to S3 are repeated for nodes for which no failure has been detected.
In the case of N in step S3, the test patterns accumulated as the test pattern database 7 in S4 are collected.
[0007]
Since the combined test pattern considers all scan registers in the circuit as virtual primary inputs / outputs, the test pattern is set in S5 to enable shift-in from the scan-in pin or shift-out from the scan-out pin of the actual circuit. The shift pattern is converted using the conversion routine 4.
The test pattern after the shift pattern conversion becomes the final test pattern 9.
[0008]
[Problems to be solved by the invention]
A first aspect of the present invention is to provide a test generation device capable of improving the efficiency of test generation and reducing the number of test patterns by performing a failure simulation even during a shift operation.
[0009]
According to a second aspect of the present invention, there is provided a test generation apparatus which applies a random pattern to a primary input pin irrelevant to a shift operation and performs a failure simulation, thereby improving test generation efficiency and reducing the number of test patterns. It is what we are trying to get.
[0010]
A third aspect of the present invention is to provide a test generation method capable of improving the efficiency of test generation and reducing the number of test patterns by performing a failure simulation even during a shift operation.
[0011]
According to a fourth aspect of the present invention, there is provided a test generation method capable of improving the efficiency of test generation and reducing the number of test patterns by performing a fault simulation after applying a random pattern to a primary input pin irrelevant to a shift operation. It is what we are trying to get.
[0012]
[Means for Solving the Problems]
In the test generation apparatus according to the first invention, in the test generation apparatus for full scan design, each time a test is generated at the time of test generation, in addition to the failure simulation for the pattern, the failure simulation for a pattern converted into a shift pattern is performed. Also perform
[0013]
In the test generation device of the second invention, when performing the failure simulation on the test pattern converted into the shift pattern, a random pattern is applied to the primary input pins irrelevant to the shift operation.
[0014]
According to a third invention test generation method, in the test generation method for full scan design, at the time of test generation, each time a test is generated, a fault simulation for the pattern is executed, and then the pattern is converted into a shift pattern, A fault simulation is also performed on the converted pattern.
[0015]
In the test generation method according to the fourth invention, when performing the failure simulation on the test pattern converted into the shift pattern, a random pattern is applied to the primary input pins irrespective of the shift operation.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiment 1 FIG.
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 shows a system configuration of a test generation device in consideration of a shift operation.
Reference numeral 10 denotes a test generation device that considers a shift operation.
The test generation device 10 includes a test generation routine 2, a failure simulation routine 3, and a shift pattern conversion routine 4.
[0017]
The function generator 5 and the circuit net information 6 are input to the test generator 10.
Reference numeral 7 denotes a test pattern database for storing the generated test patterns, and reference numeral 8 denotes a failure detection information database for each node. 9 is a final test pattern.
Reference numeral 11 denotes a test pattern database converted into a shift pattern.
[0018]
FIG. 2 shows a flowchart of the test generation device in consideration of the shift operation.
The test pattern generated in step S1 is used for failure simulation in step S2. This result is stored in the failure detection information database 8 of each node.
[0019]
In step S5, the result of shift pattern conversion of this test pattern is stored in the test pattern database 11 in which the shift pattern has been converted, and further used in step S6 for failure simulation.
This result is also stored in the failure detection information database 8 of each node.
[0020]
In step S3, by comparing all detectable faults in the circuit with each node fault detection information database 8, it is determined whether there is a node where no fault has been detected.
In the case of Y in step S3, S1, S2, S5, S6, and S3 are repeated for nodes for which no failure has been detected.
In the case of N in step S3, the test patterns accumulated as the test pattern database 11 converted in step S7 are converted into a final test pattern 9.
[0021]
In the embodiment of the present invention, faults that can be detected when the same pattern is used increase by adding a fault simulation to the test pattern that has been subjected to the shift pattern conversion.
[0022]
Hereinafter, description will be made with reference to FIG.
FIG. 3 shows an example of a circuit designed for full scan.
12, 14, 15 are AND elements, 13 is an OR element, and 16 and 17 are scan FFs.
3 can be divided into four combination blocks as shown in FIG. 4, since 16 and 17 can be regarded as virtual primary input / output pins.
Hereinafter, for the sake of simplicity, attention will be paid only to the output signal of each block.
[0023]
It is assumed that a test pattern for detecting a 0 fault with respect to the output pins of the elements 12 to 15 is generated in the test generation routine 2.
FIG. 5 shows an example of this test pattern.
[0024]
When this test pattern is converted into a shift pattern, as shown in FIG. 6, the input to the virtual primary pins EF is serially input from the scan pins of the actual circuit using the shift operation.
[0025]
At the time of the first shift operation, 0 is assigned to the scan FF 16. In this case, when a failure simulation is performed, one failure with respect to the AND element 15 can be detected.
[0026]
As described above, when the failure simulation is performed using the test pattern that has undergone the shift pattern conversion, a failure that has not been detected at present can be detected using the same test pattern. That is, the number of repetitions of steps S1 to S3 in the conventional flowchart can be reduced, and the efficiency of test generation is improved.
Further, the number of test patterns can be reduced as compared with the conventional test generation.
[0027]
Embodiment 2 FIG.
FIG. 7 shows a system configuration of a test generation device that applies a random pattern to a primary input pin irrespective of a shift operation when performing a failure simulation on a test pattern after a shift pattern conversion.
[0028]
Reference numeral 18 denotes a test generation device that applies a random pattern to a primary input pin irrespective of a shift operation when performing a failure simulation on a test pattern after the shift pattern conversion.
Reference numeral 19 denotes a random pattern insertion routine, and reference numeral 20 denotes a test pattern database after the shift pattern conversion / random pattern insertion.
[0029]
FIG. 8 is a flowchart of a test generation apparatus that applies a random pattern to a primary input pin irrespective of a shift operation when performing a failure simulation on a test pattern after the shift pattern conversion.
[0030]
Steps S1 to S5 are the same as in the first embodiment.
In step S8, a random pattern is inserted into the primary input pins irrelevant to the shift operation using the random pattern insertion routine 19 with respect to the test pattern after the shift pattern conversion.
[0031]
This result is stored in the test pattern database 20 after the shift pattern conversion / random pattern insertion, and is input as a failure simulation in S9. This result is stored in the failure detection information database 8 of each node.
[0032]
In step S3, as in the first embodiment, it is determined whether or not there is a node for which no failure has been detected.
In the case of Y in step S3, steps S1, S2, S5, S8, S9, and S3 are repeated for nodes for which no failure has been detected.
In the case of N in step S3, the test patterns accumulated as the test pattern database 20 after the shift pattern conversion / random pattern insertion in step S7 are combined into a final test pattern 9.
[0033]
In the embodiment of the present invention, a test pattern can be generated more efficiently than in the first embodiment by applying a random pattern to the primary input pins irrespective of the shift operation.
As shown in FIG. 9 with respect to the first shift operation of FIG. 6 described in the first embodiment, when 0 is applied as a random pattern to the primary input pin A irrelevant to the shift operation, the OR element 13 Can be detected.
[0034]
As described above, by applying a random pattern to the primary input pin irrelevant to the shift operation, it is possible to detect a fault that was not detected in the first embodiment using the same test pattern, thereby improving the efficiency of test generation. Thus, the number of test patterns can be reduced.
[0035]
As described above, according to the embodiment of the present invention, the failure simulation is performed even during the shift operation, or the failure simulation is performed after applying a random pattern to the primary input pin irrelevant to the shift operation. This improves the efficiency of the test and reduces the number of test patterns.
[0036]
【The invention's effect】
According to the first aspect of the present invention, it is possible to obtain a test generation device capable of improving the efficiency of test generation and reducing the number of test patterns by performing a failure simulation even during a shift operation.
[0037]
According to the second aspect of the present invention, a failure simulation is performed after applying a random pattern to a primary input pin irrelevant to a shift operation, thereby improving test generation efficiency and reducing the number of test patterns. A device can be obtained.
[0038]
According to the third aspect of the present invention, it is possible to obtain a test generation method capable of improving the efficiency of test generation and reducing the number of test patterns by performing the failure simulation even during the shift operation.
[0039]
According to the fourth aspect of the present invention, a failure simulation is performed after applying a random pattern to the primary input pin irrelevant to the shift operation, thereby improving the efficiency of test generation and reducing the number of test patterns. You can get the way.
[Brief description of the drawings]
FIG. 1 is a diagram showing a system configuration of a test generation device in consideration of a shift operation according to an embodiment of the present invention.
FIG. 2 is a flowchart of a test generation device in consideration of a shift operation according to an embodiment of the present invention.
FIG. 3 is a diagram showing an example of a circuit designed for full scan according to an embodiment of the present invention;
FIG. 4 is a diagram showing an example in which FIG. 3 is divided by virtual primary input / output pins.
FIG. 5 is a diagram showing an example of a test pattern for FIG. 4;
FIG. 6 is a diagram showing an example in which FIG. 5 is subjected to shift pattern conversion.
FIG. 7 shows a system configuration of a test generation apparatus according to another embodiment of the present invention, which applies a random pattern to a primary input pin irrespective of a shift operation when performing a failure simulation on a test pattern after a shift pattern conversion. FIG.
FIG. 8 is a flowchart of a test generation apparatus according to another embodiment of the present invention, which applies a random pattern to a primary input pin irrespective of a shift operation when performing a failure simulation on a test pattern after a shift pattern conversion. It is.
9 is a diagram illustrating an example in which a random pattern is applied to a primary input pin irrespective of a shift operation with respect to FIG. 6;
FIG. 10 is a diagram showing a system configuration of a conventional test generation device.
FIG. 11 is a flowchart of a conventional test generation device.
[Explanation of symbols]
1 test generation device, 2 test generation routine, 3 fault simulation routine, 4 shift pattern conversion routine, 5 function library, 6 circuit net information, 7 test pattern database, 8 fault detection information database for each node, 9 final test pattern 10. Test generation apparatus in consideration of shift operation, shift pattern converted test pattern database, 12.14.15 AND element, 13 OR element, 16.17 scan FF, 18 fault simulation for test pattern after shift pattern conversion , A test generator for applying a random pattern to a primary input pin irrespective of a shift operation, 19 a random pattern insertion routine, and 20 a test after a shift pattern conversion / random pattern insertion. Pattern database.

Claims (4)

In a test generation apparatus for full scan design, each time a test is generated at the time of test generation, in addition to a failure simulation for the pattern, a test simulation for a pattern obtained by converting the pattern into a shift pattern is also performed. apparatus. 2. The test generation apparatus according to claim 1, wherein when performing the failure simulation on the test pattern converted into the shift pattern, a random pattern is applied to a primary input pin irrelevant to the shift operation. In the test generation method in full scan design, at the time of test generation, each time a test is generated, a failure simulation is performed on the pattern, and then the pattern is converted into a shift pattern, and a failure simulation is also performed on the converted pattern A test generation method. 4. The test generation method according to claim 3, wherein when performing the failure simulation on the test pattern converted into the shift pattern, a random pattern is applied to a primary input pin irrelevant to the shift operation.

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