JPH09307435A - Drift alarm generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a drift alarm generation circuit which outputs no alarm against the phase drift that is caused by an instantaneous fault. SOLUTION: A PLO(phase-locked oscillator) 2 controls the oscillation frequency of a generated clock J so as to secure the phase synchronization with an external input clock I. A phase comparator circuit 14 monitors the phase difference between a divided clock K of the clock J and the clock I and outputs a phase sift signal A when the phase difference exceeds the prescribed value. A drift detection signal generation circuit 15 starts the output of a drift detection signal B when the output of the signal A is started. Then the circuit 15 continuously outputs the signals B until the end of a drift period when the signals A are periodically and continuously outputted. A mask signal generation circuit 16 starts the output of a mask signal D in response to the start of the output of the signal B. Then the circuit 16 continuously outputs the signals D until the time equal to the phase pull-in time of the PLO 2 elapses. A drift alarm output circuit 18 outputs a drift alarm signal E in a period when a delayed signal C (having its output start coincident with the signal D) of the signal B is outputted with no output of the signal D.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is provided for a phase-locked oscillator circuit for phase-locking an internally generated clock with a reference clock input from the outside, and detects a phase drift between the external clock and the generated clock. The present invention relates to a drift alarm generation circuit for issuing an alarm.

[0002]

2. Description of the Related Art Conventionally, such a drift alarm generating circuit has an external clock and a phase-locked oscillation circuit (PLO: Phase).
The phase difference between the clocks generated by the Locked Oscillator) is monitored, and when the phase difference exceeds a predetermined value, a drift alarm is output as a failure of the external clock or PLO.

Usually, in a transmission system or the like, a PLO
And a drift alarm generating circuit are provided in a plural number to form a redundant configuration with respect to the generated clock of the PLO. One of the plurality of PLOs is selected and the generated clock of the PLO is supplied to each device. . When the drift alarm generation circuit corresponding to the selected PLO outputs a drift alarm, the supply clock is switched to the generated clock of another PLO.

[0004]

SUMMARY OF THE INVENTION The conventional drift alarm generating circuit described above has a structure in which a momentary failure such as a phase jump (a failure in which the phase is instantaneously discontinuous) occurs in the external clock or an instantaneous failure in the PLO. Even if such a failure occurs, the phase difference between the external clock and the clock generated by the PLO becomes a predetermined value or more, so a drift alarm is output, which causes the transmission system to change the supply clock to the clock generated by another PLO. Since it is switched to, there is a momentary interruption in the supply clock. However, in such a case, since the generated clock is again phase-synchronized with the external clock within the phase pull-in time of the PLO, outputting the drift alarm causes an extra interruption in the supply clock.

As described above, the conventional drift alarm generating circuit has a problem in that a momentary failure of the external clock or the PLO is mistakenly recognized as a continuous failure and a drift warning is output.

Here, the phase pull-in time is the upper limit value of the time taken from the occurrence of the phase drift to the phase synchronization in the PLO.

The present invention solves such a conventional problem, and an object thereof is to provide a drift alarm generating circuit which does not output a drift alarm for a phase drift due to an instantaneous obstacle such as phase jump. .

[0008]

In order to achieve the above object, the drift alarm generating circuit of the present invention is provided for a phase-locked oscillator circuit for phase-locking a clock internally generated with a reference clock inputted from the outside. In the drift warning generating circuit, the phase difference between the external clock and the generated clock is monitored, and when a phase shift occurs where the phase difference becomes a predetermined value or more, the output of the drift detection signal is started, and the phase Drift detection means for continuously outputting the drift detection signal until the end of the phase drift period in which the deviation continues to occur periodically or continuously, and starts the output of the mask signal in synchronization with the start of the output of the drift detection signal, A mask signal generation circuit that continuously outputs the mask signal until a time equal to the phase pull-in time of the phase-locked oscillation circuit has elapsed. , It is characterized in that it has a drift alarm output circuit for outputting a drift warning period in which the drift detection signal has been output, and not the mask signal is output.

According to another aspect of the drift alarm generating circuit of the present invention, the drift detecting means monitors the phase difference between the external clock and the generated clock, and the phase shift occurs when the phase shift occurs. When a phase comparison circuit that outputs a signal and the output of the phase shift signal are started, the output of the drift detection signal is started, and the output of the drift detection signal is continued until a predetermined time elapses, and the predetermined time elapses. If the output of the phase shift signal is started again before
A drift detection signal generation circuit that continuously extends the output of the drift detection signal until the predetermined time elapses from this point of time, and sets the predetermined time to a time equal to or longer than the time interval of occurrence of the phase shift periodically generated in the drift period. It is characterized by having.

According to another aspect of the drift alarm generating circuit of the present invention, the mask signal generating circuit starts outputting a mask signal in synchronization with the start of output of the drift detection signal, and a time equal to the phase pull-in time has elapsed. If the output of the drift detection signal is started again before the time equal to the phase pull-in time elapses, the mask signal is output until the time equal to the phase pull-in time elapses. The feature is that the signal output is continuously extended.

Therefore, according to the present invention, the drift detection means outputs the drift detection signal corresponding to the phase drift period, and from the start of the output of the drift detection signal until the phase pull-in time of the phase locked oscillator circuit elapses.
The mask signal generation circuit outputs the mask signal, and the drift warning output circuit outputs the drift warning signal while the drift detection signal is being output and the mask signal is not being output. It is possible not to output the drift alarm for the phase drift due to the instantaneous disturbance of

[0012]

1 is a circuit block diagram showing an embodiment of a drift alarm generating circuit of the present invention. The drift warning generation circuit 1 shown in FIG.
LO: Phase Locked Oscillator 2).

The PLO 2 is an oscillating circuit for generating a clock phase-synchronized with an external input clock, and has a voltage controlled oscillator (VCO) 21, a frequency divider 22, a phase comparator 23 and an integrating circuit 24. Then
These are feedback loops (PLL: Phase Locked)
Loop) is formed. The clock generated by the PLO 2 is supplied to each device (not shown) as a reference clock. The frequency of the generated clock is 2 ⁿ times the external input clock frequency (n is 0 or a positive integer).

The VCO 21 oscillates at a frequency based on the input frequency control voltage (DC voltage) M to generate a clock, and changes the oscillation frequency according to the change in the frequency control voltage M. Here, the oscillation frequency is increased as the frequency control voltage M increases.

The frequency divider 22 frequency-divides the generated clock J of the VCO 21 by 2 ⁿ and outputs a frequency-divided clock K having the same frequency level as the external input clock I. For example, when the frequency of the generated clock J is four times the frequency of the external input clock I, the generated clock J is divided by four.

The phase comparator 23 outputs a frequency control pulse L according to the phase difference between the external input clock I and the frequency-divided clock K from the frequency divider 22. For example, the frequency control pulse L whose pulse width changes in proportion to the phase difference is output.
External input clock rising (or falling)
On the other hand, when the rising edge (or falling edge) of the divided clock is in a delayed phase, a positive frequency control pulse having a pulse width corresponding to the phase difference is output, and when it is in an advanced phase, the A negative frequency control pulse having a pulse width corresponding to the phase difference is output, and the pulse is not output when the rising edges (or falling edges) of both clocks have the same phase (when synchronized).

The integrating circuit 24 time-integrates the frequency control pulse L from the phase comparator 23 to generate an external input clock I.
And a frequency control voltage M of direct current, which is proportional to the time integration value of the phase difference between the generated clock J and the divided clock K, is generated and output to the VCO 21. Here, the frequency control voltage M depends on the integral value of the phase difference during the period in which the rising edge (or the falling edge) of the divided clock is a delayed phase with respect to the rising edge (or the falling edge) of the external input clock. The period in which the phase increases and, conversely, the phase is advanced, decreases in accordance with the integrated value of the phase difference, and the period in which both clocks are synchronized has a constant value.

Here, the external input clock I and the VCO 21
The phase synchronization with the generated clock J (hereinafter, simply referred to as phase lock) is lost due to the occurrence of an instantaneous failure such as a phase jump of the external input clock or the continuous failure of the external input clock or PLO2. However, if a phase drift occurs due to a momentary disturbance such as a phase jump of the external input clock I, the PLO 2 locks the phase within the phase pull-in time. Restore.

Next, the drift alarm generation circuit 1 includes a phase comparison circuit 14, a drift detection signal generation circuit 15, and a delay circuit 1.
6, a mask signal generation circuit 17, and a drift warning output circuit 1
8 is provided.

The phase comparison circuit 14 uses the external input clock I
And the divided clock K input from the frequency divider 22 of PLO2
And the phase difference between them is monitored, and a phase shift signal is output when this phase difference is equal to or greater than a predetermined value. Here, when the phase difference between the rising edge (or the falling edge) of the external input clock J and the divided clock K is equal to or greater than the predetermined threshold value θ, the phase that becomes the Low level (hereinafter, referred to as “L”) The shift signal A is output. Note that the phase shift signal A is periodically output during the phase drift period due to an instantaneous obstacle.

When the output of the phase shift signal A is started, the drift detection signal generating circuit 15 starts outputting the drift detection signal B, and the phase shift signal A continues to be output periodically or continuously during the drift period. The drift detection signal B is continuously output until the end. This drift detection signal B is a signal that is at a high level (hereinafter referred to as “H”) in correspondence with the drift period. Further, for example, when the phase shift signal A becomes active ('L'), the drift detection signal generating circuit 15 sets a timer to change the output from'L 'to'H', and sets the timer set time T.
After 1 lapse of time, the output is returned to'L ', and if the phase shift signal A becomes active (' L ') again before the time is up, the output is held at'H' at this point and the timer is set again. It can be realized by using a timer circuit. The timer setting time T1 is set to a value that is equal to or longer than a generation time interval of the phase shift that periodically occurs in the phase drift period, that is, a value that is equal to or longer than the output time interval of the phase shift signal A that is periodically output, and It is preferable to approximate this output time interval.

Here, the drift detection signal generation circuit 15
As monostable multivibrator 15a (74 series monostable multivibrator IC "74HC123")
Is used. The monostable multivibrator 15a has a trigger input terminal IN, a trigger inversion input terminal nIN, passive element connection terminals CG and CR, and an output terminal Q, the CG terminal is grounded, and a phase shift signal A (active level = 'L') is input and the Q output is used as the drift detection signal B (active level = 'H'). When the phase shift signal changes from'H 'to'L', a timer is set and the Q output is output. The signal is changed from "L" to "H", and the capacitor C1 and CR terminal connected between the CG and CR terminals and the power supply VD
After the timer setting time T1 determined by the resistor R1 connected between D has elapsed, the time is up and the output signal of Q is'L '.
Return to When the phase shift signal becomes active again before the time is up, the output of Q is held at "H" at this point and the timer is set again to perform the above timer operation. The monostable multivibrator 16a changes the drift detection signal B to "H" after the phase shift signal is input and before the output of the drift signal B is started, that is, after the phase shift signal A becomes "L". Requires a delay time (timer set time).

The mask signal generation circuit 16 starts the output of the mask signal D in response to the start of the output of the drift detection signal B, and continuously outputs the mask signal D until the time equal to the phase pull-in time of PLO2 has elapsed. This mask signal D
Is a signal that changes from “L” to “H” in response to the start of output of the drift detection signal B, and is “H” for a period equal to the phase pull-in time. Further, the drift detection signal generation circuit 15 sets a timer to change the output from “L” to “H” when the drift detection signal B becomes active (“H”), and after the timer set time T2 elapses, the time is set. Up to return the output to'L ', and if the drift detection signal becomes active again before the time is up,
This can be realized by using a timer circuit that resets the timer while keeping the output at "H" at this point. The timer setting time T2 (> T1) is set to a value equal to the phase pull-in time of PLO2.

Here, as the mask signal generation circuit 16, the same monostable multivibrator 16a as the drift detection signal generation circuit 15 (the same IC "74HC123" as the monostable multivibrator 15a) is used. In the monostable multivibrator 16a, the CG terminal is grounded, the drift detection signal B (active level = 'H') is input to the trigger input terminal IN, and the output of the output terminal Q is masked by a mask signal D (active level = 'H'). ), When the drift detection signal B becomes active ('H'), a timer is set and the output of Q is changed from'L 'to'H'.
After the elapse of the timer time T2 determined by the capacitor C2 connected between the CR terminals and the resistor R2 connected between the CR terminal and the power supply VDD, the time is up and the output of Q is returned to'L '. In addition, before the time is up again, the drift detection signal B
Becomes active, the timer is set again at this point while the output of Q is kept at "H". The monostable multivibrator 16a operates in the following manner from when the drift detection signal is input to when the output of the mask signal is started, that is, after the drift detection signal B becomes "H".
Delay time (timer set time) T
d is required.

The delay circuit 17 is for compensating for the delay of the mask signal D with respect to the drift detection signal B.
The drift detection signal B from the drift detection signal generation circuit 15 is delayed by the above timer set time Td and the delayed drift detection signal C is output. This delay circuit 17 is, for example, a D flip-flop (74 series IC “74HC
175 ").

The drift warning output circuit 18 outputs the drift warning signal E while the drift detection signal B is being output and the mask signal D is not being output. This drift warning signal E is the drift detection signal B here.
Is output (is “H”), and the mask signal D
When is not output (when it is'L '),
It is a signal that becomes "H". This drift warning output circuit 1
Reference numeral 8 is a 2-input NOR gate 18a having an input terminal and an inverting input terminal here. The delay drift detection signal C from the delay circuit 17 is input to the input terminal of the NOR gate 18a, and the mask signal D is input to the inverting output terminal. A 2-input N having an inverting input terminal and an input terminal
It can be easily realized by using an AND gate or the like.

The drift detection signal generating circuit 15 described above is used.
The mask signal generation circuit 16 is not limited to a timer circuit such as a monostable multivibrator, and can be realized by using a counter circuit, for example.

Next, the operation of PLO2 will be described.
The generated clock J of the VCO 21 is supplied to each device as a reference clock and is also input to the frequency divider 22. The frequency divider 22 frequency-divides the generated clock J and outputs a frequency-divided clock K having the same frequency as the external input clock I. The divided clock K is input to the phase comparator 23 and the phase comparison circuit 14 of the drift alarm generation circuit 1.
The phase comparator 23 uses an external input clock I and a divided clock K.
Of the phase difference between the integrator circuit 24 and the frequency control pulse L corresponding to the phase difference.
Is input to The integrating circuit 24 time-integrates the frequency control pulse L to generate a frequency control voltage M proportional to the time integration value of the phase difference between the external input clock I and the divided clock K, and inputs this to the VCO 21. As a result, the frequency of the generated clock J of the VCO 21 is controlled to be 2 ⁿ , which is the frequency of the external input clock I, and the generated clock J is synchronized with the external input clock I.

Next, the operation of the drift alarm generating circuit 1 will be described. FIG. 2 is an operation timing chart of the drift warning generation circuit 1. In FIG. 2, the timer set time of the monostable multivibrator 15a is set to 0 for the sake of simplicity.

In FIG. 2, PL1, PL2 and PL3 are due to a phase lock period by PLO2, PD1 to PD3 are due to a phase drift period due to an instantaneous fault such as a phase jump of an external input clock, and period PD4 is due to continuous fault occurrence. The phase drift period is shown.

First, the operation in the period P1 (phase lock period PL1) will be described. At this time, since the phase difference between the external input clock I and the divided clock K is controlled by the PLO 2 to be a value smaller than the threshold value θ, the phase comparison circuit 14 does not output the phase shift signal A (phase shift). Signal A
Is always'H '). Therefore, the drift detection signal generation circuit 15
Does not output the drift detection signal B (drift detection signal B
Is always “L”), and the drift warning output circuit 18 does not output the drift warning signal E (the drift warning signal E is always “L”). The operations in the phase lock period PL2 of the period P2 and the phase lock periods PL2 and PL3 of the period P3 are the same as above.

Next, the operation in the period P2 will be described. When a phase jump occurs in the external input clock at time t1, the phase difference between the external input clock I and the divided clock K in the phase comparison circuit 14 periodically becomes equal to or greater than the threshold value θ at times t1, t2, and t3. The shift signal A is at times t1 and t
At 2 and t3, it changes from'H 'to'L'.

When the phase shift signal A changes from "H" to "L" at time t1, the drift detection signal generation circuit 15 is set by the timer and the drift detection signal B changes from "L" to "H". Since the phase shift signal A changes from “H” to “L” at the times t2 and t3, and the interval between the times t1, t2, and t3 is within the time T1, the drift detection signal generation circuit 15 changes the drift detection signal B to “ While holding at H ',
The timer is set at the times t2 and t3, and the drift detection signal B changes from "L" to "H" after a lapse of time T1 from the time t3. The time during which the drift detection signal B is "H" is shorter than the phase pull-in time (timer time of the mask signal generation circuit 16) T2.

When the drift detection signal B changes from "L" to "H" at time t1, the mask signal generation circuit 16 is set by the timer, and after the timer setting time Td has elapsed from the time t1, the mask signal D changes from "L" to "H". Become H '. The mask signal D becomes “L” after the phase pull-in time T2 has elapsed from the time t1 + Td.

The drift detection signal B output from the drift detection signal generation circuit 15 is delayed by the delay circuit 17 for the timer set time Td of the mask signal generation circuit 16, and the drift detection signal C as the drift detection signal C is output. The mask signal D is input to the inverting input terminal of the counter 18, and the mask signal D is input to the input terminal of the drift warning output circuit 18. However, in the period from time t1 + Td to t3 + T1 + Td when the delay drift detection signal C is “H”, the mask signal D is “H”, so the delay drift detection signal C is masked by the mask signal D and the drift warning signal E is No output (remains'L ').

Next, the operation in the period P3 will be described. At time t4, a phase jump occurs in the external input clock, and the phase difference between the external input clock I and the divided clock K is the threshold value θ.
As described above, when the phase shift signal A changes from “H” to “L”, the drift detection signal generation circuit 15 is set by the timer, the drift detection signal B changes from “L” to H, and the time T
It returns to'L 'after 1 lapse. When a phase jump occurs in the external input clock at time t5, the phase difference between the external input clock I and the divided clock K is the threshold value θ at times t5 and t6.
As described above, the phase shift signal A is'H 'at the times t5 and t6.
Becomes'L '. At time t5, the phase shift signal A becomes'H '.
From "L" to "L", the drift detection signal generation circuit 15 is set by the timer, and the drift detection signal B changes from "L" to "H". The phase shift signal A changes from “H” to “L” at the time t6, and the interval between the times t5 and t6 is within the time T1. Therefore, the drift detection signal B is held at the “H” and drifts at the time t6. The detection signal generation circuit 15 is set by the timer, and the drift detection signal B changes from'L 'to'H' after a lapse of time T1 from time t6. The time from the time t4 to t4 + T1 when the drift detection signal B becomes “H” and the time from the time t5 to t6 + T1 are both shorter than the phase pull-in time T2.

When the drift detection signal B changes from "L" to "H" at time t4, the mask signal generation circuit 16 is set by the timer, and the mask signal D changes from "L" to "H" at time t4 + Td. Further, since the time from time t4 + Td to t5 is shorter than the phase pull-in time T2, when the drift detection signal B changes from'L 'to'H' again at time t5, the mask signal generation circuit 16 changes the mask signal D to'H '. The timer is set while being held, and the mask signal D changes from “H” to “L” after a lapse of time Td + T2 from time t5.

In the drift warning output circuit 18, the mask signal D is "H" during the period from time t4 + Td to t4 + T1 + Td when the delay drift detection signal C is "H" and during the time t5 + Td to t6 + T1 + Td, so the delay drift detection signal is "H". Both Cs are masked by the mask signal D, and the drift warning signal E is not output (it remains'L ').

Finally, the operation in the period P4 will be described.
When a failure occurs in the external input clock or PLO2 at time t7, the phase difference between the external input clock I and the divided clock K in the phase comparison circuit 14 periodically becomes equal to or more than the threshold value θ after time t7, and the phase shift signal is generated. A is periodically output (from'H 'to'L').

When the phase shift signal A changes from "H" to "L" at time t7, the drift detection signal generating circuit 15 is set by the timer and the drift detection signal B changes from "L" to "H". The phase shift signal A periodically changes from “H” to “L” after time t7, and this interval is within the time T1. Therefore, the drift detection signal generation circuit 15 holds the drift detection signal B at “H”. As it is, the timer is set by the phase shift signal A, and the drift detection signal B continuously becomes'H 'from time t7 onward.

When the drift detection signal B changes from "L" to "H" at time t7, the mask signal generation circuit 16 is set by the timer, and after the timer setting time Td has passed from time t7, the mask signal D changes from "L" to "H". Become H '. The mask signal D becomes “L” after the phase pull-in time T2 has elapsed from the time t7 + Td.

The drift detection signal B output from the drift detection signal generation circuit 15 is delayed by the delay circuit 17 for the timer set time Td of the mask signal generation circuit 16, and is input to the inverting input terminal of the drift alarm generation circuit 18. The mask signal D is input to the input terminal of the drift warning output circuit 18.

In the drift alarm output circuit 18, the delayed drift detection signal C is'H 'after the time t7 + Td, but during the period from the time t7 + Td to t7 + T2 + Td, the mask signal D is also'H', so the delayed drift detection signal C is'H '. C is masked by the mask signal D, and the drift warning signal E is not output (it remains'L '). When the mask signal D becomes “L” at time t7 + T2 + Td, the drift warning signal E is output (from “L” to “H”) to notify the occurrence of a failure.

As described above, according to the above embodiment, the phase comparison circuit 14 causes the phase shift signal A when the phase difference between the external input clock I and the divided clock K exceeds a predetermined value.
And the drift detection signal generation circuit 15 outputs the drift detection signal B corresponding to the phase drift period in which the phase shift signal A is continuously or continuously output, and the mask signal generation circuit 16 detects the drift. The mask signal D is output from the start of the output of the signal B until the phase pull-in time of the PLO 2 has elapsed, and the drift alarm output circuit 18 outputs the drift detection signal and the drift alarm during the period when the mask signal is not output. It is possible to prevent the drift alarm from being output in response to a phase drift due to an instantaneous obstacle such as a phase jump of the external clock.

[0045]

As described above, according to the present invention, the drift detection signal output corresponding to the phase drift period elapses from the start of the drift detection signal output for a time equal to the phase pull-in time of the phase-locked oscillator circuit. It is masked by the mask signal that is output up to, and the drift warning is output when there is a period when the drift detection signal is not masked, so that the drift warning can be issued against the phase drift due to an instantaneous failure such as the phase jump of the external clock. Since no output can be performed, it is possible to reduce unnecessary supply clock switching in a transmission system or the like.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing an embodiment of a drift alarm generation circuit of the present invention.

FIG. 2 is an operation timing chart in the drift warning generation circuit according to the embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Drift alarm generation circuit 2 Phase synchronous oscillation circuit (PLO) 14 Phase comparison circuit 15 Drift detection signal generation circuit 16 Mask signal generation circuit 15a, 16a Monostable multivibrator (74HC
123) 17 delay circuit 18 drift warning output circuit 18a 2 input NOR gate 21 voltage controlled oscillator (VCO) 22 frequency divider 23 phase comparator 24 integrating circuit A phase shift signal B drift detection signal C delay drift detection signal D mask signal E Drift alarm signal I External input clock J Generated clock K Divided clock L Frequency control pulse M Frequency control voltage

Claims (3)

[Claims] 1. A drift alarm generating circuit provided for a phase-locked oscillator circuit that synchronizes an internally generated clock with a reference clock input from the outside, and monitors a phase difference between the external clock and the generated clock. When a phase shift in which the phase difference exceeds a predetermined value occurs, the drift detection signal is started to be output, and the drift detection is continued until the end of the phase drift period in which the phase shift continues to occur periodically or continuously. Drift detection means for continuously outputting a signal, starting the output of the mask signal in synchronization with the start of the output of the drift detection signal, until the time equal to the phase pull-in time of the phase-locked oscillation circuit has elapsed, the mask signal A mask signal generation circuit that continuously outputs, the drift detection signal is output, and the mask signal is output. And a drift warning output circuit that outputs a drift warning during a non-driving period. 2. The drift detecting means monitors a phase difference between the external clock and the generated clock, and outputs a phase shift signal when the phase shift occurs, and the phase comparator circuit. When the output of the shift signal is started, the output of the drift detection signal is started, the output of the drift detection signal is continued until a predetermined time elapses, and the output of the phase shift signal is started again before the predetermined time elapses. Then, from this point of time, the drift detection signal is continuously extended until the predetermined time elapses, and the predetermined time is a drift that is equal to or longer than the generation time interval of the phase shift periodically generated in the drift period. The drift alarm generating circuit according to claim 1, further comprising a detection signal generating circuit. 3. The mask signal generation circuit starts the output of the mask signal in synchronization with the output start of the drift detection signal, and continues the output of the mask signal until a time equal to the phase pull-in time has elapsed. When the output of the drift detection signal is started again before the time equal to the phase pull-in time has elapsed, the mask signal output is continuously extended from this point until the time equal to the phase pull-in time has elapsed. The drift alarm generating circuit according to claim 1.