JPH09306965A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit having an evaluation circuit as a monitor for evaluation of formed wiring lines mounted thereon, which can easily estimate a faulty point and analyze its defective mode. SOLUTION: The evaluating monitor is arranged so that, for example, a latch cell 21 including write and read circuits to and from a latch circuit 27 as a part of a wiring pattern 28 is provided on a chip to perform writing and reading operations over the latch circuit 27 of the latch cell 21 and to estimate such defective mode and defective point as broken line or shortcircuiting in the wiring pattern 28 to be evaluated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having an evaluation circuit for evaluating a formed wiring evaluation monitor. 2. Description of the Related Art In recent years, as the functionality and integration of semiconductor devices have increased, the density of patterns and elements formed on mounted chips has increased. Since the width, pitch, etc. of the wiring pattern will be different if the manufacturing process is different, it is necessary to form a monitor of patterns and elements on the chip to evaluate the process start-up. There is a demand for easier location estimation and failure mode analysis. For that purpose, an evaluation circuit for estimating a defective portion and analyzing a defective mode only by giving a predetermined signal is required.

[0002]

2. Description of the Related Art Conventionally, as an evaluation method of a wiring monitor,
It is general that a wiring evaluation monitor is placed on a chip in several modes and individually inspected, and each monitor is evaluated individually.

FIG. 6 shows an explanatory view of a conventional wiring evaluation monitor. 6 (A) is parallel to the pattern 11 as a wiring evaluation monitor on a chip (11 ₁₎ a predetermined thickness, it is formed by a predetermined number alone according to the monitoring mode at a predetermined pitch. The pads 12 are provided on both ends of each pattern 11.
a ₁ ~, 12b~ is formed. When these patterns 11 are formed in multiple layers on a chip, they are conducted by vias and corresponding pads are formed on the surface.

Further, FIG. 6B shows a multilayer structure on a chip.
And a chain to the pattern 13 (13 ₁ ~) is formed in a predetermined sequence, the pad 14 ₁ milestone portion of each chain in each column
Is formed. Then, according to the evaluation mode such as short circuit or disconnection of each pattern 11, 13, the corresponding pad (12a
_1, 12b _1, and performs evaluation checks by contacting a probe individually to 14 ₁ ~).

Further, although not shown, in evaluation of a bulk system such as an element formed on a chip as an evaluation monitor, pads are formed at the input end and the output end of each element or a circuit formed by the element. Then, by inputting a signal to the corresponding pad and inspecting the output state from the corresponding pad, it is evaluated whether or not the normal operation is performed.

[0006]

However, as described above, arranging a wiring pattern or bulk system evaluation monitor as a single unit on a chip for evaluation is formed on the chip for each evaluation monitor. In consideration of layer conditions (upper layer, lower layer, etc.) and arrangement conditions, all pads must be inspected by the probe according to the evaluation mode. Furthermore, when there are multiple evaluation items, the evaluation corresponding to each evaluation item is performed. There is a problem that it is necessary to perform the inspection and evaluation in the mode, and it takes a lot of time before the evaluation analysis and evaluation judgment.

Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor integrated circuit that facilitates defect location estimation and failure mode analysis.

[0008]

In order to solve the above-mentioned problems, according to a first aspect of the present invention, in a semiconductor integrated circuit equipped with an evaluation monitor for setting process conditions in semiconductor manufacturing, the evaluation monitor is A semiconductor integrated circuit is configured by forming a memory unit that outputs the state of the evaluation monitor according to the determination signal.

According to a second aspect of the present invention, the evaluation monitor according to the first aspect is a wiring pattern formed of a predetermined formation layer at a predetermined pitch of a predetermined width. In the third aspect, the evaluation monitor according to the first or second aspect is a circuit element formed on a semiconductor.

According to a fourth aspect of the present invention, in any one of the first to third aspects, the memory means is arranged in an array to form a memory block. In claim 5, claim 4
The evaluation monitor is formed with respect to a predetermined memory means of the described memory block so as to pair the memory means at both ends in the horizontal direction and both ends in the vertical direction.

According to a sixth aspect, the memory blocks according to the fifth aspect are arranged in an array to form an array block,
The evaluation monitor of the same type or different types of evaluation targets is formed for each memory block. In claim 7, claim 6
In the above, the memory blocks in which the same kind of evaluation monitor is formed are uniformly arranged in the array block.

As described above, according to the first to third aspects of the present invention,
On the semiconductor, there is provided a memory means having a part of an evaluation monitor such as a wiring pattern having a predetermined width and pitch, a circuit element, etc., and a judgment signal is supplied to the memory means to change the state of the evaluation monitor. Output it for judgment and evaluation. As a result, it is not necessary to perform monitor evaluation by itself in accordance with a plurality of evaluation items, and it becomes possible to easily perform defect location estimation and defect mode analysis in the memory state of the memory means.

In the invention of claim 4 or 6, the memory means is arranged in an array to form a memory block, and the memory blocks are appropriately arranged in an array to form an array block. This facilitates defect location estimation and failure mode analysis for multiple types of evaluation items,
It is possible to calculate the defect rate and the defect rate for each block, and it is possible to facilitate determination and evaluation.

According to a fifth aspect of the invention, the evaluation monitors are formed so that the memory means are paired at both ends in the horizontal direction and the vertical direction in the memory block. As a result, the pair of memory means have the same result depending on the evaluation mode of the evaluation monitor, and it is possible to easily determine and evaluate the defect type in the evaluation mode.

According to the invention of claim 7, in the array block in which the memory blocks are arranged in an array, the memory blocks in which the same kind of evaluation monitors are formed are uniformly arranged. This makes it possible to easily determine and evaluate the position-dependent defect.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a schematic view of the essential parts of an embodiment of the present invention. FIG. 1 shows a circuit diagram of an example of a latch cell 21 as a memory means, in which a write enable row address line (WER) 22 and a read enable line (RE) 23 are arranged in the horizontal direction and a write enable in the vertical direction. Column address line (WEC) 2
4, a drive line (DLV) 25 and a data output line (D _out ) 26 are arranged.

The NAND circuit NAND1 has two input terminals.
Are connected to WER22 and WEC24 respectively, and output
The end is connected to the inverter circuit INV1. Meanwhile, the first
Power supply V_DD2 P channel F between the second power supply GND and the
ET (Field Effect transist
or) transistor T₁, T_TwoSeries circuit and two
N-channel FET transistor T_Three, T_FourSeries times
And the path are connected in series. Transistor T₁, T_FourNo
Is connected to DLV25, and transistor T_TwoGame
Is connected to the output terminal of the NAND circuit NAND1. Ma
Transistor T _ThreeThe gate of the inverter circuit INV
1 is connected to the output terminal. The NAND circuit NAND1,
Inverter circuit INV1 and transistor T₁~ T_FourBut
It serves as a write circuit for a latch circuit described later.

A latch circuit 27 is composed of two bidirectionally connected inverter circuits INV2 and INV3, and the connection point between the output terminal of the inverter circuit INV2 (the output terminal of the inverter circuit INV1) and the transistors T ₂ and T ₃ . A wiring pattern 28, which is an evaluation monitor, is connected to and. Then, the inverter circuit INV3 of the latch circuit 27
Is connected to one input end of the NOR circuit NOR1 and is connected to one input end of the NAND circuit NAND2.

On the other hand, the inverter circuit INV4 has an input end connected to the RE 23 and an output end connected to the inverter circuit INV4.
5 and the other input terminal of the NOR circuit NOR1. In addition, the inverter circuit INV
The output terminal of 5 is connected to the other input terminal of the NAND circuit NAND2.

The first power source V _DD and the second power source GND
A P-channel FET transistor T ₅ and an N-channel FET transistor T ₆ are connected in series between
The connection point of the transistors T ₅ and T ₆ is connected to D _out 26. The gate of the transistor T ₅ is connected to the output terminal of the NAND circuit NAND2, in which the gate of the transistor T ₆ is connected to the output terminal of the NOR circuit NOR1.

The inverter circuits INV4, INV5,
The NAND circuit NAND2, the NOR circuit NOR1, and the transistors T ₅ and T ₆ serve as a read circuit for the latch circuit 27. Although the wiring pattern 28 serves as an evaluation monitor as described above, all the circuit elements such as the NAND circuit NAND1 forming the memory circuit 21 serve as an evaluation monitor.

The operation of the latch cell 21 will be briefly described. Here, it is assumed that the wiring pattern 28 and each circuit element are not defective. When writing to the latch circuit 27, the transistors T _2, T ₃ in the ON state output becomes "0" when the signal is supplied NAND circuit NAND1 of "1" to the WER22 and WEC24, in this case DLV25 "1" signal is supplied transistor T ₄ is a turned on state to the latch circuit 27
The information "0" of the second power supply GND is latched at. Further, when the signal "0" is supplied to the DLV25 to the latch circuit 27 the transistor T ₁ is turned on has information "1" of the first power supply V _DD is latched.

On the other hand, when the latch information is read from the latch circuit 27, when the signal "1" is supplied to the RE 23, the signal "1" is input to the other input terminal of the NAND circuit NAND2 and the NOR circuit. A signal of "0" is input to the other input end of NOR1. Therefore, when the latch information of the latch circuit 27 is "1", "1" is input to one of the input terminals of the NAND circuit NAND2 and the NOR circuit NOR1, respectively, and the output of the NAND circuit NAND2 is "0" and the NOR circuit NOR1. Output becomes "0" and the transistor T ₅
Only that is turned on, and a signal of "1" is output to D _out 26.

When the latch information of the latch circuit 27 is "0", the NAND circuit NAND2 and the NOR circuit N are provided.
"0" is input to one input terminal of each OR1, the output of the NAND circuit NAND2 is "1", and the NOR circuit NOR1
It becomes "1" output is one in which a "0" signal to the D _out 26 only the transistor T ₆ is turned on is outputted.

Therefore, the latch cells of FIG. 1 are arranged in FIG.
The top view of the latch block is shown. FIG. 2 corresponds to FIG.
The latch cells 21 are arranged in an array to form a memory block.
Equivalent to the latch block 31 formed as
A typical memory circuit (SRAM) is configured.
On this latch block 31, there is one column in the vertical direction.
Wiring pattern 28 of a constant number (for example, two as one round trip)
a (28a₁, 28a _Two) Is formed a predetermined number, and the horizontal direction
A certain number of lines (for example, two lines for one round trip) per line
Pattern 28b (28b₁, 28b_Two) Is formed a predetermined number
It is. In this case, the wiring patterns 28a and 28b are mutually
In order to prevent short circuit to multiple layers
It is formed with a predetermined pitch of width.

Vias are appropriately formed in the wiring patterns 28a and 28b in accordance with the evaluation mode to form via-covered portions in the vias, and a via-chain wiring pattern is formed between the vias corresponding to the respective layers. May be. Then, among the latch cells 21 forming the latch block 31, each horizontal wiring pattern 28b (28b ₁ , 28b ₂ )
The latch cells 21 at both ends are paired, and the latch cells 21 at both ends of the vertical wiring pattern 28a (28a ₁ , 28a ₂ ) are paired. Note that latch cells other than those described above are evaluated by the monitor for evaluation of circuit elements other than the wiring pattern 28. In this case, without connecting the wiring pattern 28 of FIG. 1, the transistors T _2, T ₃
The connection point of is directly connected to the latch circuit 27,
The wiring pattern of each circuit element is formed on a predetermined formation layer on the wafer.

Therefore, FIG. 3 shows the latch cell of FIG.
Shows the circuit diagram of the main part of the connection between the H circuit and the wiring evaluation monitor.
You. As shown in FIG. 3, the wiring pattern is arranged in the vertical direction.
Latch cell 21 (21_A1Toss
Wiring pattern at the input part of the latch circuit 27
28a₁And the latch cell 21 (21 _A2
In the input part of the latch circuit 27 in
Pattern 28a₁Wiring pattern 2 placed close to
8a_TwoIs connected. This connection state is the vertical wiring pattern.
Turn 28 (28a₁, 28a_Two) In each column.

Further, a wiring pattern wired in the horizontal direction
To the latch cell 21 (21_B1To)
The wiring pattern 28b is provided at the input portion of the latch circuit 27.
₁And the latch cell 21 (21_B2And
In the input part of the latch circuit 27 in
28b₁Wiring pattern 28b arranged close to_TwoBut
Connected. This connection state is horizontal wiring pattern 2
8 (28b₁, 28b _Two) In each line
You.

In the connected state as described above, each latch cell 2
In the case of causing the latch circuit 27 of No. 1 to perform writing, if the connected wiring pattern 28 is, for example, broken, the input of the latch circuit 27 is in a flow state, and this is detected by any of the latch cells 21. It is possible to easily determine which of the wiring patterns 28 to be disconnected is broken.

In addition, the wiring pattern 28 (for example, 2
8a ₁ and 28a ₂ and 28b ₁ and 28b ₂ ) are short-circuited, a pair of latch cells 21 (21 _A1 and 2
1 _A2 , 21 _B1 and 21 _B2 ) are read by the latch circuit 27 and the output results are the same. As a result, it is possible to easily determine whether or not there is a short circuit, and which wiring pattern 28 (28a ₁ , 28a ₂ , 28b ₁ , 28b ₂ )
It is also possible to easily determine whether or not there is a short circuit.

As described above, it is possible to facilitate the estimation of the defective portion of the wiring pattern or the circuit element and the analysis of the defective mode in the evaluation mode. Subsequently, FIG.
2 shows an explanatory view when the latch blocks of FIG. 2 are arranged in an array. The latch block 31 shown in FIG. 4 has the above-mentioned latch cells 21 arranged in an array, and the row address (aa to ah) and the column address (ba to bh) of the latch block 31 are shown in one box in the drawing. It is recognized and selected, and two latch cells 21 are arranged at one address as shown in the figure. This is appropriately arranged as the number of wiring patterns 28 to be formed and the one for manufacturing. In the latch block 31 shown in FIG. 4, the wiring pattern 28 as shown in FIG. 2 is omitted.

The latch blocks 31 are arranged in an array on a chip (semiconductor) 41 and are arranged in the order of AA to AH, BA to.
The array block 42 is formed into, for example, two blocks 42a and 42b like BH. A ring oscillator 43 is provided around the array block 42 on the chip 41.
The control unit 44 and the like are arranged and formed. Then, the ring oscillator 43 and the control unit 44 select the latch block 31 at the addresses AA to AH and BA to BH of the array block 42 to select row addresses (aa to aa).
h) and column addresses (ba to bh) are written with physical input values (“1” or “0”) corresponding to the respective evaluation modes in each latch cell 21 to determine and evaluate the state of the wiring pattern 28 and each circuit element. Is to do.

As a result, it is possible to easily estimate the type of the evaluation monitor and its contents by estimating the defective portion of each evaluation monitor or causing a defect. Next, FIG. 5 shows an explanatory view of the arrangement of the latch blocks in the array block of FIG. FIG. 5A shows a chip 41.
The above shows the arrangement of the latch blocks 31 for each evaluation target when the latch blocks 31 are arranged in an array as shown in FIG. That is, for example, the latch blocks (indicated by block Nos. 1 to 8) 31 corresponding to eight evaluation targets (described in FIG. 5B) are uniformly arranged in each of the blocks 42a and 42b of the array block 42. The case is shown.

Here, the evaluation target is shown as an example in FIG. 5B with the wiring pattern as the evaluation target. In this case, the wiring pattern is assumed to be formed of four layers (LA to LD), the wiring pattern of LA and LD is formed in the vertical (vertical) direction, and the wiring pattern of LB and LC is formed in the horizontal (horizontal) direction. It is formed. Then, as shown in FIG. 5B, the block No. of each latch block 31. The evaluation target is determined according to. Note that the via covering described in FIG. 5B means that there is a via forming portion that exceeds the pattern width when forming a via (that is, the space between patterns becomes narrow at this via covering portion). .

The block No. The NB via chains shown in FIGS. 7 and 8 are between the A layer and the B layer (see FIG. 6B).
(Refer to FIG. 4) is formed and evaluation is performed. Similarly, NC indicates a case where via chains are evaluated between the B layer and the C layer, and ND indicates a case where evaluation is performed between the C layer and the D layer.

As described above, by uniformly arranging the same latch blocks 31 to be evaluated in the array block 41, it is possible to judge a defect due to a positional deviation due to a misalignment at the time of alignment or a warp of a wafer in a semiconductor manufacturing process. ,
It is something that can be evaluated.

[0037]

As described above, according to the first to third aspects of the invention, the memory means is provided on the semiconductor, which is part of a monitor for evaluation of wiring patterns having a predetermined width and pitch, circuit elements and the like. By supplying a determination signal to the memory means and outputting the state of the evaluation monitor for determination and evaluation, it is not necessary to perform monitor evaluation by itself according to a plurality of evaluation items. With the memory state of the means, it is possible to easily perform defect location estimation and defect mode analysis.

According to the fourth or sixth aspect of the invention, the memory means are arranged in an array to form a memory block, and the memory blocks are appropriately arranged in an array to form an array block. For the evaluation items of, the defect location estimation and the failure mode analysis are facilitated,
It is possible to calculate the defect rate and the defect rate for each block, and it is possible to facilitate determination and evaluation.

According to the invention of claim 5, the evaluation monitors are formed such that the memory means are paired at both ends in the horizontal direction and the vertical direction in the memory block. The same result is obtained depending on the evaluation mode of the monitor for use, so that it is possible to easily determine and evaluate the defect type in the evaluation mode.

According to the invention of claim 7, the position dependency can be easily achieved by uniformly arranging the memory blocks in which the same kind of evaluation monitors are formed in the array block in which the memory blocks are arranged in an array. It is possible to judge and evaluate the defects.

[Brief description of drawings]

FIG. 1 is a main part configuration diagram of an embodiment of the present invention.

FIG. 2 is a plan view of a latch block in which the latch cells of FIG. 1 are arranged.

3 is a main part circuit diagram of a connection state of a latch circuit of the latch cell of FIG. 2 and a wiring evaluation monitor.

FIG. 4 is an explanatory diagram when the latch blocks of FIG. 2 are arranged in an array.

5 is an explanatory diagram of a layout of latch blocks in the array block of FIG.

FIG. 6 is an explanatory diagram of a conventional wiring evaluation monitor.

[Explanation of symbols]

21 Latch Cell 22 WER 23 RE 24 WEC 25 DLV 26 D _out 27 Latch Circuit 28 Wiring Pattern 28a Vertical Pattern 28b Horizontal Pattern 31 Latch Block 41 Chip 42 Array Block 43 Ring Oscillator 44 Control Unit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical indication location H01L 21/8242

Claims (7)

[Claims] 1. A semiconductor integrated circuit equipped with an evaluation monitor for setting process conditions in semiconductor manufacturing, comprising the evaluation monitor as a part, and outputting the state of the evaluation monitor in response to a determination signal. A semiconductor integrated circuit, characterized in that a memory means for performing the above is formed. 2. The semiconductor integrated circuit according to claim 1, wherein the evaluation monitor is a wiring pattern formed in a predetermined formation layer with a predetermined width and a predetermined pitch. 3. The evaluation monitor according to claim 1 or 2,
A semiconductor integrated circuit, which is a circuit element formed on a semiconductor. 4. The semiconductor integrated circuit according to claim 1, wherein the memory means are arranged in an array to form a memory block. 5. The predetermined monitor means of the memory block according to claim 4, wherein the evaluation monitor is formed so as to pair the memory means with both ends in the horizontal direction and both ends in the vertical direction. A characteristic semiconductor integrated circuit. 6. The memory block according to claim 5 is arranged in an array to form an array block, and the evaluation monitor of the same kind or different kinds of evaluation objects is formed for each memory block. Integrated semiconductor circuit. 7. The semiconductor integrated circuit according to claim 6, wherein the memory blocks in which the same type of evaluation monitor is formed are uniformly arranged in the array block.