JPH09306166A - Boosting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a boosting circuit which can cope with power source voltage widely used, can secure operation margin in low power source voltage, and can avoid excessive stress applied to a gate insulation film of a transistor in high power source voltage. SOLUTION: By controlling a level of a boosting stop signal BTOF inputted to an input terminal Tc , a level of a boosting circuit control signal BCTL generated by a boosting circuit control section 20 is adjusted, and a level of a boosting voltage VOUT generated by a boosting voltage generation section 30. Thereby, the boosting stop signal BTOF of a high level is inputted at the operation of low power source voltage, boosting voltage VOUT is generated, operation margin can be secured, the boosting stop signal BTOF of a low level is inputted at the operation of high power source voltage, boosting operation of the boosting voltage generation section 30 is stopped, and stress applied to a gate insulation film of an access transistor can be reduced and power consumption can be reduced by outputting power source voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a booster circuit for supplying a boosted voltage to a memory device, for example.

[0002]

2. Description of the Related Art Conventionally, a capacitor has been used for a memory cell.
In a semiconductor memory device such as a DRAM, a memo
At the time of re-access, the bit line or bit
In order to transfer charges from the memory line to the memory cell without waste,
Access transistor for connecting memory cell and bit line
Power supply voltage V_CCAccess at least
Threshold voltage V of the transistor_thThe voltage set high
Pressure, so-called power supply voltage V _CCThe voltage of + α is the access transistor
Applied to the word line to which the gate electrode of the transistor is connected
You.

This is because the access transistor connecting the memory cell and the bit line is often composed of an n-channel MOS transistor (hereinafter referred to as an nMOS transistor) in layout and capacity, and the memory cell is connected to the bit line or the bit line. This is for avoiding a voltage drop between the source diffusion layer and the drain diffusion layer of the nMOS transistor when the charge is transferred from the memory cell to the memory cell, and if the boosted voltage is set sufficiently higher than the power supply voltage V _CC ,
This is because the influence of this voltage drop can be avoided.

[0004]

By the way, in recent years, as the process miniaturization technology has advanced, the gate insulating film of the access transistor has been made thinner, which lowers the withstand voltage level of the access transistor. Excessive stress is applied, which is not preferable in terms of transistor reliability. Especially when the power supply voltage V _CC is used over a wide range, in order to secure an operation margin during low voltage operation,
Although the boosting rate (ratio between boosted voltage and power supply voltage) is set higher, there is a conflicting problem that excessive stress is applied to the gate insulating film of the access transistor during high voltage operation.

The present invention has been made in view of such circumstances, and an object thereof is to cope with a power supply voltage used over a wide range, to secure an operation margin at a low voltage, and to obtain a gate insulating film of a transistor under a high voltage. An object of the present invention is to provide a booster circuit that can avoid the stress on the.

[0006]

In order to achieve the above object, the present invention is capable of boosting a power supply voltage to at least two levels, and selects one of a plurality of boosting levels according to the input of a boosting control signal. Voltage generating means for selecting a boosted voltage of one level and supplying the boosted voltage to an object to be boosted, and a boosting control signal indicating the boosting level to be selected by the voltage generating means, receiving the control signal from the outside, and the voltage generating means. And a control means for outputting to.

Preferably, the control means receives a second control signal from the outside and outputs a boosting control signal for instructing the voltage generating means to stop the boosting operation and output the power supply voltage. . Further, it has a timing control means for controlling the timing of the boosting operation of the voltage generating means in response to a third control signal from the outside.

According to the present invention, the control means generates the boosting control signal instructing the boosting level according to the control signal from the outside, and outputs the boosting control signal to the voltage generating means. The voltage generating means generates a boosted voltage having a level designated by the boosting control signal, and outputs the boosted voltage to the supply target of the booster circuit. Also,
In accordance with the second control signal, the step-up control means switches the operation / stop state of the step-up circuit. When the operating state is set, the boosted voltage of the level set by the control signal is generated, and when the operating state is set, the power supply voltage is output by the voltage generating means. Furthermore, the third from the outside
In response to the control signal, the timing control means controls the timing of the boosting operation of the voltage generating means.

As a result, the boosting rate of the booster circuit can be switched according to a control signal from the outside, and by setting the boosting rate high during low voltage operation, an operating margin can be secured and the boosting rate during high voltage operation can be maintained. By setting the voltage low or stopping the boosting operation, the stress applied to the gate insulating film of the transistor can be reduced, and the power supply voltage used in a wide range can be dealt with.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION First Embodiment FIG. 1 is a circuit diagram showing a first embodiment of a booster circuit according to the present invention. In FIG. 1, 10 is a timing control unit,
20 is a booster circuit control unit, 30 is a boosted voltage generation unit, 40 is a memory cell array, T _C is a boost stop signal BTOF (second
Input terminal of the control signal), T _OUT denotes an output terminal of the boosted voltage V _OUT, respectively.

The timing controller 10 controls the chip start signal R
Upon receiving the AS and the address signal ADR, a booster circuit activation signal BTST is generated after a predetermined delay time has elapsed, and is output to the booster circuit controller 20.

The booster circuit controller 20 is the timing controller 1
Booster circuit start signal BTST from 0 and input terminal T _C
In response to these control signals, the boost voltage generation unit 30 receives a boost stop control signal BTOF from the boost circuit control signal BC.
Output TL. For example, when receiving the high level boost stop signal BTOF from the input terminal T _C , the boost circuit control unit 20 keeps the high level, while the boost circuit activation signal BTST from the timing control unit 10 is held at the high level, For example, boosting circuit control signal BCTL of power supply voltage V _CC level is generated and output to boosted voltage generating unit 30. On the other hand, a low level boost stop signal BTO from the input terminal T _C
Upon receiving F, the booster circuit control unit 20 holds the booster circuit control signal BCTL at a low level.

The boosted voltage generator 30 is a booster circuit controller 20.
The boosting circuit control signal BCTL is received, the boosting operation is performed in response to the boosting circuit control signal BCTL, and the boosted voltage V _OUT is generated and supplied to the memory cell array 40. While the booster circuit control signal BCTL of high level is input from the booster circuit control unit 20, the boosted voltage generation unit 30 performs the boosting operation, and the boosted voltage V
_OUT is generated and supplied to the memory cell array 40. On the other hand, when receiving the boost circuit control signal BCTL held at the low level from the boost circuit control unit 20, the boost voltage generation unit 30 stops the boost operation and supplies the power supply voltage V _CC to the memory cell array 40.

FIG. 2 is a timing chart of the booster circuit shown in FIG. The operation of the circuit configuration described above will be described below with reference to the timing chart of FIG. 2A shows a timing chart of the timing control unit 10, and FIG. 2B shows a timing chart of the booster circuit control unit 20.

As shown in FIG. 2A, at time t ₀ , the chip activation signal RAS is in an active state, for example,
Switch to low level. The chip activation signal RAS
Address signal ADR before switching to active state
Has been confirmed.

In the timing control unit 10, the chip start
To the address signal ADR after the motion signal RAS is input.
Therefore, it is enough to confirm the selected memory cell.
In order to secure time, the fall of the chip activation signal RAS
Delay time T from the edge_DAfter the passage of
Booster circuit start signal BT held at high level within time
ST is generated. For example, as shown in FIG.
At the falling edge of the chip activation signal RAS
Time t₀To delay time T_DTime t after ₁From
Time T_PBoost circuit start signal held at high level inside
BTST is generated.

As shown in FIG. 2B, the booster circuit control unit 20 receives the booster circuit activation signal BTST from the timing control unit 10 and the booster stop signal BTOF input from the input terminal T _C, and receives the booster circuit. Start signal BTST
Is held at the high level, the boost stop signal BT
Booster circuit control signal BCTL is generated according to the level of OF. High level boost stop signal B from input terminal T _C
When receiving the TOF, while the booster circuit activation signal BTST is held at the high level, a high level, for example,
The booster circuit control signal BCTL at the power supply voltage V _CC level is generated. Low level boost stop signal B from input terminal T _C
When receiving the TOF, the booster circuit control signal BCTL is held at the low level, for example, the ground potential GND level.

Further, before the chip activation signal RAS becomes active, that is, before the time t _{0 when} the falling edge of the chip activation signal RAS appears, the boosting stop signal BTOF is supplied from the input terminal T _C to the booster circuit controller 20. Entered in.

The boosted voltage generator 30 is operated according to the booster circuit control signal BCTL from the booster circuit controller 20 to generate the boosted voltage V _OUT , and the memory cell array 4 is operated.
0 is supplied. While the high-level booster circuit control signal BCTL is being input from the booster circuit controller 20, the booster voltage generator 30 performs the boosting operation to generate the boosted voltage V _{OUT, which} is output to the output terminal T _OUT. , A low-level booster circuit control signal BCT from the booster circuit control unit 20.
While L is being input, in the boosted voltage generation unit 30, the boosting operation is stopped and the power supply voltage V _CC is output terminal T _OUT.
Is output to

For example, during low voltage operation, the input terminal T _C
By inputting the high-level boost stop signal BTOF to the, the boost circuit control unit 20 generates the high-level boost circuit control signal BCTL, and in response to this, the boost voltage generation unit 30 boosts the power supply voltage V _CC + α. A voltage V _OUT is generated. Here, α is a voltage equal to or higher than the threshold voltage V _th of the nMOS transistor forming the access transistor. As a result, an operation margin at the time of low voltage operation is secured, and the charge transfer efficiency between the memory cell and the bit line can be improved.

Further, at the time of high voltage operation, by inputting the low level boost stop signal BTOF to the input terminal T _C , the boost operation of the boost voltage generator 30 is stopped and the power supply voltage V _CC is output. As a result, stress applied to the gate insulating film of the access transistor during high voltage operation can be reduced, and reliability of the memory device can be improved and power consumption can be reduced.

As described above, according to the present embodiment, the booster circuit control unit 20 is controlled by controlling the level of the signal input to the input terminal T _C of the boost stop signal BTOF.
Is adjusted by adjusting the level of the booster circuit control signal BCTL, and the boosted voltage V of the boosted voltage generation unit 30 is adjusted accordingly.
Control _OUT level. For example, at low voltage operation,
The boost stop signal BTOF of high level is input, the boost voltage generation unit 30 is operated to output the boost voltage V _OUT , the operation margin at the time of low voltage operation can be secured, and the boost stop signal BTOF of low level at the time of high voltage operation can be secured. Is input to stop the boosting operation of the boosted voltage generating section 30 and output the power supply voltage V _CC , and it is possible to reduce the stress applied to the gate insulating film of the access transistor during the high voltage operation, thereby reducing the power consumption of the circuit. .

Second Embodiment FIG. 3 is a circuit diagram showing a second embodiment of the booster circuit according to the present invention, and is a diagram showing a concrete configuration example of the booster circuit. In FIG. 3, T _RAS input terminals of the chip activation signal RAS (third control _{signal), T A0, T A1,} ..., T AN address signal ADS _0, ADS _1, ..., the input terminal of the ADS _N, T _S is an input terminal for the voltage control signal VOLT (control signal), T _C is an input terminal for the boost stop signal BTOF (second control signal), ADRBUF ₀ , ADRBUF ₁ , ..., AD
RBUF _N is an address buffer, 10 is a timing control unit, 20 is a booster circuit control unit, 30 is a boosted voltage generation unit, 4
Reference numeral 0 indicates a memory cell array, and reference numerals 50 and 60 indicate address decoders.

As shown in the figure, the input terminal T _RAS of the chip activation signal _RAS has the address buffers ADRBUF ₀ , AD.
RBUF _1, ..., are connected to ADRBUF _N and the timing control unit 10, the chip activation signal RAS is active, for example, when held at a low level, the address buffer _{ADRBUF 0, ADRBUF 1, ...,} AD
The address signal A input to the address signal input terminals T _A0 , T _A1 , ..., T _AN when RBUF _N is set to the conductive state.
DS ₀ , ADS ₁ , ..., ADS _N are address buffers A
The address signal ADR is generated by being input to the address decoder 50 via DRBUF ₀ , ADRBUF ₁ , ..., ADRBUF _N.

The timing control unit 10 uses the address signal AD
It operates according to R and the chip activation signal RAS, and after a predetermined delay time has passed from the falling edge of the chip activation signal RAS, generates the booster circuit activation signal BTST and outputs it to the booster circuit control unit 20.

The booster circuit controller 20 is the timing controller 1
0 boosting circuit start signal BTST and input terminal T_S
The voltage control signal VOLT input from the
The booster circuit control signal BCTL is output to the pressure generator 30.
As shown in FIG. 3, the timing control unit 10 has a NOR gate.
NRGT, delay circuit DLY₁, DLY_Two, Nand Gate
NGT and inverter INV₀₁, INV₀₂Composed by
Have been. Address input to the input side of NOR gate NRGT
When the address signal ADR from the coder 50 is input,
The output signal of the gate NRGT is the delay circuit DLY.₁Through
It is input to the NAND gate NGT. Inverter INV₀₁
The chip activation signal RAS is input to the input terminal of the
Data INV₀₁Output signal of the delay circuit DLY_TwoThrough
Input to the NAND gate NGT. Nand Gate NGT
Output signal is inverter INV₀₂Input to the inverter
INV₀₂Output signal of the booster circuit start signal BTST
And output to the booster circuit controller 20.

Although not shown, the timing control unit 10 has a boost stop signal B input from the input terminal T _C.
A control circuit for holding the output level of the booster circuit activation signal BTST at a low level, for example, the ground potential GND when receiving the TOF is provided.

The boost voltage generator 30 is a boost circuit controller 20.
In response to the booster circuit control signal BCTL from, the boosting operation is performed to generate the boosted voltage V _OUT and supply it to the address decoder 60.

In response to the address signal ADR from the address decoder 50, the address decoder 60 supplies the boosted voltage V _OUT from the boosted voltage generator 30 to the word line WL _n to which the memory cell designated by the address signal ADR is connected.
Of the address signal AD from the memory cell array 40
A memory cell is selected according to R.

As described above, in the second embodiment, the booster circuit controller 20 controls the timing controller 10 according to the level of the voltage control signal VOLT input to the input terminal T _S of the voltage control signal VOLT. The booster circuit control signal BCTL is generated and input to the boosted voltage generator 30 while the booster circuit activation signal BTST generated in step 1 is held at the high level. The boosted voltage generator 30 generates a boosted voltage V _OUT at a level according to the booster circuit control signal BCTL from the booster circuit controller 20 and supplies it to the address decoder 60.

FIG. 4 shows a booster circuit control unit 20 and a boosted voltage.
3 is a circuit diagram showing a specific configuration example of a generation unit 30. FIG. Illustrated
As shown in FIG.₁,
INV_Two, INV _ThreeAnd Nand Gate NGT₁, NG
T_TwoThe boost voltage generator 30 is configured by
TAINV_Ten, INV₁₁, PMOS transistor PT₁,
PT_TwoAnd boosting capacitor C₁, C_TwoComposed by
Have been. Inverter INV₁, INV_Two, I
NV_ThreeAnd Nand Gate NGT₁, NGT_TwoIs power
Pressure V_CCIs the operating voltage, and the inverter INV_Ten, INV₁₁
Is the boosted voltage V from the boosted voltage generator 30._OUTThe operating voltage
Receive as.

In the booster circuit controller 20, the input terminal T
_IN is an input terminal of the inverter INV ₁ , a NAND gate NG
They are connected to the input terminals of T ₁ and NGT ₂ , respectively.
The booster circuit activation signal BTST from the timing controller 10 is input to the input terminal T _IN , and the voltage control signal VOLT is input to the input terminal T _S. One input terminal of the NAND gate NGT ₁ is connected to the input terminal T _IN , and the other input terminal is connected to the output terminal of the inverter INV ₂ . The input terminal of the inverter INV ₂ has a voltage control signal VO.
It is connected to the input terminal T _{S of the} LT.

One input terminal of the NAND gate NGT ₂ is connected to the input terminal T _IN of the booster circuit start signal BTST,
The other input terminal is the input terminal T _S of the voltage control signal VOLT.
It is connected to the. The output terminal of the NAND gate NGT ₂ is connected to the electrode of the capacitor C ₂ of the boost voltage generator 30 via the inverter INV ₃ .

In the boosted voltage generating section 30, the drain diffusion layer of the pMOS transistor PT ₁ is connected to the supply line of the power supply voltage V _CC , and the source diffusion layer is connected to the output terminal T _OUT of the boosted voltage V _OUT . pMOS transistor P
Output terminal T _{OU T} of the source diffusion layer of T ₂ is the boosted voltage V _OUT
And the drain diffusion layer is connected to the electrode of the capacitor C ₂ . In addition, the pMOS transistor PT ₁ ,
The gate electrodes of PT ₂ are inverters INV ₁₀ and I
It is connected to the output terminal of NV ₁₁ . Inverter INV
The input terminal ₁₀ is the inverter INV of the booster circuit control unit 20.
Is connected to the _first output terminal, the input terminal of the inverter INV ₁₁ is connected to the output terminal of the NAND gate NGT ₁ of the booster circuit controller 20.

One electrode of the capacitor C ₁ is connected to the input terminal T _IN of the booster circuit activation signal BTST, and the other electrode is connected to the output terminal T _OUT of the boosted voltage V _OUT .
One electrode of the capacitor C ₂ is connected to the output terminal of the inverter INV ₃ , and the other electrode is connected to the drain diffusion layer of the pMOS transistor PT ₂ .

The capacitor C ₁ is used as a boost capacitor and the capacitor C ₂ is used as a sub boost capacitor. When a low level signal is input to the input terminal T _S of the voltage control signal VOLT, the boost capacitor C ₁
When only a high level signal is input to the input terminal T _S of the voltage control signal VOLT, the boost capacitor C ₁ and the sub boost capacitor C ₂ are not used, the boost rate of the boost circuit is set low, and the boost capacitor C ₁ and Both the sub-boost capacitors C ₂ contribute to the boosting operation, and the boosting rate of the booster circuit is set high.

Hereinafter, in the configurations of the booster circuit control unit 20 and the boosted voltage generation unit 30 described above, the operation of the booster circuit will be described with reference to the timing chart of the boosted circuit control unit 20 and the boosted voltage generation unit 30 shown in FIG. explain. Note that FIG. 5A shows the input terminal T _{S of the} voltage control signal VOLT.
5B is a timing chart in the case where a low-level signal is input to FIG. 5, and FIG. 5B is a timing chart in the case where a high-level signal is input to the input terminal T _S of the voltage control signal VOLT.

[0038] As shown in FIG. 5 (a), before the boosting circuit start signal BTST is input to the input terminal T _IN, the input terminal T _IN is held at the low level, the inverter INV
₁ and the output terminal of the NAND gate NGT ₁ are held at the high level, and the output terminal of the inverter INV ₁₀ (node N
D ₄ ) and the output terminal of the inverter INV ₁₁ (node N
D ₆ ) are both low level, for example, ground potential GND
Is held. Therefore, the pMOS transistor P
Both T ₁ and PT ₂ are conductive.

Further, the node ND ₅ connected to the input terminal T _IN of the booster circuit activation signal BTST is held at the low level, and further the output terminal of the inverter INV ₃ , that is, the node ND ₇ is held at the low level. There is. Therefore, the capacitors C ₁ and C ₂ are charged by the power supply voltage V _CC, and the node ND ₃ and the capacitor C ₂ connected to the output terminal T _OUT of the boost voltage generator 30 and the drain diffusion layer of the pMOS transistor PT ₂ are connected. Both nodes ND ₈ formed by the connection points are held at the power supply voltage V _CC level.

From the time t ₁ to the input terminal T _IN , the time width T _P
Booster circuit start signal BTS held at high level during
T is applied. From the rising edge of the booster circuit start signal BTST, the inverter INV ₁ and the inverter I
After the delay time of NV ₁₀ has passed, the node ND ₄ switches to the high level, and after the delay time of the NAND gate NGT ₁ and the inverter INV ₁₁ has passed, the node ND 4
_{Since 6} also switches to the high level, the pMOS transistors PT ₁ and PT ₂ switch to the non-conducting state.

Input terminal T of voltage control signal VOLT_SIs
Node ND because it is kept at the high level₇Is low
Retained on level. On the other hand, node ND_FiveBoost circuit system
Since the control signal BCTL is applied,
For example, power supply voltage V_CCRetained on level. Capacitor
C₁By capacitive coupling of the node ND_Three, That is, out
Force terminal T_{OU T}Is boosted, for example, 2V_CCUp to level
Boosted. As a result, the booster circuit start signal BTST is
While held at the high level, the boost voltage generator 30
Output terminal T_OUTAbout 2V_CCBoosted voltage V_OUTIs output
It is. Actually, boosted voltage V_OUTNore
Bell is 2V_CCPower supply voltage V_CCHigher,
2V_CCThe following voltage is the boost voltage V_OUTAs a boost voltage
Output terminal T of raw part 30 _OUTIs output to

The inverter INV_Ten, INV₁₁Rises
Pressure voltage V_OUTSince it is operating as the operating voltage,
If the output terminals of these inverters are held at high level
Node ND_FourAnd node ND₆Is the boost voltage
Pressure V_OUTIt becomes the level of. Therefore, the pMOS transistor
Star PT₁, PT_TwoWhen the
Pressure V_OUTLevel high voltage is applied, pMOS transistor
Star PT₁, PT _TwoLeakage current is prevented
It is.

The boosting operation when a high level signal is input to the input terminal T _S of the voltage control signal VOLT will be described below with reference to the timing chart of FIG. The voltage control signal VOLT is shown in FIG.
Of the input terminal T _S , the nodes ND ₆ , ND ₇ , and ND ₈ and the output terminal T _OUT are shown, and the timing charts of the other nodes are the same as those in FIG. 5A.

As shown, when the voltage control signal VOLT is held at the high level, the booster circuit start signal BT
After a lapse of the delay time of the NAND gate NGT ₂ and the inverter INV ₃ from the rising edge of ST, that is, the time t ₁ , the node ND ₇ switches to the high level.

Also, the NAND gate NGT₁Output terminal of
Since it is held at high level, the inverter INV₁₁Out of
Input terminal is held at low level and pMOS transistor
PT _TwoAre held in a conductive state. Therefore, the node ND
₈And node ND_ThreeThat is, the output of the boost voltage generator 30
Force terminal T_OUTPMOS transistor P in a conductive state
T_TwoConnected via a capacitor C_TwoGenerated boost voltage
It is used for the boosting operation of the unit 30.

By the capacitive coupling of the capacitors C ₁ and C ₂ ,
The nodes ND ₃ and ND ₈ are boosted, and the boosted voltage V _OUT having a higher level than that when only the capacitor C ₁ is used is output to the output terminal T _OUT .

Further, the boost stop signal BTO shown in FIG.
F input terminal T _C is at a high level, for example, power supply voltage V
_{When the CC} level signal is input, as described above, the timing control unit 10 causes the booster circuit start signal BT to be generated.
ST is held at a low level, for example, ground potential GND. In response to this, in the boosted voltage generation unit 30, both the node ND ₄ and the node ND ₅ are held at the low level, so that the pMOS transistor PT ₁ is held in the conductive state and the output terminal T _OUT of the boosted voltage generation unit 30 is held. It is connected to the supply line of the power supply voltage V _CC via the pMOS transistor PT ₁ in the conductive state, and the voltage of the power supply voltage V _CC level is output to the output terminal T _OUT . That is, when the high-level boost stop signal BTOF is received, the boost operation of the boost voltage generation unit 30 is stopped, and the power supply voltage V _CC level voltage is output to the output terminal T _OUT .

FIG. 6 shows the boosted voltage V _OUT in this embodiment.
7 is a graph showing the relationship between the power supply voltage V _CC and the power supply voltage V _CC . As shown in FIG. 6, when the power supply voltage V _CC is at a low level, for example, below the level of the voltage V _CC1 , the voltage control signal VOLT is set at a high level to increase the boost rate of the boost voltage V _OUT , that is, boost. The ratio between the voltage V _OUT and the power supply voltage V _CC is set high. When the power supply voltage V _CC is equal to or higher than the level of the voltage V _CC1 , for example, between the illustrated voltage V _CC1 and the voltage V _CC2 , the boosted voltage V _OUT is boosted by setting the voltage control signal VOLT to a low level. The rate is set low.

As a result, the boosting rate is set high during the low voltage operation to secure an operating margin, and the boosting rate is set low during the high voltage operation, or the boosting operation is stopped by the boost stop signal BTOF, and the power supply is stopped. The voltage V _CC level is supplied with the voltage, and it is possible to avoid applying excessive stress to the gate insulating film of the access transistor during memory access.

As described above, according to the present embodiment, the boosting voltage generator 30 includes the boosting capacitors C ₁ and C _2.
And the pMOS transistors PT ₁ and PT ₂ of the boost voltage generation unit 30 are both set to the conductive state when the boost circuit activation signal BTST is held at the low level, and the capacitors C ₁ and C ₂ are set to the power supply voltage V _CC level. When the voltage control signal VOLT is set to the high level when the booster circuit start signal BTST is held at the high level, both capacitors C ₁ and C ₂ contribute to the boosting operation, and the high level boosted voltage V _OUT And the voltage control signal VOLT is set to the low level, the capacitor C ₂ is not used and only the capacitor C ₁ contributes to the boosting operation to generate the boosted voltage V _OUT at the low level. by setting the voltage control signal VOLT according to V _CC, the boosted voltage of a high level occurs at low voltage operation, the boosted voltage level at the high voltage operation By stopping the El or boosting operation, it corresponds to the supply voltage V _CC to be used over a wide range.

Further, in the reliability test, for example, in the withstand voltage test of the gate insulating film of the access transistor of the memory cell array 40, by setting the voltage control signal VOLT to a high level, a high boosted voltage V _{OUT can be obtained.}
Is generated and an accelerated test is performed. Further, when the reliability test of the entire chip is performed, the voltage control signal VOLT is set to a low level, the boost rate is set to a low level, or the boost operation is stopped to set the power supply voltage V _CC to a high level. The measurement time can be shortened by applying stress to the entire chip with a high power supply voltage without applying excessive stress to the booster circuit.

[0052]Third embodiment FIG. 7 shows a third embodiment of the booster circuit according to the present invention.
It is a circuit diagram. In FIG. 7, 20a is a booster circuit control
Reference numeral 30a denotes a boosted voltage generator. Figure
As shown, two voltage control signals VOLT₁, VOLT
_TwoIs provided, and these two voltage control signals are input terminal T
_S1, T_S2Are input respectively. Booster circuit controller 20a
In NANDGATE NGT₁, Inverter INV
_Two, Nand Gate NGT_TwoAnd inverter INV_ThreeWhen
NAND gate NGT having substantially the same connection relationship_Three, INVA
Data INV_Four, Nand Gate NGT_FourAnd inverter
INV_FiveIs provided.

Further, in the boosted voltage generator 30, a sub-boost capacitor C ₃ is provided in addition to the sub-boost capacitor C ₂ , and the pMOS transistor PT ₃ for connecting or disconnecting the capacitor C ₃ to the node ND _8.
And an inverter INV ₁₂ are provided. The inverter INV ₁₂ receives the voltage of the node ND ₈ as an operating voltage.

Capacitor C₁, C_TwoPart composed by
The step-up operation for a minute is similar to that of the second embodiment described above,
Where capacitor C_ThreeOnly for boost operation
explain. Input terminal T_INBooster circuit start signal input to
When BTST is held at the low level, the node N
D₉Is held at a low level, and the NAND gate NG
T _ThreeOutput terminal of the inverter I
NV₁₂Since the output terminal of is held at low level,
pMOS transistor PT_ThreeIs in conduction. As well
The booster circuit start signal BTST is held at the low level.
The pMOS transistor PT₁, PT_TwoAlso guide
It is open. Node ND₉Is kept low
Therefore, the capacitor C_ThreeIs the power supply voltage V_CCCharge to level
Is done.

When the booster circuit start-up signal BTST switches to the high level, the conduction state of the pMOS transistor PT ₃ is input to the input terminal T _S2 and the voltage control signal VOLT is input.
Depends on ₂ levels. For example, when the high-level voltage control signal VOLT ₂ is input to the input terminal T _S2 , the input terminal of the inverter INV ₁₂ is held at the high level and the output terminal of the inverter INV ₁₂ is held at the low level. The transistor PT ₃ is conductive, and the node ND ₉ is connected to the booster circuit start signal BTS.
After the delay time of the NAND gate NGT ₂ and the inverter INV ₅ has passed from the rising edge of T, it switches to the high level, and the node ND ₁₀ , that is, the connection point between the capacitor C ₃ and the drain diffusion layer of the pMOS transistor PT ₃ is changed to the capacitor. Boosted by capacitive coupling of C ₃ ,
PMOS transistor PT ₂ whose boosted voltage is conductive
And PT ₃ via the output terminal T of the boost voltage generator 30.
_It is output to _OUT .

On the other hand, the input terminal T_S2Low level voltage control
Signal VOLT_TwoIs input, the inverter I
NV₁₂The input terminal of the
INV₁₂Since the output terminal of is held at high level, p
MOS transistor PT_ThreeIs in a non-conducting state. others
Therefore, the capacitor C_ThreeIs the boost node ND₈Separated from
And the capacitor C _ThreeIs for boosting operation of the boosted voltage generator 30.
Does not contribute.

Thus, the input terminal T_S1, T_S2Entered in
Voltage control signal VOLT₁, VOLT_TwoControl the level of
Control the capacitor that contributes to the boost operation.
Output terminal T of the boost voltage generator 30_OUTOutput to
Boosted voltage V_OUTThe level of can be adjusted in multiple stages. Was
For example, the voltage control signal VOLT₁, VOLT_TwoTogether with
By setting to low level, the capacitor C_Two, C
_ThreeTogether with the output terminal T of the boost voltage generator 30 _OUTCut off
Separated, capacitor C₁Only contribute to boost operation, boost
The rate is set low. On the other hand, the voltage control signal VOLT
₁High level, voltage control signal VOLT_TwoThe low level
Setting the boost circuit start signal BTST to high
PMOS transistor when held at level i
PT_TwoIs set to the conductive state, and the pMOS transistor P
T_ThreeIs set to the non-conduction state, the capacitor C_TwoBut
Contributes to boosting operation, and the capacitor C_ThreeIs separated. This
Therefore, the capacitor C₁Higher boosted voltage V than when only
_OUTIs generated and a high boost rate is obtained.

Then, the voltage control signal VOLT₁, VOL
T_TwoAre both set to high level,
If the road start signal BTST is held at high level
PMOS transistor PT_Two, PT_ThreeAre both conducting
Is set to the state and the capacitor C _Two, C_ThreeAre both boosting
Capacitor C₁And C_TwoOnly when
Higher boosted voltage V_OUTGenerated, higher boost
You get the rate.

Thus, the voltage control signals VOLT ₁ , V
By adjusting the logical combination of OLT ₂ , it is possible to control the number of capacitors that contribute to the boosting operation, whereby the boosting rate can be set in multiple stages, and with respect to the power supply voltage V _CC used over a wide range, The effect of stabilizing the boosted voltage V _OUT is obtained.

Furthermore, in the third embodiment as well,
Timing control when pressure stop signal BTOF is input
The booster circuit start-up signal BTST goes low by the section 10.
The boosting operation of the boosted voltage generator 30a is stopped,
Output terminal T_OUTPower supply voltage V _CCLevel voltage is output
You. Therefore, when operating with a high power supply voltage,
By stopping the boost operation and outputting the power supply voltage,
It can reduce stress when operating at high power supply voltage and low power consumption.
Can be reduced.

As described above, according to the present embodiment, the boosting voltage generator 30a includes the boosting capacitors C ₁ and C.
₂ and C ₃ are provided, and when the booster circuit start signal BTST is held at the low level, the pMOS of the boosted voltage generator 30a is
Transistors PT ₁ , PT ₂ and PT ₃ are both set in a conductive state, and capacitors C ₁ , C ₂ and C ₃ are connected to power supply voltage V _CC.
When the voltage is charged to the level and the booster circuit start signal BTST switches to the high level, the voltage control signals VOLT ₁ , VLT ₁
By combining the logic of OLT ₂ , the number of capacitors contributing to the boosting operation is adjusted, the level of the boosting voltage V _OUT is adjusted in multiple stages, and the boosting operation is stopped by the boosting stop signal BTOF. The power supply voltage V _CC can be supported, the boosting rate can be set in multiple stages, an operation margin at low voltage can be secured, and stress at high voltage and power consumption can be reduced.

[0062]

As described above, according to the booster circuit of the present invention, the boosting rate is increased during low voltage operation to secure an operating margin, and the boosting rate is decreased during high voltage operation to reduce the gate insulating film of the access transistor. It is possible to reduce stress on the memory device, improve reliability of the memory device, and reduce power consumption. Further, in the reliability test, there is an advantage that a stressed acceleration test can be performed by increasing the boosting rate at a high voltage to shorten the measurement time.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a booster circuit according to the present invention.

FIG. 2 is a timing chart in the first embodiment.

FIG. 3 is a circuit diagram showing a second embodiment of a booster circuit according to the present invention.

FIG. 4 is a configuration diagram of a booster circuit controller and a boosted voltage generator according to the second embodiment.

FIG. 5 is a timing chart according to the second embodiment.

FIG. 6 is a graph showing the relationship between the boosted voltage V _OUT and the power supply voltage V _CC in the second embodiment.

FIG. 7 is a circuit diagram showing a third embodiment of a booster circuit according to the present invention.

[Explanation of symbols]

10 ... Timing control unit, 20, 20a ... Boost circuit control unit, 30, 30a ... Boost voltage generation unit, 40 ... Memory cell array, 50, 60 ... Address decoder, T _IN ... Boost circuit activation signal BTST input terminal, T _S , T _S1 , T _S2 ... Voltage control signals VOLT, VOLT ₁ , VOLT ₂ input terminals, T _OUT ... Boosted voltage V _OUT output terminals, INV ₁ , I
_{NV 2 ,, INV 5, INV 10} , INV 11, INV 12 ...
Inverter, NGT ₁ , NGT ₂ , NGT ₃ , NGT ₄
NAND gate, PT ₁ , PT ₂ , PT ₃ ... pMOS transistor, V _CC ... Power supply voltage, GND ... Ground potential.

Claims (3)

[Claims] 1. A voltage capable of boosting a power supply voltage to at least two or more levels, and selecting a boosted voltage of one of a plurality of boosted levels according to an input of a boosting control signal and supplying the boosted voltage to a boost target. A booster circuit having a generating means and a control means for receiving a control signal from the outside and outputting the boosting control signal indicating the boosting level to be selected by the voltage generating means to the voltage generating means. 2. The control means receives a second control signal from the outside and outputs a boost control signal for instructing the voltage generating means to stop the boost operation and output the power supply voltage. The booster circuit described. 3. The booster circuit according to claim 1, further comprising timing control means for controlling the timing of the boosting operation of said voltage generating means in response to a third control signal from the outside.