JPH09298285A - Integrated circuit device incorporating light receiving elements and manufacture thereof - Google Patents

Integrated circuit device incorporating light receiving elements and manufacture thereof

Info

Publication number
JPH09298285A
JPH09298285A JP8109274A JP10927496A JPH09298285A JP H09298285 A JPH09298285 A JP H09298285A JP 8109274 A JP8109274 A JP 8109274A JP 10927496 A JP10927496 A JP 10927496A JP H09298285 A JPH09298285 A JP H09298285A
Authority
JP
Japan
Prior art keywords
light receiving
integrated circuit
region
receiving element
light
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8109274A
Other languages
Japanese (ja)
Other versions
JP2882354B2 (en
Inventor
Masahiko Kawaratani
正彦 瓦谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP8109274A priority Critical patent/JP2882354B2/en
Publication of JPH09298285A publication Critical patent/JPH09298285A/en
Application granted granted Critical
Publication of JP2882354B2 publication Critical patent/JP2882354B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide an integrated circuit device incorporating a plurality of light receiving elements wherein an integrated circuit and the plurality of light receiving elements are formed adjacent to each other on a semiconductor substrate, which can be made small in size and low in power consumption, can improve its productivity and be made low in its manufacturing cost; and also to provide a method for manufacturing the integrated device. SOLUTION: Three light receiving parts (N<-> epitaxial layer 3) are divided on a semiconductor substrate 1 as surrounded by a P<+> type element isolation diffusion region 2b and a P<+> type buried region 2a. In this way, the high-concentration region having the same conduction type as the semiconductor substrate 1 is subjected to an element isolation of the light receiving region by means of burying and diffusing processes used at the time of forming a transistor to thereby form a light receiving part. As a result, since minor carriers generated by light illuminated on an area other than the light receiving part can be captured, cross-talk can be prevented. Since an additional formation step in the same process as an integrated circuit is eliminated, its productivity can be improved. Further, since fine processing is possible, its miniaturization can be realized. Since it can be made in the form of an integrated circuit, a low power consumption can be realized.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、複数個の受光素子
を集積回路と同一基板上に形成した受光素子内蔵集積回
路装置及びその製造方法に関し、特に、コンパクトディ
スク(以下“CD”と略記する)等の光ディスクピックア
ップ装置に係る素子内蔵集積回路装置及びその製造方法
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device with a built-in light receiving element in which a plurality of light receiving elements are formed on the same substrate as an integrated circuit and a method for manufacturing the same, and more particularly to a compact disc (hereinafter abbreviated as "CD"). ) And the like, the present invention relates to a device-integrated integrated circuit device for an optical disk pickup device and a method for manufacturing the same.

【0002】[0002]

【従来の技術】マルチメディア化が進むなか、光半導体
素子と集積回路の融合技術が普及しつつある。特に、受
光部が半導体受光素子を複数個配列してなる受光素子内
蔵集積回路装置,CD等に用いられるピックアップ信号
読取等各分野で実用化がなされている。
2. Description of the Related Art Along with the progress of multimedia, a technique of integrating an optical semiconductor element and an integrated circuit is becoming popular. In particular, it has been put to practical use in various fields such as an integrated circuit device with a built-in light receiving element in which a plurality of semiconductor light receiving elements are arranged in a light receiving portion, and a pickup signal reading used in a CD or the like.

【0003】このような半導体受光素子として、例えば
特開平3−156980号公報に記載されているような受光素
子、即ち、「半導体結晶の光吸収領域に受光領域が複数
個形成された受光素子において、隣接する前記受光領域
間の光吸収領域の一部が空乏化されている受光素子。」
が知られている。
As such a semiconductor light receiving element, for example, a light receiving element as described in Japanese Patent Application Laid-Open No. 3-156980, that is, "in a light receiving element in which a plurality of light receiving regions are formed in a light absorbing region of a semiconductor crystal, , A light receiving element in which a part of the light absorption region between the adjacent light receiving regions is depleted. ”
It has been known.

【0004】上記従来の半導体受光素子について、図5
を参照して具体的に説明する。なお、図5は、従来の半
導体受光素子を説明する図であって、(A)はその平面図
であり、(B)は(A)のX−X線断面図である。
FIG. 5 shows the conventional semiconductor light receiving element described above.
This will be specifically described with reference to FIG. 5A and 5B are views for explaining a conventional semiconductor light receiving element, FIG. 5A is a plan view thereof, and FIG. 5B is a sectional view taken along line XX of FIG.

【0005】従来の半導体受光素子は、図5(A)に示す
ように、受光素子部12,受光素子のp側電極13,ノンド
−プInGaAs受光層(光吸収領域)18,その周辺部分
を含め空乏化する部分を形成する拡散領域15,電荷を外
部に取り出すための電極13aより構成されている。そし
て、図5(B)に示すように、n+型InP基板19上にノ
ンド−プInGaAs受光層(光吸収領域)18を5μm成
長させた後、Znの選択拡散を行い、受光部を形成する
拡散領域(受光領域)14及びその周辺部分を含め空乏化す
る部分を形成する拡散領域(P+領域)15が形成されてい
る。また、各受光領域14間は、境界から150μm離して
形成されている。なお、図5(B)において、16は反射防
止膜,17はn側電極である。
As shown in FIG. 5A, a conventional semiconductor light receiving element includes a light receiving element portion 12, a p-side electrode 13 of the light receiving element, a non-doped InGaAs light receiving layer (light absorbing region) 18, and a peripheral portion thereof. It is composed of a diffusion region 15 that forms a depleted portion including the electrode 13a for taking out electric charges to the outside. Then, as shown in FIG. 5B, after a non-doped InGaAs absorption layer (light absorption region) 18 is grown on the n + type InP substrate 19 by 5 μm, Zn is selectively diffused to form a light receiving portion. And a diffusion region (light receiving region) 14 and a diffusion region (P + region) 15 that forms a depleted portion including its peripheral portion. Further, the respective light receiving regions 14 are formed at a distance of 150 μm from the boundary. In FIG. 5B, 16 is an antireflection film and 17 is an n-side electrode.

【0006】[0006]

【発明が解決しようとする課題】ところで、前記従来の
半導体受光素子においては、次の第1〜第3の問題点を
有している。
By the way, the above-mentioned conventional semiconductor light receiving element has the following first to third problems.

【0007】(第1の問題点)従来の半導体受光素子で
は、クロスト−ク防止を行うために素子サイズを大きく
する必要があり、素子の小型化が困難となっていた。即
ち、第1の問題点は、従来の技術において、受光部間の
クロスト−クを防止するために数100μm離す必要があ
り、このため、素子の小型化ができないことである。そ
の理由は、受光部間に発生した少数キャリアをP+領域
下の空乏層領域で捕獲する必要があるからである。
(First Problem) In the conventional semiconductor light receiving element, it is necessary to increase the element size in order to prevent crosstalk, which makes it difficult to miniaturize the element. That is, the first problem is that in the conventional technique, it is necessary to separate them by several hundreds of μm in order to prevent crosstalk between the light receiving portions, and therefore, the element cannot be downsized. The reason is that the minority carriers generated between the light receiving portions need to be captured in the depletion layer region below the P + region.

【0008】(第2の問題点)また、集積回路の製造プ
ロセスを用いて半導体受光素子を形成することができな
いため、製造工程数を増加させることになり、生産性及
び低価格化も困難となっていた。即ち、第2の問題点
は、従来の技術において、PIN-PD構造及びP+領域
等を形成するためには、集積回路の標準製造プロセスに
よって製造できないことである。その理由は、集積回路
の特性を追求したプロセスのなかに“受光素子を考慮し
たトランジスタ,抵抗等”が存在しないからである。
(Second problem) Further, since the semiconductor light receiving element cannot be formed by using the manufacturing process of the integrated circuit, the number of manufacturing steps is increased, and it is difficult to reduce the productivity and the cost. Was becoming. That is, the second problem is that the conventional technique cannot be manufactured by the standard manufacturing process of the integrated circuit in order to form the PIN-PD structure, the P + region and the like. The reason is that there is no "transistor, resistance, etc. considering the light receiving element" in the process of pursuing the characteristics of the integrated circuit.

【0009】(第3の問題点)さらに、クロスト−ク効
果を上げるためには、一般的にP+領域の空乏層を広げ
なければならないが、このためには、高逆バイアス印加
が必要となり、その結果として、低消費電力化が困難と
なっていた。即ち、第3の問題点は、従来の技術におい
て、クロスト−ク効果を上げるためには、P+領域の空
乏層を広げなければならない。このため、数10Vの逆バ
イアス印加が必要であり、低消費電力化ができないこと
である。その理由は、集積回路の基準電圧5V程度では
空乏層の広がりが少なく、深く入射した光より発生した
少数キャリアが捕獲できないからである。
(Third Problem) Further, in order to enhance the crosstalk effect, it is generally necessary to widen the depletion layer in the P + region, but for this purpose, high reverse bias application is required. As a result, it has been difficult to reduce power consumption. That is, the third problem is that in the conventional technique, in order to improve the crosstalk effect, the depletion layer in the P + region must be widened. Therefore, it is necessary to apply a reverse bias of several tens of volts, and it is impossible to reduce the power consumption. The reason is that the depletion layer spreads little at a reference voltage of about 5 V of the integrated circuit, and minority carriers generated from deeply incident light cannot be captured.

【0010】(本発明の目的)本発明は、従来技術にお
ける上記第1〜3の問題点に鑑み成されたものであっ
て、その目的(技術的課題)とするところは、半導体基板
上に集積回路と複数個の受光素子とを隣接して形成する
受光素子内蔵集積回路装置及びその製造方法において、
複数の受光素子間のクロスト−クを防ぎ、小型化,生産
性の改善化,低価格化,低消費電力化を実現する受光素
子内蔵集積回路装置及びその製造方法を提供することに
ある。
(Object of the Invention) The present invention has been made in view of the above-mentioned first to third problems in the prior art, and the object (technical problem) is to provide a semiconductor substrate on the semiconductor substrate. In a light receiving element built-in integrated circuit device and a manufacturing method thereof, in which an integrated circuit and a plurality of light receiving elements are formed adjacently,
An object of the present invention is to provide an integrated circuit device with a built-in light receiving element that prevents crosstalk between a plurality of light receiving elements, realizes miniaturization, improvement in productivity, cost reduction, and low power consumption, and a manufacturing method thereof.

【0011】[0011]

【課題を解決するための手段】そして、本発明は、上記
目的を達成する手段として、特に、半導体基板上に集積
回路と複数個の受光素子とを隣接して形成する際に、各
受光部間及び隣接する集積回路と受光部との間を、全方
向に拡散する少数キャリアを集積回路の標準製造プロセ
スを用いて抑制しうるようにしたことを特徴とする。
The present invention provides a means for achieving the above-mentioned object, in particular, when forming an integrated circuit and a plurality of light receiving elements adjacent to each other on a semiconductor substrate, each light receiving portion is formed. The feature is that minority carriers diffused in all directions between the adjacent and adjacent integrated circuits and the light receiving section can be suppressed by using a standard manufacturing process of the integrated circuit.

【0012】即ち、本発明に係る受光素子内蔵集積回路
装置は、「集積回路を形成する第1の導電型の半導体基
板に形成された第1の導電型の高濃度領域上に、第2の
導電型の領域を形成し、該第2の導電型の領域を前記第
1の導電型の高濃度領域により複数に分割し、この際、
前記第2の導電型領域を前記第1の導電型の高濃度領域
で囲むように形成してなることを特徴とする受光素子内
蔵集積回路装置。」(請求項1)を要旨とする。
That is, the integrated circuit device with a built-in light-receiving element according to the present invention has the following features: "A second conductive type high concentration region formed on a first conductive type semiconductor substrate forming an integrated circuit; A conductive type region is formed, and the second conductive type region is divided into a plurality of regions by the first conductive type high-concentration region.
An integrated circuit device with a built-in light receiving element, wherein the second conductivity type region is formed so as to be surrounded by the first conductivity type high concentration region. (Claim 1).

【0013】また、本発明に係る受光素子内蔵集積回路
装置は、「集積回路を形成する第1の導電型の半導体基
板に形成された第1の導電型の高濃度領域上に、第2の
導電型の領域を形成し、受光領域を前記第2の導電型の
高濃度領域で分割し、前記受光領域を前記第1の導電型
の高濃度領域で形成してなることを特徴とする受光素子
内蔵集積回路装置。」(請求項2)を要旨とする。
Further, the integrated circuit device with a built-in light receiving element according to the present invention has a feature that "the second conductivity type is formed on the high-concentration region of the first conductivity type formed on the semiconductor substrate of the first conductivity type forming the integrated circuit. A light receiving region characterized by forming a conductive type region, dividing the light receiving region by the second conductivity type high concentration region, and forming the light receiving region by the first conductivity type high concentration region. An integrated circuit device with a built-in element. "(Claim 2).

【0014】さらに、本発明に係る受光素子内蔵集積回
路装置の製造方法は、「半導体基板上に集積回路と複数
個の受光素子とを隣接して形成する受光素子内蔵集積回
路装置の製造方法において、各受光部間及び隣接する集
積回路と受光部との間を、全方向に拡散する少数キャリ
アを集積回路の標準製造プロセスを用いて抑制すること
を特徴とする受光素子内蔵集積回路装置の製造方法。」
(請求項3)を要旨とする。
Further, the method for manufacturing an integrated circuit device with a built-in light receiving element according to the present invention is "a method for manufacturing an integrated circuit device with a built-in light receiving element in which an integrated circuit and a plurality of light receiving elements are formed adjacently on a semiconductor substrate. Manufacturing of an integrated circuit device with a built-in light receiving element, characterized in that minority carriers that diffuse in all directions are suppressed between each light receiving part and between an adjacent integrated circuit and a light receiving part using a standard manufacturing process of an integrated circuit. Method."
(Claim 3) is the gist.

【0015】[0015]

【発明の実施の形態】以下、本発明について詳細に説明
すると、本発明は、前記したとおり、集積回路の標準製
造プロセスを用いることにより、従来の複数の受光領域
を形成したクロスト−クを容易に解決し、小型化,低消
費電力化,生産性の向上,低価格化を意図するために成
されたものである。
BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in detail below. As described above, the present invention facilitates a conventional crosstalk having a plurality of light receiving regions by using a standard manufacturing process of an integrated circuit. It was made in order to solve the above problems and to achieve miniaturization, low power consumption, improved productivity, and low price.

【0016】そして、本発明に係る受光素子内蔵集積回
路装置は、具体的には、後に詳記するが、図1に示すよ
うに、半導体基板1上に、P+型埋込領域2aとN-型エ
ピタキシャル層3とP+型素子分離拡散領域2bとを有
するものである。また、同じく図2に示すように、N-
型エピタキシャル層3を素子分離するN+型素子分離拡
散領域7と受光部を形成するP+型光吸収拡散領域8と
を有するものである。
[0016] Then, the light-receiving element built integrated circuit device according to the present invention, specifically, will be detailed in later, as shown in FIG. 1, on a semiconductor substrate 1, P + -type buried region 2a and N It has a − type epitaxial layer 3 and a P + type element isolation diffusion region 2b. Similarly, as shown in FIG. 2, N
It has an N + type element isolation diffusion region 7 for element isolation of the type epitaxial layer 3 and a P + type light absorption diffusion region 8 for forming a light receiving portion.

【0017】[0017]

【作用】本発明の生じる作用について、上記した図1に
示す具体例により説明する。図1は、後に詳記するが、
本発明に係る“複数配列された受光部”の断面構造を示
す図であって、N-型エピタキシャル層3は、半導体基
板1上に形成され、P+型埋込領域2a及びP+型素子分
離領域2bにより囲まれるように分割して形成されてい
る。
The operation of the present invention will be described with reference to the specific example shown in FIG. 1, which will be described in detail later,
FIG. 2 is a diagram showing a cross-sectional structure of a “plurality of light receiving portions” according to the present invention, in which an N type epitaxial layer 3 is formed on a semiconductor substrate 1, and a P + type buried region 2a and a P + type element are formed. It is formed so as to be divided so as to be surrounded by the separation region 2b.

【0018】そして、このN-型エピタキシャル層3を
カソ−ド領域とし、一方、P+埋込領域2a及び接地さ
れたP+型素子分離拡散領域2bをアノ−ド領域とし、
かつP+型素子分離拡散領域2bの各幅を数μmと隣接
するように受光領域を形成することで、受光領域以外に
生成した少数キャリアの大半をP+型素子分離拡散領域
2bでホ−ルと再結合でき、受光部間におけるクロスト
−クを大幅に低減でき、しかも受光領域形成は、集積回
路の標準プロセスを利用するため、付加工程なく、低消
費電圧化ができるという作用が生じる。
The N type epitaxial layer 3 is used as a cathode region, while the P + buried region 2a and the grounded P + type element isolation diffusion region 2b are used as an anode region.
In addition, by forming the light receiving region so that each width of the P + type element isolation diffusion region 2b is adjacent to several μm, most of the minority carriers generated in the regions other than the light receiving region are stored in the P + type element isolation diffusion region 2b. And the crosstalk between the light receiving portions can be greatly reduced, and the light receiving region is formed by using the standard process of the integrated circuit. Therefore, there is an effect that the power consumption can be reduced without additional steps.

【0019】[0019]

【実施例】次に、本発明の実施例について図面を参照し
て説明するが、本発明は、以下の実施例によって限定さ
れるものではなく、前記した本発明の要旨を逸脱しない
範囲で変形,変更をすることができるものである。
EXAMPLES Examples of the present invention will now be described with reference to the drawings, but the present invention is not limited to the following examples and is modified within a range not departing from the gist of the present invention. , It is possible to make changes.

【0020】(実施例1)図1は、本発明に係る受光素
子内蔵集積回路装置の一実施例(実施例1)を示す半導体
受光素子の断面図である。
(Embodiment 1) FIG. 1 is a sectional view of a semiconductor light receiving element showing an embodiment (Embodiment 1) of an integrated circuit device with a light receiving element according to the present invention.

【0021】本実施例1に係る受光素子内蔵集積回路装
置の半導体受光素子は、3つの受光部(N-型エピタキシ
ャル層3)が半導体基板1上に形成されている。この3
つの受光部(N-型エピタキシャル層3)は、図1に示す
ように、半導体基板1上にP+型素子分離拡散領域2b
とP+埋込領域2aとにより囲まれるように分割されて
いる。そして、正の電圧が印加されたN-型エピタキシ
ャル層3をカソ−ド領域とし、一方、P+埋込領域2a
及び接地されたP+型素子分離拡散領域2bをアノ−ド
領域とし、また、P+型素子分離拡散領域2bの幅を数
μmと隣接するように形成されている。
In the semiconductor light receiving element of the integrated circuit device with a built-in light receiving element according to the first embodiment, three light receiving portions (N type epitaxial layer 3) are formed on the semiconductor substrate 1. This 3
As shown in FIG. 1, the two light receiving portions (N type epitaxial layer 3) are formed on the semiconductor substrate 1 by a P + type element isolation diffusion region 2 b.
And the P + buried region 2a. Then, a positive voltage is applied N - -type epitaxial layer 3 cathode - and de region, whereas, P + buried region 2a
The grounded P + -type element isolation diffusion region 2b is used as an anode region, and the P + -type element isolation diffusion region 2b is formed to have a width of several μm adjacent thereto.

【0022】このように形成された受光部を用い、受光
面に照射された光を光電流として各々のカソ−ド電極5
から取り出し、この半導体受光素子と同一基板上に形成
しているアンプ回路6を通して光強度を検出する。な
お、図1中の4は、N+型電極引出拡散領域であり、9
は反射防止膜である。
Using the light-receiving portion thus formed, the light radiated on the light-receiving surface is used as a photocurrent for each cathode electrode 5.
Then, the light intensity is detected through an amplifier circuit 6 formed on the same substrate as this semiconductor light receiving element. Reference numeral 4 in FIG. 1 denotes an N + -type electrode extraction diffusion region, and 9
Is an antireflection film.

【0023】CD用ピックアップでは、後段の制御回路
に電圧入力する必要があり、電流−電圧変換アンプ回路
を用いる。
In the CD pickup, it is necessary to input a voltage to the control circuit at the subsequent stage, and a current-voltage conversion amplifier circuit is used.

【0024】この実施例1の受光素子内蔵集積回路装置
の特徴点は、集積回路に用いられているトランジスタ形
成の標準プロセスを利用し、N-型エピタキシャル層3
を分割すると共に、 各々の受光部のアノ−ド領域とな
る各々のP+型素子分離拡散領域2b及び2μm程度の
+型埋込領域2aを拡散により、他のトランジスタを
形成した時に同時に形成できる点にある。即ち、集積回
路に用いられている標準プロセスに付加工程を追加する
ことなく、半導体受光素子を同一基板の集積回路内に形
成することができる。
A feature of the integrated circuit device with a built-in light receiving element of the first embodiment is that the standard process for forming a transistor used in an integrated circuit is utilized and the N -- type epitaxial layer 3 is used.
Is formed at the same time when other transistors are formed by diffusing each P + -type element isolation diffusion region 2b to be an anode region of each light-receiving section and the P + -type buried region 2a of about 2 μm. There is a point that can be done. That is, the semiconductor light receiving element can be formed in the integrated circuit on the same substrate without adding an additional step to the standard process used for the integrated circuit.

【0025】ここで、本実施例1の上記半導体受光素子
の製造方法について説明すると、まず、各々のP+型埋
込領域2aを半導体基板1中に形成した後、N-型エピ
タキシャル層3を成長させ、次に、P+型素子分離領域
2bを拡散し、これによりN-型エピタキシャル層3を
分割する。
The method for manufacturing the semiconductor light receiving element of the first embodiment will now be described. First, after each P + type buried region 2a is formed in the semiconductor substrate 1, the N type epitaxial layer 3 is formed. After growing, the P + type element isolation region 2b is diffused, thereby dividing the N type epitaxial layer 3.

【0026】そして、各々分割されたN-型エピタキシ
ャル層3にカソ−ド電極(配線)5を接続するため、N+
型電極引出拡散領域4を形成した後、反射防止膜9を形
成し、次に、この反射防止膜9にカソ−ド電極5結線用
のコンタクト・ホ−ルを形成し、カソ−ド電極(配線)5
を形成して、図1に示す受光素子内蔵集積回路装置の半
導体受光素子を製造する。
Then, in order to connect the cathode electrode (wiring) 5 to each divided N type epitaxial layer 3, N +
After forming the die electrode lead-out diffusion region 4, an antireflection film 9 is formed, and then a contact hole for connecting the cathode electrode 5 is formed on the antireflection film 9 to form the cathode electrode ( Wiring) 5
Are formed to manufacture the semiconductor light receiving element of the integrated circuit device with a built-in light receiving element shown in FIG.

【0027】以上説明した本実施例1の受光素子内蔵集
積回路装置において、受光部に光が照射され、光吸収に
よるキャリアホ−ル対の生成箇所がP+埋込領域2aの
下部でおこる際、少数キャリアは、拡散により全方向へ
移動することになる。この全方向に移動した電子は、P
+型埋込領域2a及びP+型素子分離拡散領域2bに達
し、その大半のキャリアはホ−ルと再結合することにな
る。
In the integrated circuit device with a built-in light receiving element according to the first embodiment described above, when the light receiving portion is irradiated with light and the generation of the carrier hole pair due to light absorption occurs below the P + buried region 2a. , Minority carriers will move in all directions due to diffusion. The electrons moving in all directions are P
Reaching the + type buried region 2a and the P + type element isolation diffusion region 2b, most of the carriers will be recombined with the holes.

【0028】この光吸収によるキャリアホ−ル対の生成
箇所は、半導体素子の材質及び照射される光の波長によ
っても異なる。このため、半導体受光素子は、P+埋込
領域2aの下部で生成されたキャリアによる光電流を発
生することはない。従って、本実施例1の受光素子内蔵
集積回路装置では、受光部間におけるクロスト−クが大
幅に低減できることとなる。
The location where the carrier hole pair is generated by this light absorption varies depending on the material of the semiconductor element and the wavelength of the irradiated light. Therefore, the semiconductor light receiving element does not generate a photocurrent due to the carriers generated below the P + buried region 2a. Therefore, in the integrated circuit device with a built-in light receiving element of the first embodiment, the crosstalk between the light receiving portions can be greatly reduced.

【0029】(実施例2)図2は、本発明に係る受光素
子内蔵集積回路装置の他の実施例(実施例2)を示す半導
体受光素子の断面図である。図2において、7はN+
素子分離拡散領域であり、8はP+型光吸収拡散領域で
ある。その他の符号1,3,5,6は、前掲の図1と同
一である。
(Embodiment 2) FIG. 2 is a sectional view of a semiconductor light receiving element showing another embodiment (embodiment 2) of an integrated circuit device with a light receiving element according to the present invention. In FIG. 2, 7 is an N + type element isolation diffusion region, and 8 is a P + type light absorption diffusion region. Other reference numerals 1, 3, 5 and 6 are the same as those in FIG. 1 described above.

【0030】本実施例2に係る受光素子内蔵集積回路装
置の半導体受光素子では、CDからDVDへの記録密度
増加に伴い、発光源の波長も短波長側に向かっている。
光吸収によるキャリアホ−ルの生成箇所は、照射される
光の波長が短くなると狭くなる。本実施例2は、この作
用を利用した半導体受光素子であり、図2に示す「CD
等に用いる受光素子内蔵集積回路装置の半導体受光素
子」である。
In the semiconductor light receiving element of the integrated circuit device with a built-in light receiving element according to the second embodiment, the wavelength of the light emitting source is moving toward the short wavelength side as the recording density from CD to DVD increases.
The location where the carrier holes are generated by light absorption becomes narrower as the wavelength of the irradiated light becomes shorter. The second embodiment is a semiconductor light receiving element that utilizes this effect, and the "CD
The semiconductor light receiving element of the integrated circuit device with a built-in light receiving element used for the above.

【0031】この実施例2の特徴点は、前記実施例1と
同様、集積回路に用いられるトランジスタ形成の標準プ
ロセスを利用する点にあり、これにより、集積回路に用
いられている標準プロセスに付加工程を追加することな
く、半導体受光素子を同一基板の集積回路内に形成する
ことができる。
The feature of the second embodiment is that the standard process for forming a transistor used in an integrated circuit is used as in the case of the first embodiment, and thus the standard process used in the integrated circuit is added. The semiconductor light receiving element can be formed in an integrated circuit on the same substrate without adding steps.

【0032】本実施例2の図2に示す半導体受光素子の
製造方法について説明すると、まず、半導体基板1の上
部にN-型エピタキシャル層3を薄く形成し、続いて、
受光領域以外に生成される少数キャリアを捕獲するた
め、かつカソ−ド電極5を接続するため、N+型素子分
離拡散領域7を形成する。次に、受光領域及びアノ−ド
電極を接続するためのP+型光吸収拡散領域8を形成
し、反射防止膜9を形成した後、この反射防止膜9にア
ノ−ド電極用のコンタクトホールを形成し、アノ−ド電
極用の配線5aを形成して、図2に示す受光素子内蔵集
積回路装置の半導体受光素子を製造する。
The method of manufacturing the semiconductor light receiving element shown in FIG. 2 of the second embodiment will be described. First, the N type epitaxial layer 3 is thinly formed on the semiconductor substrate 1, and then,
An N + type element isolation diffusion region 7 is formed in order to capture minority carriers generated outside the light receiving region and to connect the cathode electrode 5. Next, a P + type light absorption / diffusion region 8 for connecting the light receiving region and the anode electrode is formed, an antireflection film 9 is formed, and then a contact hole for the anode electrode is formed in the antireflection film 9. And the wiring 5a for the anode electrode is formed to manufacture the semiconductor light receiving element of the integrated circuit device with a built-in light receiving element shown in FIG.

【0033】(実施例3)図3は、本発明に係る受光素
子内蔵集積回路装置をCD等に用いた一実施例(実施例
3)を示す平面図である。
(Embodiment 3) FIG. 3 is a plan view showing an embodiment (Embodiment 3) in which the integrated circuit device with a built-in light receiving element according to the present invention is used for a CD or the like.

【0034】本実施例3では、図3に示すような構成か
らなり、各受光素子部11と集積回路部6aは、アルミ配
線等で結線されている。また、集積回路部6aと受光素
子部11とは、素子分離領域(受光素子部と回路部の分離
拡散領域)10で分離され、また、受光素子部11以外はア
ルミ等により遮光されている。このため、受光素子部11
に照射された光は、集積回路部6aに影響することはな
い利点を有する。なお、図4は、図3に示す実施例3の
受光素子内蔵集積回路装置において、その図3のA−A
間を測定した出力電圧の素子表面内分布図である。
In the third embodiment, the light receiving element portion 11 and the integrated circuit portion 6a have the structure shown in FIG. 3, and are connected by aluminum wiring or the like. Further, the integrated circuit portion 6a and the light receiving element portion 11 are separated by an element isolation region (separation diffusion region of the light receiving element portion and the circuit portion) 10, and the portion other than the light receiving element portion 11 is shielded by aluminum or the like. Therefore, the light receiving element section 11
The light radiated on the light has an advantage that it does not affect the integrated circuit portion 6a. It should be noted that FIG. 4 shows the integrated circuit device with a built-in light receiving element of the third embodiment shown in FIG.
It is an element surface distribution diagram of the output voltage which measured the space.

【0035】[0035]

【発明の効果】本発明は、以上詳記したとおり、集積回
路の標準製造プロセスを用いるため、受光素子の素子分
離が容易にでき、素子の小型化ができる効果が生じる。
また、付加工程もなく、生産性の向上を図ることができ
る。その理由は、半導体基板に同一の導電型の高濃度領
域を埋め込み、受光素子の分離を同一導電型の高濃度領
域を拡散することで、トランジスタ形成と同時に形成で
きるからである。
As described in detail above, the present invention uses the standard manufacturing process of an integrated circuit, so that the elements of the light receiving element can be easily separated and the elements can be miniaturized.
In addition, productivity can be improved without additional steps. The reason is that a high-concentration region of the same conductivity type is embedded in the semiconductor substrate, and the light-receiving element can be separated at the same time as the transistor is formed by diffusing the high-concentration region of the same conductivity type.

【0036】また、本発明は、受光領域での空乏層領域
を広くしなくても感度が取れ、低電圧化(即ち低消費電
圧化)ができる効果が生じる。その理由は、受光領域を
薄いエピタキシャル成長で形成するからである。
Further, according to the present invention, the sensitivity can be obtained without widening the depletion layer region in the light receiving region, and the voltage can be lowered (that is, the consumption voltage can be reduced). The reason is that the light receiving region is formed by thin epitaxial growth.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る受光素子内蔵集積回路装置の一実
施例(実施例1)を示す半導体受光素子の断面図。
FIG. 1 is a sectional view of a semiconductor light receiving element showing an embodiment (Example 1) of an integrated circuit device with a light receiving element according to the present invention.

【図2】本発明に係る受光素子内蔵集積回路装置の他の
実施例(実施例2)を示す半導体受光素子の断面図。
FIG. 2 is a sectional view of a semiconductor light receiving element showing another embodiment (embodiment 2) of an integrated circuit device with a light receiving element according to the present invention.

【図3】本発明に係る受光素子内蔵集積回路装置をCD
等に用いた一実施例(実施例3)を示す平面図。
FIG. 3 is a diagram showing the integrated circuit device with a built-in light receiving element according to the present invention as a CD.
The top view which shows one Example (Example 3) used for the etc.

【図4】図3に示す実施例3の受光素子内蔵集積回路装
置において、図3のA−A間を測定した出力電圧の素子
表面内分布図。
4 is an element surface distribution diagram of the output voltage measured between AA in FIG. 3 in the integrated circuit device with a built-in light receiving element of Example 3 shown in FIG. 3;

【図5】従来の半導体受光素子を説明する図であって、
(A)はその平面図であり、(B)は(A)のX−X線断面
図。
FIG. 5 is a diagram illustrating a conventional semiconductor light receiving element,
(A) is the top view, (B) is the XX sectional view taken on the line of (A).

【符号の説明】[Explanation of symbols]

1 半導体基板 2a P+型埋込領域 2b P+型素子分離拡散領域 3 N-型エピタキシャル層 4 N+型電極引出拡散領域 5 カソ−ド電極 5a 配線 6 アンプ回路 6a 集積回路部 7 N+型素子分離拡散領域 8 P+型光吸収拡散領域 9 反射防止膜 10 受光素子部と回路部の分離拡散領域 11 受光素子部 12 受光素子部 13 受光素子のp側電極 13a 電極 14 受光部を形成する拡散領域 15 周辺部分を含め空乏化する部分を形成する拡散領
域 16 反射防止膜 17 n側電極 18 ノンド−プInGaAs受光層(光吸収領域) 19 n+型InP基板
1 Semiconductor Substrate 2a P + Type Embedded Region 2b P + Type Element Isolation Diffusion Region 3 N - Type Epitaxial Layer 4 N + Type Electrode Extraction Diffusion Region 5 Cathode Electrode 5a Wiring 6 Amplifier Circuit 6a Integrated Circuit Section 7 N + Type Element isolation diffusion region 8 P + type light absorption diffusion region 9 Antireflection film 10 Separation diffusion region of light receiving element portion and circuit portion 11 Light receiving element portion 12 Light receiving element portion 13 P-side electrode 13a electrode of light receiving element 14 Forming light receiving portion Diffusion region 15 Diffusion region forming depletion region including peripheral part 16 Antireflection film 17 n-side electrode 18 Non-doped InGaAs absorption layer (light absorption region) 19 n + type InP substrate

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 集積回路を形成する第1の導電型の半導
体基板に形成された第1の導電型の高濃度領域上に、第
2の導電型の領域を形成し、該第2の導電型の領域を前
記第1の導電型の高濃度領域により複数に分割し、この
際、前記第2の導電型領域を前記第1の導電型の高濃度
領域で囲むように形成してなることを特徴とする受光素
子内蔵集積回路装置。
1. A second conductivity type region is formed on a high concentration region of the first conductivity type formed on a semiconductor substrate of the first conductivity type forming an integrated circuit, and the second conductivity type region is formed. A high-concentration region of the first conductivity type is divided into a plurality of regions, and the second-conductivity type region is surrounded by the high-concentration region of the first conductivity type. An integrated circuit device with a built-in light-receiving element.
【請求項2】 集積回路を形成する第1の導電型の半導
体基板に形成された第1の導電型の高濃度領域上に、第
2の導電型の領域を形成し、受光領域を前記第2の導電
型の高濃度領域で分割し、前記受光領域を前記第1の導
電型の高濃度領域で形成してなることを特徴とする受光
素子内蔵集積回路装置。
2. A region of the second conductivity type is formed on a high-concentration region of the first conductivity type formed on a semiconductor substrate of the first conductivity type forming an integrated circuit, and a light receiving region is formed in the first light receiving region. 2. An integrated circuit device with a built-in light-receiving element, characterized in that the light-receiving region is divided into two high-concentration regions of conductivity type, and the light-receiving region is formed by the high-concentration region of the first conductivity type.
【請求項3】 半導体基板上に集積回路と複数個の受光
素子とを隣接して形成する受光素子内蔵集積回路装置の
製造方法において、各受光部間及び隣接する集積回路と
受光部との間を、全方向に拡散する少数キャリアを集積
回路の標準製造プロセスを用いて抑制することを特徴と
する受光素子内蔵集積回路装置の製造方法。
3. A method for manufacturing an integrated circuit device with a built-in light receiving element, wherein an integrated circuit and a plurality of light receiving elements are formed adjacent to each other on a semiconductor substrate, and between the light receiving sections and between the adjacent integrated circuits and the light receiving sections. The method for manufacturing an integrated circuit device with a built-in light-receiving element is characterized in that the minority carriers diffused in all directions are suppressed by using a standard manufacturing process of the integrated circuit.
JP8109274A 1996-04-30 1996-04-30 Integrated circuit device with built-in light receiving element Expired - Fee Related JP2882354B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8109274A JP2882354B2 (en) 1996-04-30 1996-04-30 Integrated circuit device with built-in light receiving element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8109274A JP2882354B2 (en) 1996-04-30 1996-04-30 Integrated circuit device with built-in light receiving element

Publications (2)

Publication Number Publication Date
JPH09298285A true JPH09298285A (en) 1997-11-18
JP2882354B2 JP2882354B2 (en) 1999-04-12

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ID=14506021

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Country Status (1)

Country Link
JP (1) JP2882354B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6462328B2 (en) 2000-08-08 2002-10-08 Denso Corporation Photo-detection sensor and method of manufacturing the same
JP2007521657A (en) * 2003-06-25 2007-08-02 セミコア Structure and manufacturing method of ultra-thin backside illuminated photodiode array
JPWO2011089949A1 (en) * 2010-01-25 2013-05-23 アイアールスペック株式会社 Compound semiconductor photo detector array

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63160270A (en) * 1986-12-23 1988-07-04 Nikon Corp Semiconductor device having photosensor and signal processing element
JPS6439658U (en) * 1987-09-02 1989-03-09
JPH07183563A (en) * 1993-12-21 1995-07-21 Sony Corp Semiconductor device
JPH0818093A (en) * 1994-06-30 1996-01-19 Sony Corp Semiconductor photoreceiver and semiconductor device and manufacture thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63160270A (en) * 1986-12-23 1988-07-04 Nikon Corp Semiconductor device having photosensor and signal processing element
JPS6439658U (en) * 1987-09-02 1989-03-09
JPH07183563A (en) * 1993-12-21 1995-07-21 Sony Corp Semiconductor device
JPH0818093A (en) * 1994-06-30 1996-01-19 Sony Corp Semiconductor photoreceiver and semiconductor device and manufacture thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6462328B2 (en) 2000-08-08 2002-10-08 Denso Corporation Photo-detection sensor and method of manufacturing the same
JP2007521657A (en) * 2003-06-25 2007-08-02 セミコア Structure and manufacturing method of ultra-thin backside illuminated photodiode array
JPWO2011089949A1 (en) * 2010-01-25 2013-05-23 アイアールスペック株式会社 Compound semiconductor photo detector array
JP5942068B2 (en) * 2010-01-25 2016-06-29 アイアールスペック株式会社 Compound semiconductor photo detector array

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