JPH09298168A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH09298168A JPH09298168A JP11229396A JP11229396A JPH09298168A JP H09298168 A JPH09298168 A JP H09298168A JP 11229396 A JP11229396 A JP 11229396A JP 11229396 A JP11229396 A JP 11229396A JP H09298168 A JPH09298168 A JP H09298168A
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- Prior art keywords
- semiconductor
- semiconductor device
- manufacturing
- aqueous solution
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- Drying Of Semiconductors (AREA)
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- Junction Field-Effect Transistors (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は半導体装置およびそ
の製造方法に関する。The present invention relates to a semiconductor device and a method for manufacturing the same.
【0002】[0002]
【従来の技術】近年、半導体素子の性能を向上させるた
めに、InP基板上にInxAl1-xAs(0<x<1、
以下InAlAsと記す)やInyGa1-yAs(0<y
<1、以下InGaAsと記す)などの材料を用いた素
子の研究開発が盛んである。これらの素子の研究開発は
主にミリ波周波数帯(30GHz−300GHz)利用
システムの基本デバイスをはじめとするすぐれた特性を
もつ半導体装置の作製を目的としている。2. Description of the Related Art In recent years, in order to improve the performance of semiconductor devices, InxAl1-xAs (0 <x <1,
Hereinafter referred to as InAlAs) and InyGa1-yAs (0 <y
<1. In the following, referred to as InGaAs), the research and development of devices using materials such as InGaAs are active. The purpose of research and development of these elements is mainly to manufacture semiconductor devices having excellent characteristics such as basic devices of millimeter wave frequency band (30 GHz-300 GHz) utilization systems.
【0003】半導体素子の性能ばらつきを低減するため
には、半導体層の所望の深さまでの除去を行なう高精度
の半導体加工を行なう必要があるが、そのような半導体
加工技術としてInGaAsを被エッチング層としてI
nAlAsをエッチング停止層とする選択エッチング技
術があり、クエン酸水溶液を用いた選択エッチング技術
がイリノイ大学のTongらによって報告されている(T
ong, et al., IEEE Electron Device Lett., Vol.13, N
o.10, 1992, pp.525-527)。In order to reduce variations in the performance of semiconductor elements, it is necessary to perform highly accurate semiconductor processing for removing the semiconductor layer to a desired depth. As such a semiconductor processing technique, InGaAs is used as a layer to be etched. As I
There is a selective etching technique using nAlAs as an etching stop layer, and a selective etching technique using an aqueous citric acid solution has been reported by Tong et al. at the University of Illinois (T.
ong, et al., IEEE Electron Device Lett., Vol.13, N
o.10, 1992, pp.525-527).
【0004】[0004]
【発明が解決しようとする課題】しかしながら、クエン
酸水溶液を用いた前述の選択エッチング技術によって作
製した電界効果トランジスタ(FET:Field Effect T
ransistor)の電気的特性の一つであるゲート特性が不
良となる問題があった。However, a field effect transistor (FET) manufactured by the above-described selective etching technique using an aqueous citric acid solution.
There is a problem that the gate characteristics, which is one of the electrical characteristics of ransistor), become defective.
【0005】本発明の目的は、ゲート特性の良好なFE
Tを有する半導体装置およびその製造方法を提供するこ
とにある。An object of the present invention is to provide an FE having good gate characteristics.
A semiconductor device having T and a method of manufacturing the same are provided.
【0006】[0006]
【課題を解決するための手段】前記目的は半導体装置の
作製プロセスに、半導体膜が表面上に形成された試料の
半導体膜をその表面からエッチングするエッチング工程
と、その工程に次いでN−H結合を有する化合物の塩基
性水溶液により試料を浸淅する工程と、ゲート電極とな
る金属膜を被着する工程とを含めることにより達成でき
る。The object is to perform a semiconductor device manufacturing process, an etching step of etching a semiconductor film of a sample having a semiconductor film formed on the surface from the surface, and an N--H bond next to the etching step. This can be achieved by including a step of immersing the sample in a basic aqueous solution of the compound having the above and a step of depositing a metal film to be a gate electrode.
【0007】本発明の方法により、ゲート電極となる導
電性材料領域とそのゲート電極となる導電性材料に接す
る半導体材料領域との接触界面からチャネル層となる半
導体材料領域端部までの間にAlを含む半導体膜が存在
して、チャネル層となる半導体材料がGaを含み、ゲー
ト電極となる導電性材料領域とゲート電極となる導電性
材料領域に接する半導体材料領域との接触界面からチャ
ネル層となる半導体材料領域端部までの距離が40nm
以下であるような新規な構造のFETを有する半導体装
置を実現できる。According to the method of the present invention, Al is provided between the contact interface between the conductive material region serving as the gate electrode and the semiconductor material region in contact with the conductive material serving as the gate electrode and the end portion of the semiconductor material region serving as the channel layer. And a semiconductor film containing Ga is contained in the semiconductor material serving as the channel layer, and the channel layer is formed from the contact interface between the conductive material region serving as the gate electrode and the semiconductor material region contacting the conductive material region serving as the gate electrode. Distance to the edge of the semiconductor material region is 40 nm
It is possible to realize a semiconductor device having a FET having a novel structure as described below.
【0008】[0008]
実施例1 本発明に係る半導体装置の製造方法の一実施例について
図1ないし3を用いて説明する。図1ないし3は本発明
に係る半導体装置の製造方法を用いてInAlAs/I
nGaAs HEMT(High Electron
Mobility Transistor)のゲートリ
セスを作製するための工程図である。Example 1 An example of a method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 1 to 3 show InAlAs / I using the method for manufacturing a semiconductor device according to the present invention.
nGaAs HEMT (High Electron
FIG. 7 is a process diagram for manufacturing a gate recess of a Mobility Transistor.
【0009】本実施例のHEMT作製プロセスにおいて
図1に示す工程に至るまでの作製工程を以下に記載す
る。The manufacturing steps up to the step shown in FIG. 1 in the HEMT manufacturing process of this embodiment will be described below.
【0010】半絶縁性InP基板1の一主面に、MBE
(Molecular BeamEpitaxy)法に
より、バッファ層となるノンドープInAlAs層2、
チャネル層となるノンドープInGaAs層3、スペー
サ層となるノンドープInAlAs層4(2nm)、キ
ャリア供給層となるn型InAlAs層5(12nm、
n型キャリアを供給する不純物Si濃度5×1018cm
~2)、バリア層となるノンドープInAlAs層6(1
0nm)、オーミック層となるn型InGaAs層7
(100nm)を半絶縁性InP基板1側から順次成長
させた。ここで、InAlAs層のIn組成比xおよび
InGaAsのIn組成比yは、InP基板に格子整合
するようにそれぞれx=0.52およびy=0.53とし
た。次いで、通常のホトリソグラフィ技術と通常のウェ
ットエッチング技術を用いてHEMT作製領域以外の部
分に、表面から少なくともバッファ層となるノンドープ
InAlAs層2に到達する溝を形成した(図示せ
ず)。次いで、絶縁膜8を堆積させ、通常のホトリソグ
ラフィ技術と通常のドライエッチング法によりソース電
極とドレイン電極を形成する部分を開口し、ソース電極
9とドレイン電極10を形成した。ここで絶縁膜8とし
ては酸化珪素SiO2を用いたが、他の物質、たとえば
窒化珪素SiNxとしてもよいし、複数の絶縁物質の積
層構造としてもよい。次いで、通常のホトリソグラフィ
技術と通常のドライエッチング法によりゲート長にあた
る開口11を絶縁膜8に形成した。以上の工程を経たも
のの断面図が図1である。図1における絶縁膜8上には
前述のホトリソグラフィ工程で用いたホトレジスト膜が
被着されたままとなっているが、ホトレジスト膜は省略
した。MBE is formed on one main surface of the semi-insulating InP substrate 1.
(Molecular Beam Epitaxy) method, a non-doped InAlAs layer 2 serving as a buffer layer,
Non-doped InGaAs layer 3 which becomes a channel layer, non-doped InAlAs layer 4 (2 nm) which becomes a spacer layer, n-type InAlAs layer 5 (12 nm, which becomes a carrier supply layer)
Impurity Si concentration for supplying n-type carriers 5 × 10 18 cm
~ 2 ), a non-doped InAlAs layer 6 (1
0 nm), n-type InGaAs layer 7 serving as an ohmic layer
(100 nm) was sequentially grown from the semi-insulating InP substrate 1 side. Here, the In composition ratio x of the InAlAs layer and the In composition ratio y of InGaAs were set to x = 0.52 and y = 0.53 so as to be lattice-matched to the InP substrate. Then, using a normal photolithography technique and a normal wet etching technique, a groove reaching from the surface to at least the non-doped InAlAs layer 2 serving as a buffer layer was formed in a portion other than the HEMT fabrication region (not shown). Next, the insulating film 8 was deposited, and the portions for forming the source electrode and the drain electrode were opened by the ordinary photolithography technique and the ordinary dry etching method to form the source electrode 9 and the drain electrode 10. Although silicon oxide SiO2 is used as the insulating film 8 here, other materials such as silicon nitride SiNx may be used, or a laminated structure of a plurality of insulating materials may be used. Next, the opening 11 corresponding to the gate length was formed in the insulating film 8 by the normal photolithography technique and the normal dry etching method. FIG. 1 is a cross-sectional view of what has undergone the above steps. Although the photoresist film used in the above-mentioned photolithography process is still deposited on the insulating film 8 in FIG. 1, the photoresist film is omitted.
【0011】そしてクエン酸:過酸化水素(30%):
水=1:1:1(重量)溶液を用いてオーミック層とな
るn型InGaAs層7をエッチング除去し、バリア層
となるノンドープInAlAs層6を露出させた(図
2)。次いで、純水洗浄、乾燥後、アンモニア処理(ア
ンモニア水溶液(アンモニア水溶液(29%):水=
1:100(体積))に浸淅した後、純水洗浄)を行な
った。And citric acid: hydrogen peroxide (30%):
The n-type InGaAs layer 7 serving as the ohmic layer was removed by etching using a water = 1: 1: 1 (weight) solution to expose the non-doped InAlAs layer 6 serving as the barrier layer (FIG. 2). Then, after washing with pure water and drying, an ammonia treatment (aqueous ammonia solution (aqueous ammonia solution (29%): water =
After immersing in 1: 100 (volume), washing with pure water) was performed.
【0012】次いで、ゲート電極を形成してHEMTを
完成させた(図3)。電極形成法には通常のリフトオフ
法を用いた。Then, a gate electrode was formed to complete the HEMT (FIG. 3). The usual lift-off method was used for the electrode formation method.
【0013】本実施例のHEMT作製プロセスを用いて
作製したHEMTのゲート特性を図4の特性線401に
示す。また本実施例のHEMT作製プロセスにおいて前
述のアンモニア処理を行なわずに作製したHEMTのゲ
ート特性を図4の特性線402に示す。ゲート特性はソ
ース電圧を0Vとして、ゲート電圧Vgsを変化させな
がら、ゲート電流Igsの絶対値を測定した。ゲート電
圧0V〜0.4Vから求めた理想因子nと実効ビルトイ
ンポテンシャルΦBは、特性線401でn=約1.2、
ΦB=約0.50eV、特性線402でn=約1.4、
ΦB=約0.33eVとなり、理想因子nは特性線40
1のほうが約0.2改善されている。また特性線402
と比較して特性線401のほうがΦBにして約0.17
eV改善されている。ゲート電圧−3Vにおけるゲート
電流の絶対値は特性線401で約1.6A/cm2、特
性線402で約200A/cm2となり、特性線402
と比較して特性線401のほうが約2桁漏れ電流が少な
くなった。ゲート特性はゲート電圧の正側負側ともに特
性線402と比較して特性線401のほうが改善されて
いる。これはHEMT作製プロセスにおいて前述のよう
なアンモニア処理を行なったためであり、換言するとア
ンモニア処理を行なうことはゲート特性を改善する効果
がある。The gate characteristic of the HEMT manufactured by using the HEMT manufacturing process of this embodiment is shown by a characteristic line 401 in FIG. Further, the gate characteristic of the HEMT manufactured without performing the above-mentioned ammonia treatment in the HEMT manufacturing process of this embodiment is shown by a characteristic line 402 in FIG. Regarding the gate characteristics, the absolute value of the gate current Igs was measured while the source voltage was 0 V and the gate voltage Vgs was changed. The ideal factor n and the effective built-in potential ΦB obtained from the gate voltage 0V to 0.4V are as follows.
ΦB = about 0.50 eV, n = about 1.4 on the characteristic line 402,
ΦB = 0.33 eV, and the ideal factor n is the characteristic line 40.
1 is improved by about 0.2. The characteristic line 402
ΦB of characteristic line 401 is about 0.17
eV has been improved. The absolute value of the gate current at a gate voltage of −3 V is about 1.6 A / cm 2 on the characteristic line 401 and about 200 A / cm 2 on the characteristic line 402.
The characteristic line 401 has a smaller leakage current by about two digits than Regarding the gate characteristics, the characteristic line 401 is improved as compared with the characteristic line 402 on both the positive side and the negative side of the gate voltage. This is because the above-described ammonia treatment was performed in the HEMT manufacturing process. In other words, performing the ammonia treatment has an effect of improving the gate characteristics.
【0014】また、本実施例では、ゲート電極12とバ
リア層となるノンドープInAlAs層6との界面から
チャネル層となるノンドープInGaAs層3までの厚
さを、24nmと薄層化した仕様の半導体層構造を用い
る。したがって、本発明のアンモニア処理は、薄層化を
進めた仕様のHEMTの作製にも効果的であることがわ
かる。すなわち、本発明のアンモニア処理は、半導体層
をほとんどエッチングしないプロセスである為、薄層化
した仕様でも、しきい値電圧Vthの変化がなく、HE
MTを高精度に歩留良く作製できる。エッチングがしき
い値電圧Vthに与える影響の大きいことは、例えば、
ノンドープInAlAsバリア層6の厚みを、プロセス
マージンを増加させるために、本実施例の10nmから
26nmに厚くした場合でも、バリア層6が1nmだけ
設計値よりも多く削れるだけで、HEMTのしきい値電
圧Vthは約100mVも変化してしまうことからわか
る。Further, in this embodiment, the thickness of the semiconductor layer having a specification that the thickness from the interface between the gate electrode 12 and the non-doped InAlAs layer 6 serving as the barrier layer to the non-doped InGaAs layer 3 serving as the channel layer is reduced to 24 nm. Use structure. Therefore, it can be seen that the ammonia treatment of the present invention is effective for the production of HEMT having the specifications of advanced thinning. That is, since the ammonia treatment of the present invention is a process in which the semiconductor layer is hardly etched, the threshold voltage Vth does not change even in the thinned specification, and the HE treatment is not performed.
MT can be manufactured with high accuracy and high yield. The large influence of etching on the threshold voltage Vth is, for example,
Even when the thickness of the non-doped InAlAs barrier layer 6 is increased from 10 nm in this embodiment to 26 nm in order to increase the process margin, the barrier layer 6 is scraped by 1 nm more than the designed value, and the HEMT threshold value is reduced. It can be seen that the voltage Vth changes by about 100 mV.
【0015】本発明のアンモニア処理の薄層化での利点
は、換言すれば、ゲート電極12とバリア層6との界面
からチャネル層3までの距離が40nm以下の新規なH
EMTの実現を可能にした。また、ミリ波周波数帯(3
0GHz−300GHz)利用システムの基本デバイス
となるHEMTに使用可能である、ゲート電極12とバ
リア層6との界面からチャネル層3までの距離が24n
m以下である新規なHEMTの実現を可能にした。In other words, the advantage of the present invention in reducing the thickness of the ammonia treatment is that the distance from the interface between the gate electrode 12 and the barrier layer 6 to the channel layer 3 is 40 nm or less.
Realized EMT. In addition, the millimeter wave frequency band (3
0 GHz-300 GHz) The distance from the interface between the gate electrode 12 and the barrier layer 6 to the channel layer 3 which can be used for HEMT which is a basic device of the system is 24 n.
It has made it possible to realize a new HEMT that is less than m.
【0016】本実施例においてはHEMTのゲート電極
形成の際にアンモニア処理を行なったが、HEMT以外
の半導体素子、例えばMESFET(MEtal Se
miconductor FET)などについても同様
の効果が得られる。In the present embodiment, the ammonia treatment is carried out when forming the gate electrode of the HEMT, but a semiconductor element other than HEMT, for example, MESFET (MEtal Se) is used.
The same effect can be obtained for a micro field effect transistor (FET).
【0017】本実施例においてはオーミック層となるn
型InGaAs層7のエッチングを有機酸の一種である
クエン酸を用いて行なったが、他の種類の有機酸を用い
た場合でも、無機酸を用いた場合でも、ゲート特性の改
善効果が同様に得られる。In this embodiment, the ohmic layer n
The type InGaAs layer 7 was etched using citric acid, which is a kind of organic acid. However, the effect of improving the gate characteristics is the same when other types of organic acids or inorganic acids are used. can get.
【0018】また本実施例において用いたアンモニア水
溶液は前述の仕様に希釈したものを用いたが、前述の仕
様に限定されるものではない。The aqueous ammonia solution used in this example was diluted to the above-mentioned specifications, but it is not limited to the above-mentioned specifications.
【0019】さらに本実施例に用いたアンモニアの替わ
りに、N−H結合を有する化合物の塩基性溶液を用いて
も同様の効果がある。Further, the same effect can be obtained by using a basic solution of a compound having an NH bond instead of the ammonia used in this example.
【0020】さらに本実施例ではチャネル層をInGa
As、スペーサ層、キャリア供給層、バリア層をInA
lAsで作製したが、このInGaAsとInAlAs
の組合せを例えばInGaAsとAlGaAsの組合せ
やGaAsとAlGaAsの組合せやGaAsSbとA
lGaAsの組合せなどのように材料を変えても本発明
の主旨から逸脱しないことはいうまでもない。Further, in this embodiment, the channel layer is made of InGa.
AsA, spacer layer, carrier supply layer, and barrier layer are made of InA.
It was made of InAs, but this InGaAs and InAlAs
For example, a combination of InGaAs and AlGaAs, a combination of GaAs and AlGaAs, and a combination of GaAsSb and A
It goes without saying that changing the material such as the combination of 1 GaAs does not depart from the gist of the present invention.
【0021】実施例2 本発明に係る半導体装置の製造方法の別の実施例につい
て説明する。本実施例についても実施例1と同じく図1
ないし3を用いて説明する。前述のように図1ないし3
は本発明に係る半導体装置の製造方法を用いてInAl
As/InGaAs HEMT(High Elect
ron Mobility Transistor)の
ゲートリセスを作製するための工程図である。Embodiment 2 Another embodiment of the method of manufacturing a semiconductor device according to the present invention will be described. This embodiment is also shown in FIG.
The description will be made with reference to Nos. 3 to 3. As described above, FIGS.
Is manufactured using the method for manufacturing a semiconductor device according to the present invention.
As / InGaAs HEMT (High Elect
FIG. 6 is a process diagram for producing a gate recess of a ron Mobility Transistor).
【0022】本実施例のHEMT作製プロセスにおいて
図1に示す工程に至るまでの作製工程は実施例1と同様
であるので本実施例では省略する。In the HEMT manufacturing process of the present embodiment, the manufacturing steps up to the step shown in FIG. 1 are the same as those in the first embodiment, and are omitted in this embodiment.
【0023】次いで、図1に示す工程までを経た作製途
中のHEMTを真空ポンプで1×10~7Torr以下の
真空度に達するまで排気された真空槽内で、臭化水素ガ
ス(HBr)60mTorrとフッ素ガス(F2)12
0mTorrの混合ガス雰囲気下でArFエキシマレー
ザ装置から放出される約193nmの光を照射すること
により、オーミック層となるn型InGaAs層7をエ
ッチング除去し、バリア層となるノンドープInAlA
s層6を露出させた(図2)。次いで、純水洗浄、乾燥
後、アンモニア処理(アンモニア水溶液(アンモニア水
溶液(29%):水=1:100(体積))に浸淅した
後、純水洗浄)を行なった。Next, the HEMT in the process of being manufactured up to the step shown in FIG. 1 was evacuated by a vacuum pump until a vacuum degree of 1 × 10 to 7 Torr or less was reached, and hydrogen bromide gas (HBr) was 60 mTorr. And fluorine gas (F 2 ) 12
By irradiating light of about 193 nm emitted from the ArF excimer laser device in a mixed gas atmosphere of 0 mTorr, the n-type InGaAs layer 7 to be the ohmic layer is removed by etching and the non-doped InAlA to be the barrier layer.
The s layer 6 was exposed (FIG. 2). Then, after washing with pure water and drying, an ammonia treatment (washing with pure water after immersing in an aqueous ammonia solution (aqueous ammonia solution (29%): water = 1: 100 (volume))) was performed.
【0024】次いで、ゲート電極を形成してHEMTを
完成させた(図3)。電極形成法には通常のリフトオフ
法を用いた。Then, a gate electrode was formed to complete the HEMT (FIG. 3). The usual lift-off method was used for the electrode formation method.
【0025】本実施例のHEMT作製プロセスを用いて
作製したHEMTのゲート特性を図5の特性線501に
示す。また本実施例のHEMT作製プロセスにおいて前
述のアンモニア処理を行なわずに作製したHEMTのゲ
ート特性を図5の特性線502に示す。ゲート特性はソ
ース電圧を0Vとして、ゲート電圧Vgsを変化させな
がら、ゲート電流Igsの絶対値を測定した。ゲート電
圧0V〜0.4Vから求めた理想因子nと実効ビルトイ
ンポテンシャルΦBは、特性線501でn=約1.2、
ΦB=約0.55eV、特性線502でn=約2.2、
ΦB=約0.67eVとなり、特性線502と比較して
特性線501のほうがnにして約1.0改善されてい
る。ΦBは特性線502から得られた値のほうが大であ
るが、ゲート電圧0V〜0.4V付近では特性線401
や501のようにゲート電流が直線的に(図の縦軸が対
数軸であるので実際には指数関数的に)増加するほうが
ゲート特性は良好である。すなわち、特性線501と特
性線502とを比較すると特性線501のほうが良好な
ゲート特性を示している。これはHEMT作製プロセス
において前述のようなアンモニア処理を行なったためで
あり、換言するとアンモニア処理を行なうことはゲート
特性を改善する効果がある。The gate characteristic of the HEMT manufactured by using the HEMT manufacturing process of this embodiment is shown by a characteristic line 501 in FIG. A characteristic line 502 of FIG. 5 shows the gate characteristics of the HEMT manufactured without performing the above-mentioned ammonia treatment in the HEMT manufacturing process of this embodiment. Regarding the gate characteristics, the absolute value of the gate current Igs was measured while the source voltage was 0 V and the gate voltage Vgs was changed. The ideal factor n and the effective built-in potential ΦB obtained from the gate voltage 0V to 0.4V are n = about 1.2 on the characteristic line 501,
ΦB = about 0.55 eV, n = about 2.2 on the characteristic line 502,
ΦB = about 0.67 eV, and the characteristic line 501 is improved by n by about 1.0 compared with the characteristic line 502. The value obtained from the characteristic line 502 is larger for ΦB, but in the vicinity of the gate voltage 0 V to 0.4 V, the characteristic line 401
The gate characteristic is better when the gate current increases linearly (actually exponentially because the vertical axis of the figure is a logarithmic axis) as in FIG. That is, comparing the characteristic line 501 and the characteristic line 502, the characteristic line 501 shows better gate characteristics. This is because the above-described ammonia treatment was performed in the HEMT manufacturing process. In other words, performing the ammonia treatment has an effect of improving the gate characteristics.
【0026】また実施例1に記載した理由と同じ理由
で、ゲート電極12とバリア層6との界面からチャネル
層3までの距離が40nm以下のHEMTや、さらに薄
層化を進めて本実施例に示したようなゲート電極12と
バリア層6との界面からチャネル層3までの距離が24
nm以下の新規なHEMTの作製が、本発明を用いるこ
とにより可能となった。For the same reason as described in the first embodiment, the HEMT in which the distance from the interface between the gate electrode 12 and the barrier layer 6 to the channel layer 3 is 40 nm or less, or further thinning is performed, and this embodiment is performed. The distance from the interface between the gate electrode 12 and the barrier layer 6 to the channel layer 3 as shown in FIG.
The production of a novel HEMT having a thickness of nm or less has become possible by using the present invention.
【0027】本実施例においてはHEMTのゲート電極
形成の際にアンモニア処理を行なったが、HEMT以外
の半導体素子、例えばMESFET(MEtal Se
miconductor FET)などについても同様
の効果が得られる。In the present embodiment, the ammonia treatment was performed when forming the gate electrode of the HEMT, but a semiconductor element other than HEMT, for example, MESFET (MEtal Se).
The same effect can be obtained for a micro field effect transistor (FET).
【0028】本実施例においてはオーミック層となるn
型InGaAs層7のエッチングを臭化水素ガス(HB
r)60mTorrとフッ素ガス(F2)120mTo
rrの混合ガス雰囲気下でArFエキシマレーザ装置か
ら放出される約193nmの光を照射することにより行
なったが、前記ガス分圧とは異なるガス分圧、ハロゲン
原子を含む他の種類のガス、他の種類のエキシマレーザ
装置から放出される光をそれぞれ用いた場合でも、ゲー
ト特性の改善効果が同様に得られる。In this embodiment, the ohmic layer n
Type InGaAs layer 7 is etched with hydrogen bromide gas (HB
r) 60 mTorr and fluorine gas (F 2 ) 120 mTo
The irradiation was performed by irradiating light of about 193 nm emitted from the ArF excimer laser device in a mixed gas atmosphere of rr, but a gas partial pressure different from the gas partial pressure, another kind of gas containing a halogen atom, etc. Even when the light emitted from the excimer laser devices of the above types is used, the effect of improving the gate characteristics can be obtained similarly.
【0029】また本実施例において用いたアンモニア水
溶液は前述の仕様に希釈したものを用いたが、前述の仕
様に限定されるものではない。The aqueous ammonia solution used in this example was diluted to the above specifications, but it is not limited to the above specifications.
【0030】さらに本実施例に用いたアンモニアの替わ
りに、N−H結合を有する化合物の塩基性溶液を用いて
も同様の効果がある。Further, the same effect can be obtained by using a basic solution of a compound having an NH bond in place of the ammonia used in this example.
【0031】さらに本実施例ではチャネル層をInGa
As、スペーサ層、キャリア供給層、バリア層をInA
lAsで作製したが、このInGaAsとInAlAs
の組合せを例えばInGaAsとAlGaAsの組合せ
やGaAsとAlGaAsの組合せやGaAsSbとA
lGaAsの組合せなどのように材料を変えても本発明
の主旨から逸脱しないことはいうまでもない。Further, in this embodiment, the channel layer is made of InGa.
AsA, spacer layer, carrier supply layer, and barrier layer are made of InA.
It was made of InAs, but this InGaAs and InAlAs
For example, a combination of InGaAs and AlGaAs, a combination of GaAs and AlGaAs, and a combination of GaAsSb and A
It goes without saying that changing the material such as the combination of 1 GaAs does not depart from the gist of the present invention.
【0032】[0032]
【発明の効果】本発明によれば、ミリ波周波数帯(30
GHz−300GHz)利用システムの基本デバイスと
なるHEMTを歩留良く作製できる。According to the present invention, the millimeter wave frequency band (30
(GHz-300 GHz) HEMT which is a basic device of a utilization system can be manufactured with a high yield.
【図1】本発明の実施例1,2の半導体装置の製造工程
断面図である。FIG. 1 is a cross-sectional view of a manufacturing process of a semiconductor device according to first and second embodiments of the present invention.
【図2】本発明の実施例1,2の半導体装置の製造工程
断面図である。FIG. 2 is a sectional view of a semiconductor device manufacturing process according to the first and second embodiments of the present invention.
【図3】本発明の実施例1,2の半導体装置の製造工程
断面図である。FIG. 3 is a sectional view of a semiconductor device manufacturing process according to the first and second embodiments of the present invention.
【図4】本発明の実施例1の半導体装置の製造工程にお
けるアンモニア処理の有無の場合のHEMTのゲート特
性を示す図である。FIG. 4 is a diagram showing the gate characteristics of the HEMT with and without the ammonia treatment in the manufacturing process of the semiconductor device according to the first embodiment of the present invention.
【図5】本発明の実施例2の半導体装置の製造工程にお
けるアンモニア処理の有無の場合のHEMTのゲート特
性を示す図である。FIG. 5 is a diagram showing the gate characteristics of a HEMT with and without ammonia treatment in the semiconductor device manufacturing process according to the second embodiment of the present invention.
1……半絶縁性InP基板、2……バッファ層となるノ
ンドープInAlAs層、3……チャネル層となるノン
ドープInGaAs層、4……スペーサ層となるノンド
ープInAlAs層、5……キャリア供給層となるn型
InAlAs層、6……バリア層となるノンドープIn
AlAs層、7……オーミック層となるn型InGaA
s、8……絶縁膜、9……ソース電極、10……ドレイ
ン電極、11……開口、12……ゲート電極、401、
501……アンモニア処理有の場合のHEMTのゲート
特性線。402、502……アンモニア処理無の場合の
HEMTのゲート特性線。1 ... Semi-insulating InP substrate, 2 ... Non-doped InAlAs layer serving as buffer layer, 3 ... Non-doped InGaAs layer serving as channel layer, 4 ... Non-doped InAlAs layer serving as spacer layer, 5 ... Carrier supply layer n-type InAlAs layer, 6 ... Non-doped In serving as a barrier layer
AlAs layer, 7 ... n-type InGaA to be an ohmic layer
s, 8 ... Insulating film, 9 ... Source electrode, 10 ... Drain electrode, 11 ... Opening, 12 ... Gate electrode, 401,
501: HEMT gate characteristic line when ammonia treatment is performed. 402, 502 ... HEMT gate characteristic line without ammonia treatment.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 21/338 9447−4M H01L 29/80 H 29/812 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification number Office reference number FI Technical indication location H01L 21/338 9447-4M H01L 29/80 H 29/812
Claims (19)
を含む半導体層を含む半導体積層膜のうちの一部分を酸
性水溶液を用いることによりエッチング除去する工程
と、前記エッチング除去を行なうことにより露出した半
導体表面をN−H結合を有する化合物の塩基性水溶液に
浸淅することにより処理する工程と、前記処理を行なっ
た半導体表面にゲート電極となる金属を被着させる工程
とを順次行なうことを特徴とする半導体装置の製造方
法。1. An Al formed on one main surface of a semiconductor substrate.
Etching a part of the semiconductor laminated film including a semiconductor layer including a semiconductor layer by using an acidic aqueous solution, and exposing the semiconductor surface exposed by the etching to a basic aqueous solution of a compound having an N—H bond. A method of manufacturing a semiconductor device, comprising sequentially performing a step of treating by immersing and a step of depositing a metal to be a gate electrode on a surface of the treated semiconductor.
を特徴とする請求項1記載の半導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein the acidic aqueous solution is an organic acid aqueous solution.
ことを特徴とする請求項2記載の半導体装置の製造方
法。3. The method of manufacturing a semiconductor device according to claim 2, wherein the organic acid aqueous solution is a citric acid aqueous solution.
溶液がアンモニア水溶液であることを特徴とする請求項
1乃至3のいずれかに記載の半導体装置の製造方法。4. The method for manufacturing a semiconductor device according to claim 1, wherein the basic aqueous solution of the compound having an N—H bond is an aqueous ammonia solution.
導体積層膜のうちの一部分を酸性水溶液を用いることに
よりエッチング除去する工程が電界効果トランジスタの
ゲートリセス形成工程であることを特徴とする請求項1
乃至4のいずれかに記載の半導体装置の製造方法。5. A step of forming a gate recess of a field effect transistor is a step of etching away a part of a semiconductor laminated film formed on one main surface of the semiconductor substrate by using an acidic aqueous solution. Claim 1
5. The method for manufacturing a semiconductor device according to any one of 4 to 4.
導体積層膜のうちの一部分を酸性水溶液を用いることに
よりエッチング除去する工程を行なうことによってAl
を含む半導体層の表面を露出させることを特徴とする請
求項1乃至5のいずれかに記載の半導体装置の製造方
法。6. A step of etching and removing a part of a semiconductor laminated film formed on one main surface of the semiconductor substrate by using an acidic aqueous solution is performed.
6. The method of manufacturing a semiconductor device according to claim 1, wherein the surface of the semiconductor layer containing is exposed.
0より大で1未満であるInyAl1-yAsであること
を特徴とする請求項6記載の半導体装置の製造方法。7. The method of manufacturing a semiconductor device according to claim 6, wherein the semiconductor layer containing Al is InyAl1-yAs having an In composition ratio y of more than 0 and less than 1.
積層膜のうちの一部分をハロゲン原子を含むガスを用い
ることによりエッチング除去する工程と、前記エッチン
グ除去を行なうことにより露出した半導体表面をN−H
結合を有する化合物の塩基性水溶液に浸淅することによ
り処理する工程と、前記処理を行なった半導体表面にゲ
ート電極となる金属を被着させる工程とを順次行なうこ
とからなることを特徴とする半導体装置の製造方法。8. A step of etching away a part of a semiconductor laminated film formed on one main surface of a semiconductor substrate by using a gas containing a halogen atom, and a semiconductor surface exposed by performing the etching removal. N-H
A semiconductor characterized by comprising sequentially performing a step of treating by immersing a compound having a bond in a basic aqueous solution and a step of depositing a metal to be a gate electrode on the surface of the treated semiconductor. Device manufacturing method.
導体積層膜のうちの一部分をハロゲン原子を含むガスを
用いることによりエッチング除去する工程においては、
前記半導体基板の一主面上に形成された半導体積層膜に
エキシマレーザ装置から放出されるパルス光が照射され
ることを特徴とする請求項8記載の半導体装置の製造方
法。9. A step of etching away a part of the semiconductor laminated film formed on one main surface of the semiconductor substrate by using a gas containing a halogen atom,
9. The method for manufacturing a semiconductor device according to claim 8, wherein the semiconductor laminated film formed on the one main surface of the semiconductor substrate is irradiated with pulsed light emitted from an excimer laser device.
ガス、もしくはHBrガスとF2ガスの混合ガスである
ことを特徴とする請求項8又は9記載の半導体装置の製
造方法。10. The gas containing a halogen atom is HBr.
10. The method for manufacturing a semiconductor device according to claim 8, wherein the gas is a gas or a mixed gas of HBr gas and F 2 gas.
水溶液がアンモニア水溶液であることを特徴とする請求
項8乃至10のいずれかに記載の半導体装置の製造方
法。11. The method of manufacturing a semiconductor device according to claim 8, wherein the basic aqueous solution of the compound having an N—H bond is an aqueous ammonia solution.
半導体積層膜のうちの一部分をハロゲン原子を含むガス
を用いることによりエッチング除去する工程が電界効果
トランジスタのゲートリセス形成工程であることを特徴
とする請求項8乃至11のいずれかに記載の半導体装置
の製造方法。12. A step of forming a gate recess of a field effect transistor, wherein the step of etching away a part of the semiconductor laminated film formed on the one main surface of the semiconductor substrate by using a gas containing a halogen atom. The method of manufacturing a semiconductor device according to claim 8, wherein the method is a semiconductor device manufacturing method.
半導体積層膜のうちの一部分をハロゲン原子を含むガス
を用いることによりエッチング除去する工程を行なうこ
とによりAlを含む半導体層の表面を露出させることを
特徴とする請求項8乃至12のいずれかに記載の半導体
装置の製造方法。13. A surface of a semiconductor layer containing Al is removed by performing a step of etching away a part of a semiconductor laminated film formed on one main surface of the semiconductor substrate by using a gas containing a halogen atom. 13. The method for manufacturing a semiconductor device according to claim 8, wherein the method is exposed.
が0より大で1未満であるInyAl1-yAsであるこ
とを特徴とする請求項13記載の半導体装置の製造方
法。14. The In composition ratio y of the semiconductor layer containing Al.
14. The method of manufacturing a semiconductor device according to claim 13, wherein InyAl1-yAs is greater than 0 and less than 1.
ート電極となる導電性材料領域に接する半導体材料領域
との接触界面からチャネル層となる半導体材料領域端部
までの距離が40nm以下であり、且つ前記ゲート電極
となる導電性材料領域と該ゲート電極となる導電性材料
に接する半導体材料領域との接触界面からチャネル層と
なる半導体材料領域端部までの間にAlを含む半導体膜
が存在し、且つ前記チャネル層となる半導体材料はGa
を含む電界効果トランジスタを有することを特徴とする
半導体装置。15. A distance from a contact interface between a conductive material region serving as a gate electrode and a semiconductor material region in contact with the conductive material region serving as the gate electrode to an end portion of the semiconductor material region serving as a channel layer is 40 nm or less. And a semiconductor film containing Al is present between the contact interface between the conductive material region serving as the gate electrode and the semiconductor material region in contact with the conductive material serving as the gate electrode to the end of the semiconductor material region serving as the channel layer. And the semiconductor material forming the channel layer is Ga
A semiconductor device having a field effect transistor including:
該ゲート電極となる導電性材料領域に接する半導体材料
領域との接触界面からチャネル層となる半導体材料領域
端部までの距離が24nm以下であることを特徴とする
請求項15記載の半導体装置。16. A distance from a contact interface between a conductive material region serving as the gate electrode and a semiconductor material region in contact with the conductive material region serving as the gate electrode to an end portion of the semiconductor material region serving as a channel layer is 24 nm or less. 16. The semiconductor device according to claim 15, wherein the semiconductor device is present.
であることを特徴とする請求項15又は16に記載の半
導体装置。17. The semiconductor film containing Al is InAlAs.
The semiconductor device according to claim 15 or 16, wherein
GaAsであることを特徴とする請求項15又は16に
記載の半導体装置。18. The semiconductor material forming the channel layer is In
17. The semiconductor device according to claim 15, which is GaAs.
ron Mobility Transistorであ
ることを特徴とする請求項15乃至18のいずれかに記
載の半導体装置。19. The semiconductor device is a High Elect
19. The semiconductor device according to claim 15, wherein the semiconductor device is a ron Mobility Transistor.
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