JPH09294051A - Loop filter circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stop the operation of a level limiter when a large frequency change in an input signal is not suddenly caused while the level limiter is in operation when a large frequency change in an input signal is suddenly caused. SOLUTION: This circuit is used for a phase locked loop(PLL). A phase comparison signal Vi outputted from a phase comparator I is given to an inverting terminal of an operational amplifier OA. Moreover, a series circuit consisting of a resistor R2 and a 1st capacitor C1 , and a 2nd capacitor C2 are connected in parallel between the inverting terminal and an output terminal of the operational amplifier OA.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a loop filter circuit used in PLL.

[0002]

2. Description of the Related Art Generally, a PLL (Phase Loc) is used.
As shown in FIG. 8, the Ked Loop) has a phase comparator I, a loop filter circuit LF, an error signal amplifier A, and a voltage controlled oscillator VCO (Voltage Controlled Oscillator).
It is a feedback system with a lator). The phase comparator I is
The frequency and phase of the input signal V are compared with the oscillation frequency and phase of the VCO, and a phase comparison signal Vi proportional to the error is generated. The phase comparison signal Vi is added to the VCO as a control signal Vc through the loop filter circuit LF, and the generation frequency of the VCO is changed in a direction to reduce the frequency difference and the phase difference between the input signal V and the output signal O of the VCO. It is a thing.

On the other hand, as shown in FIGS. 9 and 10, the conventional general loop filter circuits 100 and 200 used in this type of PLL use well-known resistors, capacitors and operational amplifiers, respectively, as shown in the figure. 9 and FIG. 10, only the reference numerals of the constituent members are attached.

The loop filter circuits 100 and 200
Both are based on a method called a charge pump method. The former loop filter circuit 100 obtains a stable response characteristic while eliminating the stationary phase error, while the latter loop filter circuit 200 is a circuit aiming at further suppression of high frequency jitter.

Another example of a conventional general loop filter circuit used for a PLL is disclosed in Japanese Patent Laid-Open No. 3-119818 as shown in FIG.

As shown in FIG. 11, the limiter circuit 306
In the loop filter circuit 300 that adopts the phase comparison signal Vi output from the phase comparator (not shown)
01 to the inverting input terminal of the operational amplifier 302. A capacitor 303, a resistor 304 connected in series with the capacitor 303, and a capacitor 3 are provided between the inverting input terminal and the output terminal of the operational amplifier 302.
05 and this capacitor 305 and a limiter circuit 306 connected in series are connected in parallel. On this occasion,
The limiter circuit 306 includes two diodes 306a and 30
6b is used for connection as shown.

The loop filter circuit 30 having the above configuration
At 0, when an AC voltage having a large amplitude is applied to the phase comparison signal Vi, the impedance of the diodes 306a and 306b becomes exponentially lower than the voltage applied to the diodes 306a and 306b, and thus the capacitor 305.
The output amplitude is limited to the on-voltages of the diodes 306a and 306b if the frequency is such that the impedance is sufficiently low. For this reason, the limiter circuit 306 operates for a signal having a relatively high frequency of the phase comparison signal Vi and a large amplitude to limit unnecessary signals and prevent saturation of the operational amplifier 302. The purpose of this circuit is PLL
The primary purpose is to prevent the saturation of the operational amplifier 302 that leads to the deadlock of the limiter circuit 3 as a result.
When 06 operates, it can be understood that unnecessary high frequency jitter is limited.

[0008]

By the way, in the loop filter circuit 300 employing the limiter circuit 306, the phase comparison signal Vi has a somewhat high frequency, which is assumed when the high frequency jitter of the input signal V is large. Although the limiter circuit 306 is operating for a signal having a large amplitude, it is not for making the PLL respond quickly when the frequency of the input signal V changes abruptly, for example, stepwise. It does not suppress the occurrence of high frequency jitter when the frequency does not change sharply.

Further, the above-described general loop filter circuits 100 and 200 are not such that the fast response of the PLL can be obtained when the frequency of the input signal V changes abruptly. The reason is described below.

The loop filter circuits 100, 200,
In 300, when the frequency of the input signal V is drastically changed in a stepwise manner, the speed of the followability of the PLL is, for example, as shown in FIG.
It largely depends on the time constant set by the capacitor 303 and the resistor 304 in No. 1. Here, the smaller the time constant is, the better the response is. However, when the time constant is small, the low-frequency fluctuation is easily tracked, so that the low-frequency jitter increases.
That is, in the loop filter circuits 100, 200, and 300, it is difficult to achieve both good responsiveness when the frequency of the input signal V largely changes and low low-frequency jitter.

Therefore, there is a demand for a loop filter circuit having a good loop gain characteristic, which responds to a change in the frequency of the input signal V and has a quick response when a large change occurs and can suppress a jitter when a small change occurs.

[0012]

The present invention has been made in view of the above problems, and a first invention is a loop filter circuit used in a PLL, in which a phase comparison signal output from a phase comparator is set to a negative polarity. A first capacitor which is input to the sex terminal and which is connected in series with the resistor,
A loop filter circuit comprising: an operational amplifier in which a second capacitor is connected in parallel between the negative terminal and the output terminal, and a level limiter connected across the resistor via a buffer amplifier. Is. A second invention is, in a loop filter circuit used for a PLL, a phase comparison signal output from a phase comparator is input to a negative terminal, and a resistor and a first capacitor connected in series with this resistor are provided. And an operational amplifier in which a second capacitor is connected in parallel between the negative terminal and the output terminal, a potential difference monitoring circuit for monitoring the potential difference between both ends of the resistor, and the potential difference monitored by the potential difference monitoring circuit. It is characterized by further comprising: a level discriminating circuit for discriminating that a predetermined set level is exceeded, and a current adding circuit for summing a current to one of the terminals of the resistor according to a result discriminated by the level discriminating circuit. It is a loop filter circuit.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a loop filter circuit according to the present invention will be described below with reference to FIGS. 1 to 7 of <First Embodiment>, <Second Embodiment>, and <Third Embodiment>. It will be described in detail in order.

[0014]

【Example】

<First Embodiment> FIG. 1 is a diagram showing a loop filter circuit of a first embodiment according to the present invention, and FIG. 2 is for explaining a loop gain characteristic of a PLL adopting the loop filter circuit of the first embodiment. 3A and 3B are waveform charts for explaining the operation of the loop filter circuit of the first embodiment.

The loop filter circuit LF1 of the first embodiment according to the present invention shown in FIG. 1 is used in the PLL (Phase Locked Loop) described above with reference to FIG.

That is, in the loop filter circuit LF1 of the first embodiment according to the present invention shown in FIG. 1, the phase comparator I has an input signal V and a voltage controlled oscillator VCO (Voltage Cont.
The output signal O from the rolled oscillator is compared in phase and the phase comparison signal Vi is output. This phase comparison signal Vi can take three states of high level H, high impedance HZ with no input, or low level L. Here, the phase comparison signal Vi is the first resistance R
₁ is input to the negative (-) polarity terminal of the operational amplifier OA, while the reference signal REF, which is an intermediate potential between the high level H and the low level L of the phase comparison signal Vi, has the positive (+) polarity of the operational amplifier OA. It is input to the terminal.

A second resistor R ₂ and this resistor R ₂ are provided between the negative (−) polarity terminal and the output terminal of the operational amplifier OA.
_A first capacitor C ₁ and a second capacitor C ₂ connected in series with ₂ are connected in parallel.

Further, a buffer amplifier BA, which is an essential part of the present invention, and a level limiter LL using _two diodes D ₁ and D ₂ are connected in series between both ends of the resistor R ₂ . That is, the resistance R ₂ is input to the input terminal of the buffer amplifier BA from the connection portion with the operational amplifier OA.
The output terminal of the buffer amplifier BA is connected to one end of the level limiter LL, and the other end of the level limiter LL is connected between the resistor R ₂ and the capacitor C ₁ . Here, the level limiter LL connected across the resistor R ₂ via the buffer amplifier BA connects the two diodes D ₁ and D ₂ in opposite directions of − + as shown in the drawing. Further, the connecting portions of the diodes D ₁ and D ₂ are provided so as to be one end and the other end of the level limiter LL.

Next, as shown in FIG. 2, P which employs the loop filter circuit LF1 of the first embodiment having the above-mentioned configuration.
The loop gain characteristic of LL (Phase Locked Loop) is −12 dB / in the range where the frequency f of the input signal V for applying the PLL is, for example, the frequency f ₁ or less.
It becomes the slope of OCT and is higher than frequency f ₁ and frequency f _1.
The slope is -6 dB / OCT in the range lower than _2, and the slope is -12 dB / OCT in the range of frequency f ₂ or higher, and the slope gently crosses at the frequencies f ₁ and f ₂ which are the intersections of the slopes.

At this time, if the loop filter circuit LF1 of the first embodiment is designed assuming that the value of the capacitor C ₁ is sufficiently larger than the value of the capacitor C ₂ , the frequency f ₁ can be calculated by the capacitor C ₁ and the resistor R _2. The approximate value is frequency f ₁ = 1 / 2πC ₁ R ₂ , and the frequency f ₂ can be calculated by the capacitor C ₂ and the resistor R ₂ and the approximate value is the frequency f.
₂ = 1 / 2πC ₂ R ₂ and there is a loop gain intersection frequency fx at the point where the −6 dB / OCT slope between the frequencies f ₁ and f ₂ intersects with the 0 dB gain line.

Next, the operation of the loop filter circuit LF1 of the first embodiment having the above-described configuration is divided into two cases, when the frequency f of the input signal V changes sharply and when the frequency f of the input signal V does not change sharply. The description will be made with reference to FIGS.

First, when the frequency f of the input signal V changes abruptly, the level limiter LL connected to both ends of the resistor R ₂ via the buffer amplifier BA operates. That is,
As shown in FIG. 3A, when the frequency f of the input signal V changes abruptly, the phase comparison signal Vi output from the phase comparator I changes from the high impedance HZ to the low level L for a long time, for example. Change. This low level L
During the period, the voltage E _R2 across the resistor R ₂ is suppressed to the voltage E _LL across the level limiter LL after a certain period of time during which the charging of the capacitor C ₂ proceeds. In this case, the current from the buffer amplifier BA is supplied to the capacitor C ₁ via the level limiter LL, and the capacitor C ₁ is supplied.
_{Since the} capacitor C ₁ operates substantially as if the capacitance of the capacitor C ₁ becomes low by strongly charging the voltage to _1, the frequency f _{1 of} the input signal V that is equal to or lower than the loop gain intersection point frequency fx is temporarily high. A loop filter with excellent response can be realized. When this is seen from the change of the control signal C to the VCO, it rises in an earlier time than in the case where the level limiter LL is not provided, and excellent responsiveness to reach the desired control voltage can be obtained with a small phase error. ing.

Next, when the frequency f of the input signal V does not change abruptly, the level limiter LL does not operate. That is, as shown in FIG. 3 (B), when the frequency f of the input signal V does not change sharply, the phase comparison signal Vi output from the phase comparator I is low level from the high impedance HZ for a short time, for example. Change to L. During the period of the low level L, the voltage ER ₂ across the resistor R ₂ rises to some extent as the capacitor C ₂ is charged, but the control voltage soon reaches a desired value, so the voltage across the level limiter LL is reduced. The value of E _LL is not reached. In this case, since the level limiter LL does not operate, the original effect of the capacitor C ₁ can be exerted, and the frequency f ₁ of the input signal V that is equal to or lower than the loop gain intersection frequency fx can be kept low and the loop with low jitter can be reduced. A filter can be realized.

Further, even when the frequency f of the input signal V changes suddenly or not, the high frequency jitter can be suppressed by the action of the capacitor C _{2 for} the range exceeding the high frequency f ₂ which is equal to or higher than the loop gain intersection frequency fx. it can.

<Second Embodiment> FIG. 4 shows a second embodiment of the present invention.
FIG. 5 is a diagram showing a loop filter circuit of the embodiment, and FIG. 5 is a diagram showing a partially modified version of the loop filter circuit of the second embodiment according to the present invention.

The loop filter circuit LF2A of the second embodiment according to the present invention shown in FIG. 4 has the same configuration as the loop filter circuit LF1 of the first embodiment described above except for a part, and here, For convenience of explanation, the same reference numerals are given to the above-mentioned constituent members, and new reference numerals are given to different constituent members, and the description will focus on the points different from the first embodiment.

As shown in FIG. 4, the loop filter circuit LF2A of the second embodiment according to the present invention is different from the first embodiment only in that _two transistors Tr ₁ and Tr ₂ are used as the level limiter LL. ing.

That is, the two transistors Tr ₁ and Tr ₂ forming the level limiter LL connect the npn type and the pnp type in a closed loop state, and the transistor T
One end and the other end of the level limiter LL are provided between r ₁ and Tr ₂ , respectively.

The loop filter circuit LF of the second embodiment
Also in 2A, as with the loop filter circuit LF1 of the first embodiment described above, the level limiter LL operates when the frequency f of the input signal V changes abruptly, while the frequency limiter LL of the input signal V does not change abruptly. Since the level limiter LL does not operate, the same effect as the first embodiment can be obtained.

[0030] Incidentally, as shown in FIG. 5, the loop filter circuit LF2B obtained by modifying a part of the second embodiment, the first capacitor C ₁ connected to the front of the resistor R _2, the level limiter LL along with this , A buffer amplifier BA is also connected as shown in the figure, and the loop filter circuit LF
The operation similar to that of 2A produces substantially the same effect.

<Third Embodiment> FIG. 6 shows a third embodiment of the present invention.
FIG. 7 is a diagram showing a loop filter circuit of the embodiment, and FIG. 7 is a diagram showing a partially modified version of the loop filter circuit of the third embodiment according to the present invention.

The loop filter circuit LF3A of the third embodiment according to the present invention shown in FIG. 6 is the loop filter circuits LF1, LF2A, LF of the first and second embodiments described above.
2B has the same configuration except for a part, and here, for convenience of description, the same reference numerals are given to the above-mentioned constituent members, and new reference numerals are given to different constituent members, First
The difference from the embodiment will be mainly described.

As shown in FIG. 6, in the loop filter circuit LF3A according to the third embodiment of the present invention, the buffer amplifier BA and level limiter L described in the first and second embodiments are used.
Instead of providing L, the potential difference monitoring circuit VK, the level determination circuit LH, and the current addition circuit IK are sequentially connected to both ends of the resistor R ₂ instead of L.

[0034] That is, the potential difference monitoring circuit VK connected to both ends of the resistor R ₂ is, the potential difference across the resistor R ₂ monitors, and outputs the monitored potential difference to the level discrimination circuit LH. When the level discriminating circuit LH compares the monitored potential difference with the predetermined set level input thereto and determines that the monitored potential difference exceeds the predetermined set level, the level discriminating circuit LH outputs the current addition control signal to the current adding circuit IK. The current adding circuit IK outputs a current to one terminal of the resistor R ₂ shown in the figure, and supplies the current to the first capacitor C ₁ .

Therefore, by the operation according to the above configuration, especially when the frequency f of the input signal V changes abruptly, the potential difference between both ends of the resistor R ₂ exceeds a predetermined set level, and accordingly, the current adding circuit IK. supplies current to the first capacitor C ₁ from, by performing the charge to the first capacitor C ₁ strongly because it operates as substantially a first capacitance of the capacitor C ₁ is lower , The frequency f of the input signal V that is equal to or lower than the loop gain intersection frequency fx
₁ is temporarily increased, and a loop filter with good responsiveness can be realized.

On the other hand, when the frequency f of the input signal V does not change abruptly, the current adding circuit IK does not operate.
The original effect of the capacitor C ₁ can be exerted, and the frequency f ₁ of the input signal V that is equal to or lower than the loop gain intersection frequency fx can be kept low to realize a loop filter with less low frequency jitter.

Further, when the frequency f of the input signal V changes suddenly or not, the high frequency jitter can be suppressed by the action of the capacitor C _{2 in} the range exceeding the high frequency f ₂ which is equal to or higher than the loop gain intersection frequency fx. it can.

As shown in FIG. 7, in the loop filter circuit LF3B, which is a partial modification of the third embodiment, the first capacitor C ₁ is connected in front of the resistor R ₂ , and accordingly the current adding circuit is connected. The current from IK is output to the other terminal of the resistor R ₂ shown in the figure, and the current is supplied to the first capacitor C ₁ connected in front of the resistor R ₂ .
The operation similar to that of the loop filter circuit LF3A produces substantially the same effect.

[0039]

In the loop filter circuit LF according to the present invention described in detail above, according to the first invention, the phase comparison signal Vi output from the phase comparator I is supplied to the operational amplifier OA.
Type of the negative terminal, and the resistor R ₂ and the resistor R
_A first capacitor C ₁ and a second capacitor C ₂ connected in series with ₂ are connected in parallel between the negative terminal and the output terminal of the operational amplifier OA, and a buffer amplifier is provided between both ends of the resistor R _2. Since the level limiter LL is connected via BA, when the frequency f of the input signal V changes abruptly, the level limiter LL connected to both ends of the resistor R ₂ via the buffer amplifier BA operates.
The first is supplied to the capacitor C ₁ via a current level limiter LL from the buffer amplifier BA, by performing the charge to the first capacitor C ₁ strongly, substantially of the first capacitor C ₁ Since it operates as if the capacitance became low, the loop gain crossover frequency fx of the input signal V is
The following frequency f ₁ is temporarily increased, and a loop filter with good responsiveness can be realized. On the other hand, when the frequency f of the input signal V does not change abruptly, the level limiter LL does not operate, so that the original effect of the capacitor C ₁ can be exhibited, and the frequency f ₁ of the input signal V that is equal to or lower than the loop gain intersection frequency fx is reduced. It can be kept low to realize a loop filter with low low-frequency jitter. Further, when the frequency f of the input signal V changes suddenly or not, the loop gain intersection frequency fx
In the range exceeding the above high frequency f ₂ , the high frequency jitter can be suppressed by the function of the capacitor C ₂ .
According to the second invention, the phase comparison signal Vi output from the phase comparator I is input to the negative terminal of the operational amplifier OA, and the resistor R ₂ and the resistor R ₂ are connected in series. The capacitor C ₁ and the second capacitor C ₂ are connected in parallel between the negative terminal and the output terminal of the operational amplifier OA, and the potential difference monitoring circuit V is connected across the resistor R _2.
Since the K, the level discriminating circuit LH, and the current adding circuit IK are sequentially connected, the potential difference between both ends of the resistor R ₂ exceeds a predetermined set level, especially when the frequency f of the input signal V largely changes suddenly. A current is supplied from the current adding circuit I to the first capacitor C ₁ to generate the first capacitor C _1.
By strongly charging to ₁ , it operates substantially as if the capacitance of the first capacitor C ₁ became low,
In the input signal V, the frequency f _{1 that} is equal to or lower than the loop gain intersection point frequency fx is temporarily increased, and a loop filter with good responsiveness can be realized. On the other hand, when the frequency f of the input signal V does not change abruptly, the current adding circuit IK does not operate, so that the original effect of the capacitor C ₁ can be exhibited, and the frequency f _{1 of the} input signal V that is equal to or lower than the loop gain intersection frequency fx is obtained. Can be kept low to realize a loop filter with low low-frequency jitter. Furthermore, when the frequency f of the input signal V changes suddenly or not, the high frequency jitter can be suppressed by the action of the capacitor C _{2 in} the range exceeding the high frequency f ₂ which is equal to or higher than the loop gain intersection frequency fx.

[Brief description of drawings]

FIG. 1 is a diagram showing a loop filter circuit of a first embodiment according to the present invention.

FIG. 2 is a diagram for explaining a loop gain characteristic of a PLL adopting the loop filter circuit of the first embodiment according to the present invention.

3A and 3B are waveform diagrams for explaining the operation of the loop filter circuit according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a loop filter circuit according to a second embodiment of the present invention.

FIG. 5 is a partially modified view of a loop filter circuit according to a second embodiment of the present invention.

FIG. 6 is a diagram showing a loop filter circuit according to a third embodiment of the present invention.

FIG. 7 is a diagram showing a partially modified version of a loop filter circuit according to a third embodiment of the present invention.

FIG. 8 is a diagram showing a general PLL.

FIG. 9 is a diagram showing a conventional general loop filter circuit.

FIG. 10 is a diagram showing a conventional general loop filter circuit.

FIG. 11 is a diagram showing a conventional general loop filter circuit.

[Explanation of symbols]

LF1 ... loop filter circuit of the first embodiment, LF2A, LF2B ... loop filter circuit of the second embodiment, LF3 ... loop filter circuit of the third embodiment, C 1 _... first capacitor, C 2 _... second capacitor , R ₁ ... First resistance, R ₂ ... Second resistance, BA ... Buffer amplifier, I ... Phase comparator, LL ... Level limiter, OA ... Operational amplifier, VK ... Potential difference monitoring circuit, LH ... Level discrimination circuit, IK ... current adding circuit, V ... input signal, Vi ... phase comparison signal.

Claims (2)

[Claims] 1. A loop filter circuit used in a PLL, wherein a phase comparison signal output from a phase comparator is input to a negative terminal, and a resistor and a first capacitor connected in series with the resistor, A loop filter circuit comprising: an operational amplifier in which two capacitors are connected in parallel between the negative terminal and the output terminal, and a level limiter connected between both ends of the resistor via a buffer amplifier. 2. A loop filter circuit used in a PLL, wherein a phase comparison signal output from a phase comparator is input to a negative terminal, and a resistor and a first capacitor connected in series with the resistor, An operational amplifier in which two capacitors are connected in parallel between the negative terminal and the output terminal, a potential difference monitoring circuit that monitors the potential difference between both ends of the resistor, and the potential difference monitored by the potential difference monitoring circuit is set to a predetermined value. A loop filter circuit comprising: a level discriminating circuit for discriminating that the level has been exceeded; and a current adding circuit for summing a current to one of the terminals of the resistor according to the result discriminated by the level discriminating circuit. .