JPH09293716A - Forming method of insulating film containing fluorine - Google Patents
Forming method of insulating film containing fluorineInfo
- Publication number
- JPH09293716A JPH09293716A JP8102546A JP10254696A JPH09293716A JP H09293716 A JPH09293716 A JP H09293716A JP 8102546 A JP8102546 A JP 8102546A JP 10254696 A JP10254696 A JP 10254696A JP H09293716 A JPH09293716 A JP H09293716A
- Authority
- JP
- Japan
- Prior art keywords
- fluorine
- film
- insulating film
- ozone
- containing silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02131—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being halogen doped silicon oxides, e.g. FSG
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置の製造
方法、特に配線を隔離するための絶縁膜の製造方法に関
するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing an insulating film for isolating wiring.
【０００２】[0002]
【従来の技術】半導体装置においては、素子および配線
を隔離するために絶縁膜が用いられる。従来この絶縁膜
として、シラン等を原料として減圧または常圧の化学気
相蒸着（ＣＶＤ）法により形成された酸化ケイ素（Ｓｉ
Ｏ2 ）膜が使用されている。第一層間膜としては硼素と
リンを含むＳｉＯ2 膜（ＢＰＳＧ）が一般に使用され、
アルミニウムまたはその合金の配線間の絶縁膜として
は、テトラエトキシシラン（ＴＥＯＳ）と酸素とを用い
たプラズマＣＶＤ法によるＳｉＯ2 （ｐ−ＴＥＯＳ）膜
や、ＴＥＯＳとオゾン（Ｏ3 ）を用いた常圧熱ＣＶＤ法
によるＳｉＯ2（Ｏ3 −ＴＥＯＳ）膜を用いることが多
い。2. Description of the Related Art In a semiconductor device, an insulating film is used to isolate an element and a wiring. Conventionally, as the insulating film, silicon oxide (Si) formed by a chemical vapor deposition (CVD) method under reduced pressure or normal pressure using silane or the like as a raw material.
O 2 ) films are used. As the first interlayer film, a SiO 2 film (BPSG) containing boron and phosphorus is generally used,
As an insulating film between wirings of aluminum or its alloy, a SiO 2 (p-TEOS) film formed by a plasma CVD method using tetraethoxysilane (TEOS) and oxygen, or a normal film using TEOS and ozone (O 3 ). A SiO 2 (O 3 -TEOS) film formed by the pressure heat CVD method is often used.
【０００３】しかしながら近年、素子の微細化に伴い、
信号伝達遅延の問題が懸念されている。これは、素子の
微細化に伴って配線間隔が狭くなるに従い、配線間容量
が増大するために生ずる。この信号伝達遅延は、半導体
装置の性能向上を妨げるものである。従って、配線間容
量の低減が必要であり、これは主に絶縁膜の誘電率の低
減により達成される。However, with the recent miniaturization of elements,
There is concern about the problem of signal transmission delay. This occurs because the inter-wiring capacitance increases as the wiring spacing becomes narrower with the miniaturization of elements. This signal transmission delay hinders the performance improvement of the semiconductor device. Therefore, it is necessary to reduce the capacitance between wirings, which is mainly achieved by reducing the dielectric constant of the insulating film.
【０００４】ところが、前述のような従来のＳｉＯ2 膜
は、比誘電率が４〜５（ＢＰＳＧ膜では５程度、Ｏ3 −
ＴＥＯＳ膜では４程度）であり、将来の高速デバイスで
は高すぎる値と考えられている。これに対し、フッ素を
ＳｉＯ2 膜中に含有させることによって比誘電率を下げ
る方法が検討され始めている（Jpn. J. Appl. Phys. Vo
l.33 (1994) pp.408-412, J. Electrochem. Soc., Vol.
140, No.3, March 1993 pp.687-692参照）。これにより
得られるフッ素含有ＳｉＯ2 （ＳｉＯＦ）膜は比誘電率
が３．６程度であってＳｉＯ2 膜のそれに比較して低
い。しかしこのＳｉＯＦ膜を半導体基板上に成膜する技
術は未だ知られていない。However, the conventional SiO 2 film as described above has a relative dielectric constant of 4 to 5 (about 5 for the BPSG film, O 3 −
It is about 4 for a TEOS film), and is considered to be too high for future high speed devices. On the other hand, a method of lowering the relative permittivity by incorporating fluorine into the SiO 2 film has begun to be studied (Jpn. J. Appl. Phys. Vo
l.33 (1994) pp.408-412, J. Electrochem. Soc., Vol.
140, No. 3, March 1993 pp. 687-692). The fluorine-containing SiO 2 (SiOF) film thus obtained has a relative dielectric constant of about 3.6, which is lower than that of the SiO 2 film. However, a technique for forming this SiOF film on a semiconductor substrate has not been known yet.
【０００５】他方、素子の微細化に伴って配線間隔が狭
くなるに従い、配線間の埋め込み性の問題も厳しくなっ
ている。例えばｐ−ＴＥＯＳ膜は、配線間が 0.5μｍ以
下の微細パターンを覆うように成膜すると、ボイドが発
生して平坦化特性が低減するので不適格である。このよ
うに、配線間が0.5 μｍ以下の微細パターンを備えた半
導体装置の製造プロセスについては、比誘電率と埋め込
み性との両性能を満足しうる絶縁膜の形成方法は未確立
の状態である。On the other hand, as the space between the wirings becomes narrower with the miniaturization of elements, the problem of embedding between wirings becomes more severe. For example, if the p-TEOS film is formed so as to cover a fine pattern having a wiring interval of 0.5 μm or less, voids are generated and the planarization characteristic is reduced, so that it is not suitable. As described above, in the manufacturing process of a semiconductor device having a fine pattern of 0.5 μm or less between wirings, a method for forming an insulating film that can satisfy both the relative permittivity and the embedding property has not been established. .
【０００６】[0006]
【発明が解決しようとする課題】そこで本発明は、微細
パターンの埋め込み性に優れ且つ比誘電率が低いフッ素
含有絶縁膜の形成方法を提供することを課題とする。SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a method for forming a fluorine-containing insulating film which is excellent in embedding of fine patterns and has a low relative dielectric constant.
【０００７】[0007]
【課題を解決するための手段】第１の本発明は、オゾン
と、フッ素含有シリコン化合物と、有機シランとを原料
とし常圧熱ＣＶＤ法によりフッ素を含有する酸化ケイ素
質の絶縁膜を半導体基板表面上に堆積することを特徴と
するフッ素含有絶縁膜の形成方法である。第２の本発明
は、原料がさらに硼素源および／またはリン源を含み、
絶縁膜がさらに硼素および／またはリンを含むを含む第
１の本発明のフッ素含有絶縁膜の形成方法である。According to a first aspect of the present invention, a silicon oxide insulating film containing fluorine is prepared by a normal pressure thermal CVD method using ozone, a fluorine-containing silicon compound and an organic silane as raw materials. It is a method for forming a fluorine-containing insulating film, which is characterized in that it is deposited on the surface. 2nd this invention WHEREIN: A raw material further contains a boron source and / or a phosphorus source,
The method for forming a fluorine-containing insulating film according to the first aspect of the present invention, wherein the insulating film further contains boron and / or phosphorus.
【０００８】[0008]
【発明の実施の形態】第１の本発明によれば、絶縁膜の
堆積方法として、Ｏ3 −ＴＥＯＳ膜の形成プロセスであ
る常圧熱ＣＶＤ法を採用したことで、微細パターンに対
する埋め込み性に優れたＳｉＯＦ膜を得ることができ
る。そして、常圧熱ＣＶＤ法に用いる原料のうちフッ素
源として、フッ素含有シリコン化合物を用いたことで、
ＳｉＯ2 膜中にフッ素を容易に含有させることができ、
これにより初めて低誘電率を有するＳｉＯＦ膜を半導体
基板表面上に形成できる。According to the first aspect of the present invention, as the method of depositing the insulating film, the atmospheric pressure thermal CVD method, which is the process of forming the O 3 -TEOS film, is adopted, so that the embedding property for the fine pattern is improved. An excellent SiOF film can be obtained. Then, by using the fluorine-containing silicon compound as the fluorine source among the raw materials used in the atmospheric pressure thermal CVD method,
Fluorine can be easily contained in the SiO 2 film,
As a result, a SiOF film having a low dielectric constant can be formed on the surface of the semiconductor substrate for the first time.
【０００９】フッ素源としてフッ素含有シリコン化合
物、すなわちＳｉ−Ｆ結合を持つ物質を用いることによ
ってのみＳｉＯ2 膜中にフッ素を含有せしめることがで
きる。このことは本発明者らの新知見であり、例えば従
来のように、原料にＯ3 −ＴＥＯＳ−Ｃ2 Ｆ6 （Ｓｉ−
Ｆ結合を持たないフッ素源）を用い常圧熱ＣＶＤ法で半
導体基板表面上にＳｉＯ2 膜を成膜しても、その膜中に
フッ素の含有がほとんど確認できない。Fluorine can be contained in the SiO 2 film only by using a fluorine-containing silicon compound as a fluorine source, that is, a substance having a Si--F bond. This is a new finding of the present inventors. For example, as in the conventional case, the raw material is O 3 -TEOS-C 2 F 6 (Si-
Even if a SiO 2 film is formed on the surface of a semiconductor substrate by a normal pressure thermal CVD method using a fluorine source having no F bond), almost no fluorine content can be confirmed in the film.
【００１０】フッ素源であるフッ素含有シリコン化合物
としては、フッ化ケイ素（ＳｉＦ4）が望ましいが、そ
の他Ｓｉ−Ｆ結合をもつ物質、例えばＳｉＦ（ＯＣ3 Ｈ
5 ） 3 等でも同等の効果が期待できる。有機シラン（Ｓ
ｉ源）としてはＴＥＯＳが好適であるが、この他ＴＥＯ
Ｓと同等の効果を有するテトラメトキシシラン、テトラ
プロポシシラン、トリエトキシシラン、ヘキサエトキシ
ジシロキサン、オクタメチルシクロテトラシロキサン、
トリメトキシシラン、ヘキサメチルシラザン等をＴＥＯ
Ｓに代えて或いはＴＥＯＳと組み合わせて用いることが
できる。Fluorine-containing silicon compound as a fluorine source
As for silicon fluoride (SiFFour) Is desirable, but
Other substances having a Si-F bond, such as SiF (OCThree H
Five ) ThreeEtc., the same effect can be expected. Organosilane (S
TEOS is suitable as the i source), but other than this, TEO
Tetramethoxysilane having the same effect as S, tetra
Propoxysilane, triethoxysilane, hexaethoxy
Disiloxane, octamethylcyclotetrasiloxane,
Trimethoxysilane, hexamethylsilazane, etc.
Can be used instead of S or in combination with TEOS
it can.
【００１１】有機シランの反応室内への導入方法として
は、Ｎ2 やＡｒ等をキャリアガスとしたバブリング法や
噴霧法があり、いずれの方法も本発明に適用できる。な
お、原料の有機シランとフッ素含有シリコン化合物との
混合比は任意に選択可能であり、成膜後の絶縁膜中のフ
ッ素含有量を高めるにはフッ素含有シリコン化合物の割
合を増加させればよい。As a method of introducing the organic silane into the reaction chamber, there are a bubbling method and a spraying method using N 2 or Ar as a carrier gas, and any method can be applied to the present invention. The mixing ratio of the organic silane as a raw material and the fluorine-containing silicon compound can be arbitrarily selected, and the ratio of the fluorine-containing silicon compound may be increased to increase the fluorine content in the insulating film after film formation. .
【００１２】第２の本発明によれば、ＢＰＳＧ膜中にフ
ッ素を含有させることでき、低誘電率のＢＰＳＧ膜を形
成することが可能になる。第２の本発明において、硼素
源としては、ジボラン、トリメチル硼素、トリエチルホ
ウ素、ホウ酸トリメチル、ホウ酸トリエチル等を用いる
ことができ、リン源としては、ホスフィン、トリメチル
ホスフィン、リン酸トリメチル、リン酸トリエチル等を
用いることができる。なお、成膜後の絶縁膜中の硼素、
リンの含有量は、硼素源、リン源の混合比を変えること
で任意に調整できる。According to the second aspect of the present invention, fluorine can be contained in the BPSG film, and a BPSG film having a low dielectric constant can be formed. In the second invention, diborane, trimethylboron, triethylboron, trimethylborate, triethylborate, etc. can be used as the boron source, and phosphine, trimethylphosphine, trimethylphosphate, phosphoric acid can be used as the phosphorus source. Triethyl or the like can be used. In addition, boron in the insulating film after film formation,
The phosphorus content can be arbitrarily adjusted by changing the mixing ratio of the boron source and the phosphorus source.
【００１３】[0013]
【実施例】図１は、本発明の実施に適した成膜装置（常
圧ＣＶＤ装置）の模式図である。図１において、１は反
応室内に原料ガスを導入する給気系、２はシリコン基
板、３はヒータ、４は排気系、５はバブラ、６はマスフ
ローコントローラ、７はオゾン生成器である。EXAMPLE FIG. 1 is a schematic diagram of a film forming apparatus (normal pressure CVD apparatus) suitable for carrying out the present invention. In FIG. 1, 1 is an air supply system for introducing a raw material gas into the reaction chamber, 2 is a silicon substrate, 3 is a heater, 4 is an exhaust system, 5 is a bubbler, 6 is a mass flow controller, and 7 is an ozone generator.
【００１４】半導体基板（本実施例ではシリコン基板）
２はフェイスダウンに保持され、裏面に密着しているヒ
ータ３により加熱される。反応室内の圧力は、給気系１
の給気速度と排気系４の排気速度とによりコントロール
される。原料ガスのうち有機シラン（本実施例ではＴＥ
ＯＳを使用）は、バブラ５に封入されキャリアガス（本
実施例ではＮ2 を使用）でバブリングすることによって
反応室内に導入される。フッ素含有シリコン化合物（本
実施例ではＳｉＦ4 を使用）およびオゾンは直接反応室
内に導入される。フッ素含有シリコン化合物、オゾンお
よびキャリアガスの流量はそれぞれマスフローコントロ
ーラ６により制御される。なお、オゾンはオゾン生成器
７により生成される。 ＜実施例１＞図１に示した成膜装置を用いてＯ3 −ＴＥ
ＯＳ膜にフッ素を含有させた第１の本発明の実施例（実
施例１）を開示する。Semiconductor substrate (silicon substrate in this embodiment)
2 is held face down and heated by the heater 3 which is in close contact with the back surface. The pressure in the reaction chamber is 1
It is controlled by the supply speed of the air and the exhaust speed of the exhaust system 4. Organosilane (TE in this example)
(OS is used) is introduced into the reaction chamber by being enclosed in the bubbler 5 and bubbling with a carrier gas (N 2 is used in this embodiment). The fluorine-containing silicon compound (SiF 4 is used in this embodiment) and ozone are directly introduced into the reaction chamber. The flow rates of the fluorine-containing silicon compound, ozone and carrier gas are controlled by the mass flow controller 6, respectively. The ozone is generated by the ozone generator 7. Example 1 O 3 -TE was formed using the film forming apparatus shown in FIG.
A first embodiment (Example 1) of the present invention in which the OS film contains fluorine will be disclosed.
【００１５】シリコン基板２をヒータ３により４００℃
に加熱保持し、排気系４により反応室圧を４００Ｔｏｒ
ｒとし、給気系１を働かせて、ＴＥＯＳのキャリアガス
であるＮ2 （Ｎ2<TEOS> と記す）を０〜３５０sccm（標
準ｍ3 ／ｍｉｎ）、ＳｉＦ4を０〜３５０sccmの範囲で
変化させ、オゾン発生器７によりオゾンを約８wt％含ま
せた酸素を５０００sccm定流量で、それぞれ導入した。
なお、Ｎ2<TEOS> ：０sccmおよびＳｉＦ4 ：０sccmなる
流量の場合は本発明に属さないが比較基準として実施し
た。The silicon substrate 2 is heated to 400 ° C. by the heater 3.
The temperature of the reaction chamber is maintained at 400 ° C by the exhaust system 4
r, and the air supply system 1 is operated to change N 2 (N 2 <TEOS>), which is a carrier gas of TEOS, in the range of 0 to 350 sccm (standard m 3 / min) and SiF 4 in the range of 0 to 350 sccm. Then, oxygen containing about 8 wt% of ozone was introduced at a constant flow rate of 5000 sccm by the ozone generator 7.
The flow rates of N 2 <TEOS>: 0 sccm and SiF 4 : 0 sccm are not included in the present invention, but were used as a comparison standard.
【００１６】この常圧熱ＣＶＤ法により、ヒータ３から
供給される熱エネルギーで原料ガスが分解され、特にＴ
ＥＯＳとオゾンとが反応室中で反応し、シリコン基板２
上にフッ素を含有するＳｉＯ2 膜が堆積する。なお、Ｓ
ｉＯ2 膜中のフッ素の含有量は、ＸＰＳ（X-ray Photoe
lectron Spectroscopy）析法による分析値である（以下
同じ）。By this atmospheric pressure thermal CVD method, the source gas is decomposed by the thermal energy supplied from the heater 3, and in particular T
EOS and ozone react in the reaction chamber, and silicon substrate 2
A SiO 2 film containing fluorine is deposited on top. Note that S
The fluorine content in the io 2 film is determined by XPS (X-ray Photoe
lectron Spectroscopy) The value analyzed by the analysis method (the same applies below).
【００１７】図２は、実施例１に係るＳｉＯＦ膜中のフ
ッ素含有量（at％；以下同じ）のＳｉＦ4 ／（ＳｉＦ4
＋Ｎ2<TEOS> ）流量比依存性を示すグラフである。な
お、ＳｉＦ4 流量とＮ2<TEOS> 流量との和は３５０sccm
と一定にした。図２に示すように、本発明に従いＳｉＦ
4 をフッ素源として使用することにより、Ｏ3 −ＴＥＯ
Ｓ膜中にフッ素を含有させることができる。FIG. 2 shows SiF 4 / (SiF 4 ) having a fluorine content (at%; the same applies hereinafter) in the SiOF film according to Example 1.
+ N 2 <TEOS>) A graph showing the flow ratio dependency. The sum of the SiF 4 flow rate and the N 2 <TEOS> flow rate is 350 sccm.
And made it constant. As shown in FIG. 2, according to the present invention, SiF
By using 4 as a fluorine source, O 3 -TEO
Fluorine can be contained in the S film.
【００１８】図３は、実施例１に係るＳｉＯＦ膜につい
て比誘電率のフッ素含有量依存性を示すグラフである。
従来のＳｉＯ2 膜では比誘電率の下限が３．９程度であ
ることが知られている。これに対し、第１の本発明によ
れば、図３から明らかなように、比誘電率をフッ素含有
量４at％で３．４程度、フッ素含有量14at％では２．９
程度にまで低下でき、比誘電率の低いＳｉＯＦ膜が得ら
れる。 ＜実施例２＞次に、ＢＰＳＧ膜にフッ素を含有させた第
２の本発明の実施例（実施例２）を開示する。FIG. 3 is a graph showing the fluorine content dependency of the relative dielectric constant of the SiOF film according to Example 1.
It is known that the lower limit of the relative permittivity of the conventional SiO 2 film is about 3.9. On the other hand, according to the first aspect of the present invention, as is clear from FIG. 3, the relative dielectric constant is about 3.4 at a fluorine content of 4 at% and 2.9 at a fluorine content of 14 at%.
A SiOF film having a low relative dielectric constant can be obtained. <Embodiment 2> Next, a second embodiment (Embodiment 2) of the present invention in which fluorine is contained in the BPSG film will be disclosed.
【００１９】成膜装置および基本的な成膜方法は実施例
１と同様である。ただし、硼素源、リン源ともにＮ2 を
キャリアガスとするバブリング法により、それぞれ流量
２５sccmで反応室内に導入した。なお、硼素源としてホ
ウ酸トリメチル（ＴＭＢ：Ｂ（ＯＣＨ3 ）3 ）を、リン
源としてリン酸トリメチル（ＴＭＰ：ＰＯ（ＯＣＨ3）
3 ）を、それぞれ使用した。The film forming apparatus and the basic film forming method are the same as in the first embodiment. However, both the boron source and the phosphorus source were introduced into the reaction chamber at a flow rate of 25 sccm by a bubbling method using N 2 as a carrier gas. In addition, trimethyl borate (TMB: B (OCH 3 ) 3 ) as a boron source and trimethyl phosphate (TMP: PO (OCH 3 )) as a phosphorus source
3 ) were used respectively.
【００２０】図４は、実施例２に係るＳｉＯＦ膜中のフ
ッ素含有量（at％；以下同じ）のＳｉＦ4 ／（ＳｉＦ4
＋Ｎ2<TEOS> ）流量比依存性を示すグラフである。な
お、ＳｉＦ4 流量とＮ2<TEOS> 流量との和は３５０sccm
と一定とした。図４から明らかなように、ＳｉＦ4 をフ
ッ素源として使用すると、ＢＯＳＧ膜中にもフッ素を含
有させることができる。FIG. 4 shows the SiF 4 / (SiF 4 ) of the fluorine content (at%; the same applies hereinafter) in the SiOF film according to the second embodiment.
+ N 2 <TEOS>) A graph showing the flow ratio dependency. The sum of the SiF 4 flow rate and the N 2 <TEOS> flow rate is 350 sccm.
And fixed. As is clear from FIG. 4, when SiF 4 is used as a fluorine source, the BOSG film can also contain fluorine.
【００２１】図５は、実施例２に係るＳｉＯＦ膜につい
て比誘電率のフッ素含有量依存性示すグラフである。従
来のＢＰＳＧ膜では比誘電率の下限が５程度であること
が知られている。これに対し、第２の本発明によれば、
図５から明らかなように、比誘電率をフッ素含有量４at
％で４．６程度、フッ素含有量14at％では４．３程度に
まで低下でき、比誘電率の低いＢＰＳＧ膜が得られる。FIG. 5 is a graph showing the fluorine content dependence of the relative dielectric constant of the SiOF film according to Example 2. It is known that the lower limit of the relative permittivity of the conventional BPSG film is about 5. On the other hand, according to the second invention,
As is clear from FIG. 5, the relative dielectric constant was determined to be 4 at.
%, The fluorine content can be lowered to about 4.3, and the fluorine content can be lowered to about 4.3, and a BPSG film having a low relative dielectric constant can be obtained.
【００２２】[0022]
【発明の効果】本発明によれば、オゾンおよびフッ化ケ
イ素、ならびにテトラエトキシシラン等の有機シランを
原料とする常圧熱ＣＶＤ法によりＳｉＯＦ膜を堆積する
ことにより、微細パターンの埋め込み性に優れ且つ比誘
電率が低いフッ素含有絶縁膜が形成できるという優れた
効果を奏する。According to the present invention, the SiOF film is deposited by the atmospheric pressure thermal CVD method using ozone, silicon fluoride, and an organic silane such as tetraethoxysilane as a raw material, so that the fine pattern embedding property is excellent. In addition, it has an excellent effect that a fluorine-containing insulating film having a low relative dielectric constant can be formed.
【図１】本発明の実施に適した成膜装置の模式図であ
る。FIG. 1 is a schematic view of a film forming apparatus suitable for implementing the present invention.
【図２】実施例１に係るＳｉＯＦ膜中のフッ素含有量の
ＳｉＦ4 ／（ＳｉＦ4 ＋Ｎ2<TEOS> ）流量比依存性を示
すグラフである。2 is a graph showing the SiF 4 / (SiF 4 + N 2 <TEOS>) flow ratio dependency of the fluorine content in the SiOF film according to Example 1. FIG.
【図３】実施例１に係るＳｉＯＦ膜について比誘電率の
フッ素含有量依存性を示すグラフである。FIG. 3 is a graph showing the fluorine content dependency of the relative dielectric constant of the SiOF film according to Example 1.
【図４】実施例２に係るＳｉＯＦ膜中のフッ素含有量の
ＳｉＦ4 ／（ＳｉＦ4 ＋Ｎ2<TEOS> ）流量比依存性を示
すグラフである。FIG. 4 is a graph showing the SiF 4 / (SiF 4 + N 2 <TEOS>) flow ratio dependency of the fluorine content in the SiOF film according to Example 2.
【図５】実施例２に係るＳｉＯＦ膜について比誘電率の
フッ素含有量依存性示すグラフである。FIG. 5 is a graph showing the fluorine content dependency of the relative dielectric constant of the SiOF film according to Example 2.
１ 給気系 ２ シリコン基板 ３ ヒータ ４ 排気系 ５ バブラ ６ マスフローコントローラ ７ オゾン生成器 1 Air Supply System 2 Silicon Substrate 3 Heater 4 Exhaust System 5 Bubbler 6 Mass Flow Controller 7 Ozone Generator
Claims (2)
と、有機シランとを原料とし常圧熱ＣＶＤ法によりフッ
素を含有する酸化ケイ素質の絶縁膜を半導体基板表面上
に堆積することを特徴とするフッ素含有絶縁膜の形成方
法。1. A fluorine-containing silicon oxide insulating film is deposited on the surface of a semiconductor substrate by atmospheric pressure CVD using ozone, a fluorine-containing silicon compound and an organic silane as raw materials. Method of forming inclusion insulating film.
源を含み、絶縁膜がさらに硼素および／またはリンを含
む請求項１記載のフッ素含有絶縁膜の形成方法。2. The method for forming a fluorine-containing insulating film according to claim 1, wherein the raw material further contains a boron source and / or a phosphorus source, and the insulating film further contains boron and / or phosphorus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8102546A JPH09293716A (en) | 1996-04-24 | 1996-04-24 | Forming method of insulating film containing fluorine |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8102546A JPH09293716A (en) | 1996-04-24 | 1996-04-24 | Forming method of insulating film containing fluorine |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09293716A true JPH09293716A (en) | 1997-11-11 |
Family
ID=14330255
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8102546A Pending JPH09293716A (en) | 1996-04-24 | 1996-04-24 | Forming method of insulating film containing fluorine |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09293716A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001041203A1 (en) * | 1999-11-30 | 2001-06-07 | Intel Corporation | Improved flourine doped sio2 film |
| EP1123991A2 (en) * | 2000-02-08 | 2001-08-16 | Asm Japan K.K. | Low dielectric constant materials and processes |
| US6905981B1 (en) | 2000-11-24 | 2005-06-14 | Asm Japan K.K. | Low-k dielectric materials and processes |
-
1996
- 1996-04-24 JP JP8102546A patent/JPH09293716A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001041203A1 (en) * | 1999-11-30 | 2001-06-07 | Intel Corporation | Improved flourine doped sio2 film |
| GB2373372A (en) * | 1999-11-30 | 2002-09-18 | Intel Corp | Improved flourine doped sio2 film |
| GB2373372B (en) * | 1999-11-30 | 2004-04-28 | Intel Corp | Improved flourine doped sio2 film |
| EP1123991A2 (en) * | 2000-02-08 | 2001-08-16 | Asm Japan K.K. | Low dielectric constant materials and processes |
| EP1123991A3 (en) * | 2000-02-08 | 2002-11-13 | Asm Japan K.K. | Low dielectric constant materials and processes |
| US6733830B2 (en) | 2000-02-08 | 2004-05-11 | Asm Japan K.K. | Processes for depositing low dielectric constant materials |
| US7144620B2 (en) | 2000-02-08 | 2006-12-05 | Asm Japan K.K. | Process for depositing low dielectric constant materials |
| US7544827B2 (en) | 2000-02-08 | 2009-06-09 | Asm Japan K.K. | Process for depositing low dielectric constant materials |
| US6905981B1 (en) | 2000-11-24 | 2005-06-14 | Asm Japan K.K. | Low-k dielectric materials and processes |
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