JPH09293386A - Storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a storage device in which the bias in the access frequency of a storage cell in a storage section is removed and by which an access can be conducted uniformly by the whole storage section and the lifetime of the whole system can be lengthened. SOLUTION: This device has a storage section 1 consisting of a large number of storage cells, an address random translation section 5 translating an external address AO on the basis of address translation conditions and outputting a translated address AR, and an address decoder 6 decoding the translated address AR to an internal address AIR. The accessed storage cells differ even when the external address AO is the same by changing the address translation conditions of the address random translation section 5 when a specified signal such as the signals of erase demand and initialization demand is input in the address translation conditions. Accordingly, even when there are the deflection properties of an access to a lowermost-order address in the external address AO, the deflection of the access frequency of the storage cells in the storage section 1 is eliminated, and the access is conducted uniformly by the whole storage section 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device, and more particularly to a storage device which is non-volatile and electrically erasable / electrically rewritable, and is limited in the number of times of rewriting and the number of times of reading access.

[0002]

2. Description of the Related Art As a conventional storage device, there is a non-volatile electrically erasable / electrically rewritable semiconductor storage device which sequentially writes and reads information such as voice and images. This storage device has a limit in the number of times of access such as the number of times of rewriting and the number of times of reading.

FIG. 5 is a block diagram showing the structure of a conventional storage device. In FIG. 5, 11 is a storage unit including a large number of storage cells, 12 is a control unit, 13 is a data bus control unit,
16 is an address decoder. In conventional storage device, it decodes the address signal A _O input from the external by the address decoder 16, and outputs to the storage unit 11 as the internal address signal A _I, the storage unit 11, corresponding to the internal address signal A _I Select a memory cell. At this time, if the external control signal S _C is a read request, the data D _OUT is output from the selected memory cell to the outside via the data bus control unit 13 and the data bus. At this time, if the external control signal S _C is a write request,
The data D _IN from the outside is written to the selected memory cell via the data bus control unit 13 and the data bus.

[0004]

SUMMARY OF THE INVENTION In the above conventional configuration,
Since the address decoder 16 uniquely converts the address signal A _O from the outside of the storage device, even if the access frequency from the outside of the storage device is deviated, it is possible to access the storage device while maintaining the same deflection. Become. Specifically, when accessing the storage device from outside the storage device, the storage unit 1 is usually accessed in order from the lowest address.
It is extremely unusual to use all the memory cells of 1 and the frequency of accessing the memory cell of the highest address is very close to 0. As described above, although the access frequency of the storage cell at the highest address and the access frequency of the storage cell at the lowest address are significantly different from each other, they are used while maintaining the bias of the access frequency. Therefore, when the memory cell of the storage unit 11 has a limited access to the number of rewrites and the number of read times, the storage cell at the lowest address reaches the limit of the limit earliest, and the storage cell at the higher address from the perspective of the storage unit 11 as a whole. There was a problem that the whole system became unusable though there was room.

An object of the present invention is to provide a storage device which can eliminate the bias of access frequency of storage cells in the storage unit, can perform uniform access in the entire storage unit, and can prolong the life of the entire system. Is.

[0006]

According to a first aspect of the present invention, there is provided a storage device comprising: a storage portion including a plurality of storage cells each having an internal address assigned thereto; and an external address input from the outside based on an address conversion condition. An address random conversion unit that converts and outputs a converted address and an address decoder that decodes the converted address output from the address random conversion unit into an internal address are provided, and the address conversion condition of the address random conversion unit is changed by a predetermined signal. It is characterized by doing so.

According to this configuration, the address random conversion unit decodes the converted address obtained by converting the external address based on the address conversion condition into the internal address by the address decoder, and a predetermined signal such as an erase request or By changing the address conversion condition when the initialization request signal is input, the memory cells accessed will be different even if the external address is the same. Therefore, even if the external address has the bias of accessing the lowest address, the memory cell selected for the same external address is different every time the address conversion condition is changed, and therefore the memory cell in the memory unit Unbiased access frequency can be eliminated, and uniform access can be performed in the entire storage unit. As a result, the total number of accesses up to the limit of access limits for rewriting and reading can be improved, and the life of the entire system can be extended. it can. While the address conversion conditions are the same, the same memory cell corresponds to the same external address, and the external address used during writing and the external address used during reading uniquely correspond.

According to a second aspect of the present invention, in the storage device according to the first aspect, the address random conversion unit is a PN.
The code is used to generate the address conversion condition, and the exclusive OR of the generated address conversion condition and the external address is output as the conversion address. With this configuration, the address conversion condition is automatically set to a predetermined signal,
For example, it is updated when an erase request or an initialization request is input.

According to a third aspect of the present invention, in the storage device according to the first aspect, the address random conversion unit is set with an address conversion condition from the outside, and the set address conversion condition and the external address are exclusive. The logical sum is output as the conversion address. With this configuration, the address conversion condition can be arbitrarily set from the outside.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described with reference to the drawings. 1 is a block diagram showing the configuration of a storage device according to a first embodiment of the present invention. In FIG. 1, reference numeral 1 is a storage unit including a large number of storage cells, 2 is a control unit, 3 is a data bus control unit, 4 is an address latch unit, 5 is an address random conversion unit, and 6 is an address decoder. Further, A _O is an external address signal input from the outside, A _R is a translated address signal converted by the address random converter 5, _AIR is an internal address signal obtained by decoding the translated address signal A _R , and S _C is an external signal. Control signals such as a read request, a write request, an erase request, and an address confirmation timing signal from _SLA, an address latch control signal, and _SCK are timing signals for updating the address conversion conditions of the address random conversion unit 5. Depending on the storage device, the address latch control signal may be directly applied from the outside. In this case, the address latch control signal (address determination timing signal) becomes S _LA .

This storage device is characterized in that an address random conversion unit 5 and an address latch unit 4 are mainly provided. In this storage device, the address signal A _O input from the outside is latched by the address latch unit 4 at the timing controlled by the address latch control signal S _LA ,
It is output to the address random conversion unit 5. The address random conversion unit 5 randomly converts the address signal A _O input from the address latch unit 4 and outputs it as a converted address signal A _R to the address decoder 6. The address decoder 6 decodes the converted address signal A _R from the address random conversion unit 5 and outputs it as the internal address signal A _IR to the storage unit 1. The memory unit 1 selects a memory cell corresponding to the internal address signal _AIR .

At this time, when the external control signal S _C is a read request, the selected memory cell outputs the data D _OUT to the outside via the data bus control unit 3 and the data bus. At this time, if the external control signal S _C is a write request, the external data D _IN is written to the selected memory cell via the data bus control unit 3 and the data bus.

FIG. 2 is a circuit diagram showing the configuration of the address random conversion unit 5. In FIG. 2, 7 is an exclusive OR circuit, 8 is a D flip-flop, 9 is an exclusive OR NOT circuit, and 10 is a shift register composed of the D flip-flop 8. In FIG. 2, the external address signal A _O of FIG. 1 is used as a 9-bit signal to configure the address random conversion unit 5, and the address signal A _O input from the address latch unit 4 to the address random conversion unit 5 is A0 ′. ~ A
8 ', and the converted address signal A _R output from the address random conversion unit 5 to the address decoder 6 is A0 to A8.
Is equivalent to

[0014] Address random transformation unit 5 are input to the address signal A0'～A8 'is by the respective exclusive OR circuit 7, an exclusive logical address conversion conditions a ₀ ~a ₈ held in the shift register 10 The sum operation is performed to become address signals A0 to A8, which are output from the address random conversion unit 5. This transformation corresponds uniquely. Therefore, the address signals A0 'to A8' and the address signal A
Each of 0 to A8 has a one-to-one correspondence with each other. For example, when accessing the same memory cell at the time of writing and reading, the external address signal A _O coincides with each other. However, if the address conversion conditions a _{0 to} a ₈ are changed, the address signals A0 ′ to A
8 'respectively one-to-one correspondence with the address signal A0~A8 is, but each of the corresponding address conversion conditions a ₀ ~a ₈
It will be different from before the change.

The timing of updating the address conversion conditions a _{0 to} a ₈ corresponds to the clock which is the timing signal S _CK input from the control unit 2. When the control unit 2 receives the control signal S _C of the erase request or the initialization request from the external device, it outputs the timing signal S _CK to the address random conversion unit 5. As a result, the shift register 10 is updated, and new address translation conditions a _{0 to} a ₈ are set.

An exclusive-or negation circuit 9 connected to the output of the shift register 10 produces a new input of the shift register 10. A circuit including the shift register 10 and the exclusive OR negation circuit 9 is a PN (Pseudo-N).
This is a well-known code generating circuit, and in the case of the 9-bit shift register 10, all the states except the state in which the address conversion conditions a _{0 to} a ₈ are all “1”, that is, (2 ⁹ -1) State = 511 State 1
It is known that it makes a transition from time to time and returns to the original state again. Although the case of 9 bits is shown here, a PN code generation circuit that circulates similarly in a state of other number of bits is known.

Tables 1 to 4 show address conversion conditions a _{0 to} a.
Address signals A0 'to A8' corresponding to the first three states of ₈ and the last 511th state, respectively.
And the address signals A0 to A8.

[0018]

[Table 1]

In this state 1, A8'-A0 '= A8-A
0, that is, the address signals A0 'to A8' become the address signals A0 to A8 as they are.

[0020]

[Table 2]

[0021]

[Table 3]

[0022]

[Table 4]

As described above, according to this embodiment, the erase request is accepted even if the address signal A _O (A0 'to A8') from the outside is biased to be accessed in order from the lowest address. Address conversion condition a ₀ of the address random conversion unit 5 when the initialization request is accepted
By changing the ~a _8, usage of the actual memory cells in the memory unit 1 becomes random, without deflection of the access frequency of the memory cell, it is possible to perform uniform access across storage unit 1, as a result It is possible to improve the total number of accesses up to the limit of the number of times of rewriting and reading, and extend the life of the entire system. For example, the average usage rate of the storage cells is 50% until one erase operation is requested, that is, until the address conversion condition is updated.
Then the life of the entire system is doubled.

FIG. 3 is a block diagram showing the configuration of a storage device according to the second embodiment of the present invention. In FIG. 3, 4
Is an address latch unit, 5 is an address random conversion unit, 1
Reference numeral 1 is a storage unit composed of a large number of storage cells, 12 is a control unit, 1
3 is a data bus control unit, 16 is an address decoder, 17
Is a conventional storage device. Further, A _O is an external address signal, A _R is an address signal changed by the address random conversion unit 5, and S _C is a control signal such as an external read request, write request, erase request, and address confirmation timing signal. , S _LA is an address latch control signal, and S _CK is a timing signal for updating the address conversion condition of the address random conversion unit 5.

This storage device is similar to the conventional storage device 17,
An address latch unit 4 and an address random conversion unit 5 similar to those in FIG. 1 are provided. The operation of this storage device is similar to the operation of the storage device of FIG. According to this embodiment, by adding the minimum necessary circuit configuration of the address latch unit 4 and the address random conversion unit 5, the conventional storage device 17 can be used as it is,
There is an effect that it is possible to improve the number of times of rewriting of a semiconductor memory device, which is characteristically limited in the number of times of rewriting and accessing the number of times of reading.

Although the address random converter 5 shown in FIG. 2 is used in the first and second embodiments,
The address random conversion unit 5 may have a circuit configuration as shown in FIG. The address random conversion unit 5 of FIG. 4 inputs the address conversion data signals D0 to D8 from the outside to the input of each D flip-flop ₈ and updates the address conversion conditions a _{0 to} a ₈ at the same timing as in FIG. ,
Determined by timing signal S _CK . In the address random conversion unit 5 of FIG. 4, the address conversion conditions a _{0 to} a are generated according to the address conversion data signals D0 to D8 input from the outside.
₈ can be controlled arbitrarily.

Further, in the first and second embodiments described above, the case where all of the address A _O is randomly converted is shown, but it is also effective to apply it to a part of the address A _O. For example, in the upper 9 bits of an 18-bit address,
The address random conversion unit 5 is applied and the lower 9 bits are left as they are. In this case, 5 of 9-bit space
It is divided into 512 banks of upper 9 bits of 12 cells. If the sequential data has a certain chunk, it is more convenient than converting all randomly.

[0028]

According to the storage device of the present invention, the address random converter converts the external address based on the address conversion condition, and the address decoder decodes the converted address into the internal address. By changing the address conversion condition when the erase request signal or the initialization request signal is input, the memory cells to be accessed are different even if the external address is the same. Therefore, even if the external address has the bias of accessing the lowest address, the memory cell selected for the same external address is different every time the address conversion condition is changed, and therefore the memory cell in the memory unit Unbiased access frequency can be eliminated, and uniform access can be performed in the entire storage unit. As a result, the total number of accesses up to the limit of access limits for rewriting and reading can be improved, and the life of the entire system can be extended. it can.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a storage device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of an address random conversion unit according to the embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a storage device according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing another configuration of the address random conversion unit in the embodiment of the present invention.

FIG. 5 is a block diagram illustrating a configuration of a conventional storage device.

[Explanation of symbols]

 1, 11 storage unit 2, 12 control unit 3, 13 data bus control unit 4 address latch unit 5 address random conversion unit 6, 16 address decoder

Claims (3)

[Claims] 1. A storage unit comprising a large number of storage cells each having an internal address, an address random conversion unit for converting an external address input from the outside based on an address conversion condition, and outputting the converted address. A memory comprising: an address decoder that decodes a translation address output from the address random translation unit into the internal address, and the address translation condition of the address random translation unit is changed by a predetermined signal. apparatus. 2. The address random conversion unit generates an address conversion condition by using a PN code, and outputs an exclusive OR of the generated address conversion condition and an external address as a conversion address. 1. The storage device according to 1. 3. The address random conversion unit is set with an address conversion condition from the outside, and outputs an exclusive OR of the set address conversion condition and the external address as a conversion address. Storage device.