JPH09292879A - Digital signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an acoustic effect adder capable of speeding up program switching when plural acoustic effects are added. SOLUTION: A program to be stored in a command ROM 2a is constituted so that plural sets of a main routine and an acoustic effect addition routine are stored, address data stored in a coefficient RAM 2c is latched when effects are switched from the outside, and further start address data is set to a program counter 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processor used in a sound effect adding device for adding a plurality of sound effects.

[0002]

2. Description of the Related Art A sound effect adding apparatus using a so-called DSP (digital signal processor) is disclosed in Japanese Patent Laid-Open No.
As shown in No. 8-50595, some DSPs add a plurality of acoustic effects in a time division manner.

[0003]

Originally, in the above-mentioned configuration, the main operation circuit such as the CPU is operated by D
The corresponding program is transferred to the SP, and all of the programs are switched as they are. Moreover, since the transfer of the program is serial transfer by handshake, the transfer speed is slow and the transfer time becomes long as a result. . Further, in consideration of control of other configurations in the system, if the transfer speed is too slow, the number of DSPs that can be simultaneously used is naturally limited, and thus the number of acoustic effects that can be added is limited. There was also a problem that musical expressions were limited based on technical limits.

The present invention was devised to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide a sound effect adding device capable of speeding up program switching when a plurality of sound effects are added. Is.

[0005]

Therefore, the digital signal processor of the present invention can store a non-volatile program memory in which a plurality of different completed processing programs are individually stored, and coefficient data used by the processing programs. Has a volatile coefficient memory, a presettable program counter, and an address register for supplying a preset address to the program counter. The address register is set to a specific value by a reset process and can be changed externally. Is a basic feature.

In this configuration, the basic effect processing program is converted into a mask ROM and used as an instruction program (nonvolatile program memory), so that the information transferred from the external main arithmetic circuit at the time of effect switching is smaller than that in the prior art. Remarkably less. Regarding the address register that supplies the preset address to the program counter,
A specific value is set by the reset process, and the configuration that can be changed from the outside is such that all effect programs stored in the mask ROM can be randomly accessed to add an acoustic effect. This is because the desired effect treatment can be selected by reducing the limitation of.

Further, in the above structure, it is preferable that the address register can transfer the contents of the coefficient memory. With this configuration, crossfade envelope processing can be regarded as one of the effects and can be processed by a program without providing a special external circuit, thereby reducing noise at the time of effect switching. However, it is not necessary to increase the number of parts.

According to another aspect of the digital signal processor of the present invention, a nonvolatile first program memory internally storing a plurality of different processing programs, a second program memory rewritable from the outside, and these It is characterized in that it has a program counter for controlling the addresses of the first and second program memories in common, and the program counter first activates the second program memory in a reset process.

In the above configuration, the basic effect processing program is masked into a ROM and used as a part of the instruction program (nonvolatile first program memory) (the program memory is externally rewritable RAM and fixed ROM). The information transferred from the external main arithmetic circuit at the time of effect switching is much smaller than the conventional one (because mainly transferred information to the second program memory). . Note that the program counter is configured to activate the second program memory first in the reset process while processing the program memory composed of the RAM and the ROM in the same row. The effect program to
Since it is not a general-purpose one but is selected according to the type of acoustic effect to be added (main routine of subprogram method and sub-routine to be described later, etc.), it has a high priority when used. It is necessary to do so.

Further, it is usual that the capacity of the second program memory is significantly smaller than the number of steps that can be processed at the sampling frequency of the input signal. As shown in FIG. 3 described later, the processing of the DSP main routine is only to control how to pass the input musical tone signal to two effect programs, and for example, one sampling of the DSP. If the number of steps that can be processed is 500, the main routine is 60 steps, and the sound effect addition routine f
1: 220 step, sound effect addition routine f2: 22
With 0 steps, the total is about 500 steps.
Of course, there are some types of effects that require about 220 steps and the processing is completed in about 100 steps. However, in order to hold the L / R input / output timing, which will be described later, wait about 200 steps. I try to return.

According to another aspect of the digital signal processor of the present invention, a non-volatile program memory internally storing a plurality of different completed processing programs and coefficient data fixedly used by the processing programs are individually stored. It has a non-volatile first coefficient memory and a volatile second coefficient memory which jointly stores rewritable coefficient data used by the processing program, and the second coefficient memory is under reset processing or before reset processing. It is characterized by being written from the outside.

In the above structure, not only the basic effect processing program is converted into the mask ROM to be used as the instruction program (nonvolatile program memory), but also the coefficient data fixedly used by the processing program is stored in the nonvolatile first coefficient. Since they are individually stored in the memory, the information transferred from the external main arithmetic circuit at the time of effect switching (being mainly transferred information to the second counting memory) is much smaller than in the conventional case.

According to a sixth aspect of the present invention, there is provided a digital signal processor in which a plurality of different and completed processing programs are individually stored in a nonvolatile first program memory, an externally rewritable second program memory, and the processing. A non-volatile first coefficient memory that individually stores coefficient data that is fixedly used by a program; and a volatile second coefficient memory that jointly stores rewritable coefficient data that is used by the processing program; And a program counter that controls the addresses of the first and second program memories in common, the program counter first starts the second program memory in the reset process, and the second coefficient memory is in the reset process or It is characterized by being written from the outside before that. This is the same as the configuration of the processing program portion of claim 3 in the configuration of the processing program portion of the configuration of claim 5 described above.

Coefficient data for adding an envelope to the value processed at the output stage of each processing program is
It is preferable to store the coefficient in the coefficient memory and lower the envelope once when the processing program is switched. With such a configuration, an incorrect value at the time of switching will not be output.

[0015]

FIG. 1 is a block diagram of an electronic musical instrument having an embodiment of a sound effect adding apparatus constructed using the digital signal processor of the present invention. In the figure, reference numeral 100 designates a panel operator / panel operation display block, which captures the contents operated by the user (player) on the panel of the electronic musical instrument, and at the same time, based on a command from a master CPU 10 described later. The state of the electronic musical instrument (for example, the state of effect connection) is displayed. The key switch block 101 takes in the on / off information of the key switch together with the key velocity, and outputs the master CP.
Send to U10. The MIDI input / output block 102 outputs the contents processed by the master CPU 10 (various kinds of information such as key-on / off, tone color number change, effect change, etc.), and sends the MIDI input information to the master CPU 10. The FD input / output block 103 stores various types of information (performance information, panel registration information, effect information, etc.) possessed by the master CPU 10 in an external storage medium such as a flexible disk or reads it from there. RA
M104 is a working RAM of the master CPU 10 and at the same time a storage area for automatic performance patterns and automatic accompaniment patterns. The ROM 105 is the master CPU 10
At the same time as storing the above program, in the case of the configuration of the embodiment of claim 3, a DSP program to be described later is stored (of course, the DSP program is read from an external storage medium and stored in the RAM 104). It is possible to put it). On the other hand, the coefficient data used for various effect programs of the DSP are also stored in the ROM 105. The ROM 105 can be replaced with a flash memory or the like. In the configuration of the embodiment, the master CPU 10 constitutes the main arithmetic circuit of the present invention that controls all of the electronic musical instruments, and performs panel initialization after power-on, R
Initial setting of AM 104 and initial setting of DSP 1 (initial loader) described later are also performed. When the tone color is changed on the panel, the corresponding parameter is set to the tone generator circuit 1 described later.
If the key is turned on and off, the state of the corresponding CH of the tone generator circuit 106 is updated based on the assignment result. Furthermore, when a new effect is selected or a new effect connection is selected on the panel, the corresponding program stored in the ROM 105 (however, only the coefficient data in the case of connection change as described later) and the coefficient Data to DSP
Transfer to 1. The tone generator circuit 106 is the master CPU 1
32DCO (digital
Controlled oscillator) can be produced, and the waveform generation method is not particularly limited. For example, the PCM waveform readout method or the sine synthesis method is used. The 32 sounds created here are multiplied by independent mix rates for the two output sequences, and then 32DC for each sequence.
O is added and output from OUT1 and OUT2. The outputs of OUT1 and OUT2 are serial stereo outputs and conform to the CDF format generally used for CDs (compact discs). Therefore, these outputs OUT1 and OUT2 are
The input format of the DAC (digital-analog converter) 107a or 107b is the same as that of the DAC 107a to 107b as long as the data is mixed without going through 1.
It can be directly connected to 07b.

The DSP 1 is an external RAM (for example, 1 Mbi).
Under control of tDRAM × 2), various sound effects are added to the tone signal. The DSP 1 has two inputs and two outputs, each of which is a stereo signal. The internal configuration of the DSP is as shown in FIG. 2 as the configuration of one embodiment of claim 1, and the instruction RO corresponding to the internal instruction storage unit is provided.
Based on the program stored in the M2a and the coefficient data transferred from the master CPU 10 and stored in the coefficient RAM 2b, a plurality of effects can be obtained within one sample time (about 44.1 KHz) for the tone signal stored in the data RAM 2c. The additional program is time-shared. That is, instruction ROM
As shown in the figure, the program stored in 2a is configured by storing a plurality of sets of a main routine and a sound effect addition routine, and a coefficient RAM 2c (may be other data RAM) when switching the effect from the outside.
The address data stored in the start address data is latched as the start address data (the master CPU 10 may immediately write the start address data). When DSP1 reaches the end of the current program, it issues an instruction to perform a vector jump there. When the decoder receives the vector jump, it outputs the corresponding address of the coefficient RAM 2c to the C bus at that timing, and the start address data is loaded at the next timing. The address is loaded as it is into the program counter, and at the next timing, the instruction ROM 2a is accessed by the address to shift to a new effect program. In this way, the effect program is decoded by the decoder and the control in the DSP is performed. On the other hand, the tone signal input from the tone generator circuit 106 is stored in the data RAM 2c,
As described above, the coefficient data transferred from the master CPU 10 is stored in the coefficient RAM 2b. Then, the coefficient data is sequentially stored in the C register 3a and the data of the tone signal is sequentially stored in the D register 3b by the control command, and the product of both registers is obtained by the multiplier 4 and temporarily stored in the P register 5. The multiplication value is added by the adder 6 together with the previous addition value stored in the Y register 7 and returned through the gate 8 and stored in the Y register 7, and these are repeated as many times as necessary. The signals for which the multiplication / addition processing has been completed are stored in the data RAM 2c from the selector 9 only in the upper 24 bits (the lower 24 bits are also used only in the case of double precision), and the stored signals are processed by another acoustic effect again. Whether additional processing is performed, or another acoustic effect is added to another musical tone signal separately from the stored signal, and further, it is output from Sout1 and Sout2 of SIO1 and SIO2. Input of the tone signal to the DSP 1 is performed using SIO 1 and 2, and output of the effect addition signal from the DSP is performed using SIO 1 and 2.

The DACs 107a and 107b are general-purpose digital-analog converters, and their output signals are output from speakers through an amplifier.

In the present embodiment, if the acoustic effect added to the input musical tone signal remains unchanged, the instruction ROM 2a.
Since it is limited to a sequence of a plurality of effect programs stored in it, and the change is essentially impossible, as shown in FIG. 2, a presettable program counter 20 other than the above configuration, And an address register 21 for supplying a preset address to the program counter 20.
Since a specific value is set as a start address by a reset process and can be changed from the outside, it is possible to freely combine the effect programs in the mask ROM and to select a desired effect process. Become. By storing the basic effect processing program in the instruction ROM 2a as described above, the information transferred from the external master CPU 10 at the time of sound effect switching is significantly smaller than that in the conventional case. Further, since the change of whether the effect program to be added is processed serially or in parallel is made based on the coefficient data, various changes can be made by changing the transfer data stored in the coefficient RAM 2b. It is possible to select whether to add the sound effect of (1) in a superimposed manner or to add a plurality of sound effects simultaneously in parallel. In that case, as shown below, DSP
The amount of data transfer is further reduced by changing the connection by changing the coefficient data within 1.

In FIG. 3, the outputs OUT1 and 2 of the tone generator circuit 106 are routed through the DSP1 to the DACs 107a and 107b.
7 shows the signal flow of the main routine in the DSP until the signal reaches the. In the figure, f1 and f2 represent two acoustic effect addition routines (processes) processed by the DSP1,
These two sound effect adding routines are either connected in series or in parallel.

To change these connections, change the main flow coefficient data in the DSP (for example, 0H ← → 7FFF).
H). This coefficient data is 16 bi
It is formed by t binary number and is treated as two's complement.
The possible values are as shown in Table 1 below. As shown in the table, the maximum value is 7FFFH, and when multiplication is performed using that value, 3276 is set inside the DSP.
It means that the value of 7/32768 = 0.999969948 ... Is multiplied. Since this value is approximately 1, 7FFFH is used as the through in this embodiment.

[0021]

[Table 1]

As shown in FIG. 3, this DSP obtains two inputs (Sin1, Sin2) and adds two effects (f
2 outputs (Sout1 and Sout2) through 1 and f2)
I do. As shown in this flow, a general-purpose DSP is used so that any of serial or parallel connection patterns can be adjusted only by adjusting coefficient data (shown by Δ in the right-pointing arrow). (Performed by adjusting coefficient data in each of f1 and f2 in DSP1).

In the case of serial connection, the signal input from Sin1 and added with the predetermined effect at f1 is the coefficient C.
By setting 11 to 7FFFH, it is possible to pass through. By setting the coefficients C41 and C51 to 0H and the coefficient C21 to 7FFFH, the current flows to the input side of f2. Here, the signal input from Sin2 by setting the coefficient C22 to 7FFFH is added by the adder, and the acoustic effect is further added at f2. Next, coefficient C31 and coefficient C42 or coefficient C5
If 2 is 7FFFH, Sout1 or Sout2
The signal is output from (however, coefficient C52 or coefficient C42
Is changed to 0H).

On the other hand, when the wires are connected in parallel, the coefficient C22
Is 7FFFH and the coefficient C21 is 0H, the effects of f1 and f2 are applied to the signals separately input from Sin1 and Sin2, and the coefficients C11, C31, C51, C52 (C1
1, C31, C41, C42) is set to 7FFFH and the coefficients C41, C42 (C51, C52) are set to 0H, so that a signal is output from Sout2 (Sout1).

Of course, each sound effect process can be passed through, but in that case, the coefficient C11 is 0H and C12 is 7FFFH in the process on the f1 side, and the coefficient C31 is 0H and C32 is 7FFFH in the process on the f2 side. It becomes possible by In this configuration, the address register 21
Thus, the contents of the coefficient memory 2b can be transferred, the crossfade envelope processing is regarded as one of the effects, and the processing can be performed on a program without providing a special external circuit. Coefficient C1 at this time
If the coefficient data is gradually increased or decreased complementarily between 1 and C12 and between the coefficients C31 and C32, the sound effect processed signal and the unprocessed signal are
It is possible to cross-fade (also, when changing from the through state to the state of outputting a musical tone signal to which a new acoustic effect is added, the above-described cross-fade can be performed).

Further, the coefficients C11, C12, C31, C32
If you want to crossfade with the master CPU1
0 has sent the value directly to the coefficients C11, C12, C31, C32 many times, but as the processing capability of the DSP increases, the coefficient value is cross-faded by the operation of the DSP itself as follows. Is also possible. In that case, the master CPU 10 sends to the DSP, as a coefficient, a value indicating how much the above coefficients should be added (or subtracted) for the crossfade operation. For example, if the master CPU 10 has C'11 = 0001H (+1), C '
When the coefficient data 12 = FFFFH (-1) is transmitted, the DSP causes C11 ← C'11 + C11, C12 ← C '.
The calculation of 12 + C12 is repeatedly calculated until max (7FFFH) or min (000H), and the calculation result is returned to the coefficient RAM 2b. Further coefficient C2
Between C1 and C22, between C41 and C42, C51 and C52
If there is an alternative between the two, it is advisable to execute the crossfade. Note that t1 to t6 in FIG. 3 indicate temporary registers in which the DSP temporarily stores the calculation result.

FIG. 4 is a flow chart showing the main flow of the DSP. Poll 110
The rising edge of the WS (word select) signal sent from the tone generator circuit 106 is detected to detect the start of one cycle of the tone signal.

The Rch input 120 is the Sin in FIG.
The signals from 1 and Sin2 are transferred to registers in1 and in
2 is taken in as in1R + 1, in2R + 1 and R
The ch output 130 is Sout1, Sout in FIG.
The signal data of ot1R-1 and ot2R-1 are output from the temporary registers ot1 and ot2 on the output side to 2.

The F1 through 140 indicates whether the flow of the effect program is passed through normally (effect addition processing is performed) or whether the sound effect program is passed through due to pre-processing by changing the sound effect. To check. When the acoustic effect is changed, pre-processing such as clearing the coefficient RAM 2b and the data RAM 2c is performed.
This is because if the processing of the effect program is performed, the processing may run away or generate a large amount of noise. The information that informs whether or not to allow this through is the master CPU.
10 may change the value of a certain address in the coefficient RAM 2b, or the master CPU 10 may directly change the DS value.
Signals may be sent to the P general purpose input port (not shown).

In normal times, which is not F1 through, callF
Go to 1 (141) and call the effect program from here. This effect program is called by calling the program counter 2 from the set of the main routine and the sound effect adding routine which are stored in the storage area of the instruction ROM 2a.
Selected by 0. The total sound effect programs that can be selected must be stored in a predetermined storage area of the instruction ROM 2a. The flow of the signal data after the processing of the sound effect adding routine f1 is, as shown in FIG. 3, for the right input, the right signal data t1R stored in the temporary register t1 is multiplied by the data of the coefficient C12. The right signal data t2R stored at t2 is multiplied by the data of the coefficient C11, both values are added and stored as the right signal data t3R of the temporary register t3 (t3R ← t1R × C12 + t
2RxC11). The same applies to the left input (t3L
← t1L × C12 + t2L × C11). On the other hand, the signal data t3R and t3L stored in the temporary register t3
Is further multiplied by the data of the coefficient C21 and the signal data in2R, in2L stored in the register in2.
Is multiplied by the data of the coefficient C22, both values are added, and the resulting values are added to the signal data t4R, t4L
Memorize as (t4R ← t3R × C21 + in2R
× C22, t4L ← t3L × C21 + in2L × C2
2).

In the case of F1 through, before the audio effect program is passed through, in order to apply a weight by the same number of steps as F1, the process proceeds to the F1 equivalent delay 142. Here, for example, a loop instruction built in the DSP is used to loop for a required number of steps (coefficient RA
Load the number of steps of F1 written in M2b and delay by that number). In this loop, the redundant function is omitted in the DSP used here, and the input and output of the R signal and the L signal are at the same port, as shown in the time chart of the DSP input / output timing of FIG. ,
This is because it must be performed within a predetermined time (corresponding to the serial data R0 and L0 processing time) from the rise (or fall) of the WS signal. And as mentioned above,
Between music signals that have not undergone sound effect addition processing,
The crossfade process is performed, and further the crossfade process is performed between the musical tone signal and the musical tone signal to which the new acoustic effect is added, and the acoustic effect changing process is ended.

Next, F2 through 150 and callF2 (1
51) and the F2-equivalent delay 152 are the same as those of F1, so detailed parts are omitted. However, the flow of the signal data after the effect program processing is as follows: the signal data t4R, t4L stored in the temporary register t4 is multiplied by the coefficient C32, and the signal data t5R, t5L stored in the temporary register t5 is multiplied by the coefficient C31. hand,
Both values are added and stored in the temporary register t6 as signal data t6R and t6L (t6R ← t4
R × C32 + t5R × C31, t6L ← t4L × C32
+ T5L × C31).

The signal data t3R, t6R, t3L, t6L stored in the temporary registers t3 and t6 are further multiplied by predetermined coefficient data and stored in the temporary registers ot1 and ot2 on the output side. Of these, the portion that finally becomes the Sout1 side output is the signal data t3R, t3L stored in the temporary register t3.
Is multiplied by a coefficient C41, the signal data t6R, t6L stored in the temporary register t6 is multiplied by a coefficient C42, both values are added, and the result is stored in the temporary register ot1 on the output side as the signal data ot1R, ot1L. Yes (ot1R ← t3R × C41 + t6R × C42, ot
1L ← t3L × C41 + t6L × C42). See you Sou
The signal to be output on the t2 side is obtained by multiplying the signal data t3R and t3L stored in the temporary register t3 by a coefficient C51, and the signal data t stored in the temporary register t6.
6R, t6L are multiplied by a coefficient C52, and both values are added,
It is stored in the temporary register ot2 on the output side as signal data ot2R and ot2L (ot2R ← t3
R × C51 + t6R × C52, ot2L ← t3L × C5
1 + t6L × C52).

Next, Lch input 160 is performed, and the signals from Sin1 and Sin2 in FIG.
1 and in2 are taken in as in1L + 1 and in2L + 1, and the Lch output 170 is Sout in FIG.
1, to Sout2, output side temporary register ot1
And ot2 output signal data of ot1L-1 and ot2L-1.

Finally, the value of the data RAM pointer (DRP) is incremented by 1 to return to the start. This is because even if the same data RAM address is specified in the program based on the next sampling, the address of +1 is actually automatically accessed. As a result, the last time (in1R / L +
The input data stored in (1, 1 in2R / L + 1) will be read out this time (in1R / L, in2R / L), and the output data stored this time (ot1R / L, ot2R / L) will be sampled next time. At time, it is read as (ot1R / L-1, ot2R / L-1).

The DSP program shown in FIG. 4 completes the preprocessing during one sampling time (44.1 KHz), enters the polling state, and waits for the next rise of the WS signal. This series of programs performs pipeline processing as shown in Table 2 below using three successive sampling times. That is, in T-1 time, in1R + 1 ← Sin1, in2R + 1 ← Sin2
Processing and in1L + 1 ← Sin1, in2L + 1 ← S
Perform in2 processing. F1 through at the next T time? , C
allF1, delay equivalent to F1, (t3R ← t1R ×
C12 + t2R × C11, t3L ← t1L × C12 + t
2L × C11), (t4R ← t3R × C21 + in2R
× C22, t4L ← t3L × C21 + in2L × C2
2), F2 through? , CallF2, F2 equivalent dela
y, (t6R ← t4R × C32 + t5R × C31, t6
L ← t4L × C32 + t5L × C31), (ot1R ←
t3R × C41 + t6R × C42, ot1L ← t3L ×
C41 + t6L × C42), (ot2R ← t3R × C5
1 + t6R × C52, ot2L ← t3L × C51 + t6
Each process of L × C52) is performed. Furthermore, at T + 1 hour, So
ut1 ← ot1R-1, Sout2 ← ot2R-1, and Sout1 ← ot1L-1, Sout2 ← ot2
The process of L-1 is performed.

[0037]

[Table 2]

The electronic musical instrument of this embodiment is used as follows. First, by turning on the switch of the electronic musical instrument, the master CPU 10 sets the panel initial setting / RAM.
Initial settings of 104 and DSP are performed. Then, necessary information is input from the FD input / output block 103 to the RAM 10
Read to 4. Master CP by the player's panel operation
U10 is from RAM 104 and / or ROM 105
The coefficient data corresponding to the selected acoustic effect is transferred to the coefficient RAM 2b of the DSP 1. At this time, it is already D by the panel operation
This means that the connection pattern within the SP has been determined.

Next, by the player's operation, the key switch ON / OFF information of the key switch block 101 is sent to the master CPU 10 together with the key velocity, and the MID is sent.
From the I / O block 102 or RAM 104 / R
The OM 105 sends performance information to the master CPU 10, and based on the performance information, the master CPU 10 sends the corresponding tone color parameter and key ON / OFF assignment result to the tone generator circuit 106, and the OUT of the tone generator circuit 106.
Tone data is output from 1 and OUT2.

The sound data is sent to the data RAM 2c via the SIOs 1 and 2 of the DSP, and as a result, the sound effect adding process is performed (effect is applied) based on either the serial or parallel connection pattern. At this time, the main routine and the sound effect adding routine fn are set as a set and are mapped in the instruction ROM 2a. When a new effect is selected on the panel, the coefficient RA
Address data is sent from the M2b to the address register 21, is set as start address data in the program counter 20, and each effect program is called and executed by the address designation. When DSP 1 reaches the end of the current program, it issues an instruction to vector jump there as described above. When the decoder receives the vector jump, the coefficient R
The corresponding address of AM2c is output to the C bus, and the start address data is loaded at the next timing. That address is loaded into the program counter 20 as it is, and at the next timing, the instruction ROM 2a is accessed at that address and a new effect program is started. In this way, the effect program is decoded by the decoder and the control in the DSP is performed. Also DSP
The connection method within 1 is determined by the coefficient data as described above, and therefore the connection pattern can be changed between series and parallel only by changing the coefficient data. The musical tone signal to which the desired acoustic effect is added is the DAC 107a and 10
It is output by 7b and is output from the speaker via the amplifier.

The master CPU 10 has a RAM 104.
-The coefficient data corresponding to it from ROM 105
Transfer to P1. Further, at that time, the sound effect program F is passed through. As described above, during this through and when changing from the through state to the state of outputting the musical tone signal to which the new sound effect is added, as described above, Coefficient C
11 and C12 and between the coefficients C31 and C32 complementarily increase / decrease the coefficient data, whereby the signal subjected to the acoustic effect processing and the signal not subjected to the processing are
It is possible to crossfade.

That is, the master CPU 10 is the C of the DSP 1.
Crossfades 11 and C31 from 7FFFH to 0H and C12 and C32 from 0H to 7FFFH. As a result, no effect is added to both the sound effect adding routines f1 and f2, and the routine goes through. The master CPU 10 commands the DSP 1 to jump (through f1 and f2). This command transmission method may be performed by rewriting one of the coefficient RAMs as described above, or by sending a signal to the general-purpose input port of the DSP 1. The DSP will not access the effect program area of the instruction ROM 2a while receiving this signal. The master CPU 10 transfers only coefficient data required for rewriting the coefficient RAM 2b in the DSP 1. Even during this transfer, the DSP 1 outputs the tone signal serially sent from the tone generator circuit 106 for each sampling without adding a sound effect. Then master C
The PU 10 commands the DSP 1 to cancel (stop) the jump (f1 through f2 through). Upon canceling this jump, the DSP returns to the normal processing flow and also accesses the programs of the sound effect adding routines f1 and f2. However, since C11 and C31 are still 0H and C12 and C32 are 7FFFH, the tone signal is exactly the same as the through signal. Further, the master CPU 10 transfers the coefficient data of the new sound effect addition routine to the DSP 1. This period is required until the DSP reaches the orbit for the calculation corresponding to the new coefficient data. Generally considering the time to rewrite external RAM data, 1 msec to 50 ms
ec is needed. The time is proportional to the capacity of the external RAM. When the new sound effect adding routine is normally processed based on the new coefficient data, the master CPU 10 sets C11 and C31 of the DSP 1 to 0H → 7.
Crossfade C12 and C32 to 7FFFH → 0H to FFFH. This makes it possible to add new acoustic effects.

FIG. 6 is a block diagram showing the internal structure of the DSP according to an embodiment of the present invention. In the drawing, only the structure of the part different from the structure of claim 1 of FIG. 2 is shown.

In this configuration, only the subprogram (acoustic effect addition routine fn) for effect processing is masked into a ROM (I-ROM 22a), and the main routine is a subprogram using an externally rewritable RAM (I-RAM 23a). The method has an instruction memory structure. I above
-The contents of the RAM 23a are written during the reset as in the configuration of the general-purpose DSP, the program counter 20 is cleared to zero after the reset, the top address of the I-RAM 23a is accessed, and the process starts from there. I-R
When it comes to the subroutine call in AM23a, this time I
-Any of the ROMs 22a will be accessed. With such a configuration, at the time of sound effect switching, the external master CPU 10 can change the sound program by changing only a part of the main routine of the effect program (that is, the call destination of the sound effect adding routine fn), and the speedup is achieved. In this configuration, unlike a general microprogram, the instructions of the I-RAM 23a and the I-ROM 22a are processed at the same level, so the configuration of the DSP 1 does not become complicated.

FIG. 7 is a block diagram showing the internal structure of the DSP according to the embodiment of the invention described in claim 6. Similar to the above, only the configuration of the part different from the configuration of claim 1 of FIG. 2 is shown in this drawing.

In this configuration, the instruction memory structure is a sub-programmed system similar to that of the second embodiment, and the coefficient data used by each acoustic effect addition routine fn is masked. ROM
Into a coefficient ROM (C-ROM 24b), and the coefficient data of the main routine and each acoustic effect addition routine fn
Collects only the coefficient data that needs to be changed from the outside to form a coefficient RAM (C-RAM 25b). With such a structure, when the sound effect is changed, the external master CPU 10 makes the DSP
The amount of processing programs and coefficient data that must be transferred to 1 is significantly reduced.

[0047]

According to the device having the configuration of the present invention described in detail above, a part or all of the instruction memory in the DSP, a part of the coefficient memory, etc.
Since the structure of the storage area of the data that is used fixedly is made into a mask ROM and the transfer amount of that portion is reduced, it is possible to speed up the switching of the program when a plurality of acoustic effects are added. Further, by treating the crossfade envelope processing as one of the effects, the number of discrete components such as the crossfade circuit can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of an electronic musical instrument including a sound effect adding device in which a DSP according to an embodiment of the present invention is used.

FIG. 2 is a block diagram showing an internal configuration of a DSP.

FIG. 3 is an explanatory diagram showing a signal flow of a main routine in the DSP.

FIG. 4 is a flowchart showing a main flow of the DSP.

FIG. 5 is a time chart showing DSP input / output timing.

FIG. 6 is a block diagram showing an internal configuration of a DSP according to an embodiment of claim 3;

FIG. 7 is a block diagram showing an internal configuration of a DSP according to an embodiment of claim 6;

[Explanation of symbols]

 1 DSP 2a Instruction ROM 22a I-ROM 23a I-RAM 2b Coefficient RAM 24b C-ROM 25b C-RAM 2c Data RAM 3a C register 3b D register 4 Multiplier 5 P register 6 Adder 7 Y register 8 Gate 9 Selector 10 master CPU 20 program counter 21 address register 106 tone generator circuits 107a, 107b DAC

Claims (7)

[Claims] 1. A non-volatile program memory internally storing a plurality of different completed processing programs,
It has a volatile coefficient memory capable of storing coefficient data used by the processing program, a presettable program counter, and an address register for supplying a preset address to the program counter, and the address register is specified by a reset process. A digital signal processor characterized by being set to a value and being changeable externally. 2. The digital signal processor according to claim 1, wherein the address register is capable of transferring the contents of a coefficient memory. 3. A non-volatile first program memory in which a plurality of different completed processing programs are individually stored inside, a second program memory rewritable from outside, and these first and second program memories. A digital signal processor having a program counter for address control in common, wherein the program counter first activates the second program memory in a reset process. 4. The digital signal processor according to claim 3, wherein the second program memory has a capacity smaller than the number of steps that can be processed at the sampling frequency of the input signal. Signal processor. 5. A non-volatile program memory internally storing a plurality of different completed processing programs,
A non-volatile first coefficient memory that individually stores coefficient data that is fixedly used by the processing program; and a volatile second coefficient memory that jointly stores rewritable coefficient data that is used by the processing program. And has the second
A digital signal processor characterized in that the coefficient memory is externally written during or before the reset process. 6. A non-volatile first program memory in which a plurality of different completed processing programs are individually stored inside, a second program memory rewritable from the outside, and a coefficient fixedly used by the processing program. A non-volatile first coefficient memory storing data individually, a volatile second coefficient memory storing jointly rewritable coefficient data used by the processing program, and the first and second program memories. A program counter for address control in common, which program counter first activates a second program memory in a reset process, and the second coefficient memory is externally written during or before the reset process. Digital signal processor characterized by. 7. The digital signal processor according to claim 5, wherein coefficient data for adding an envelope to a value processed at an output stage of each processing program is stored in the coefficient memory, and the processing program is stored. 7. The digital signal processor according to claim 5, wherein the envelope is lowered once when is switched.