JPH09289368A - Two-layer type printed circuit board and manufacturing method thereof - Google Patents

Two-layer type printed circuit board and manufacturing method thereof

Info

Publication number
JPH09289368A
JPH09289368A JP12409396A JP12409396A JPH09289368A JP H09289368 A JPH09289368 A JP H09289368A JP 12409396 A JP12409396 A JP 12409396A JP 12409396 A JP12409396 A JP 12409396A JP H09289368 A JPH09289368 A JP H09289368A
Authority
JP
Japan
Prior art keywords
layer
conductive metal
insulating film
circuit board
printed circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12409396A
Other languages
Japanese (ja)
Inventor
Tadahiro Nishikawa
忠寛 西川
Shunroku Toyama
俊六 遠山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyo Metallizing Co Ltd
Original Assignee
Toyo Metallizing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyo Metallizing Co Ltd filed Critical Toyo Metallizing Co Ltd
Priority to JP12409396A priority Critical patent/JPH09289368A/en
Publication of JPH09289368A publication Critical patent/JPH09289368A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0393Flexible materials
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/115Via connections; Lands around holes or via connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections

Landscapes

  • Manufacturing Of Printed Wiring (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

PROBLEM TO BE SOLVED: To obtain a very fine circuit pattern at a high yield by specifying the number and max. length of through-holes piercing a two-layer type printed circuit board and conductive metal layer to reach the surface of an insulation film. SOLUTION: A conductive metal layer 2 is formed on an insulation film 1 and chemically adsorbed pref. through a water soln. to pin-holes through which the film 1 is exposed, i.e., defects of this metal layer 2 and, if required, to bored throughholes to expose the film 1, and then the electroplating is made to obtain a two-layer type printed board. It is specified that the number and max. length of pin-holes of this board are 10 holes/m<2> or less and 10 microns or less as measured with the transmitted light and steromicroscope. Thus it is possible to produce a fine pattern with through-holes of 80 microns or less pitch at a high yield which was difficult to mass-produce, whereby more highdensity and more high-integration degree electric and electronic apparatus are expectable.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は接着剤層のない2層
型プリント回路用基板で、80ミクロンピッチ以下の超
微細回路パタ−ンを高収率で提供できるプリント回路用
基板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a two-layer type printed circuit board having no adhesive layer and capable of providing an ultrafine circuit pattern having a pitch of 80 μm or less in a high yield.

【0002】[0002]

【従来の技術】従来、フレキシブルプリント回路用基板
としてポリイミドフィルムあるいはPETフィルムに接
着剤を介して銅箔を張合わせた通称“3層型”が使用さ
れている。3層型プリント回路用基板は、接着剤にエポ
キシ系樹脂あるいはアクリル系樹脂が用いられているた
め、それに含まれる不純物イオンにより、電気特性が劣
化するという欠点を有し、また接着剤の耐熱温度が精々
100〜150℃であるため、ポリイミドの高耐熱性
(400℃以上)特性が十分に生かされないという欠点
を有するので、高温実装を必要とするICチップへのワ
イヤ−ボンディングなどでスペックダウンを余儀なくさ
れている。また3層型プリント回路用基板では、銅箔の
一般的な膜厚が18ミクロンあるいは35ミクロンであ
るため、80ミクロンピッチ(銅配線40ミクロン、ギ
ャップ40ミクロン)以下のパタ−ニングを行うには銅
が厚すぎてエッチング率が著しく低下し、銅箔表面側の
回路幅と接着剤面側の回路幅が著しく異なり、あるいは
エッチングで全体が著しく細り目的の回路パタ−ンが得
られないという欠点もある。
2. Description of the Related Art Conventionally, a so-called "three-layer type" in which a copper foil is laminated on a polyimide film or a PET film via an adhesive has been used as a substrate for a flexible printed circuit. Since the three-layer type printed circuit board uses an epoxy resin or an acrylic resin as an adhesive, it has a drawback that the electrical characteristics are deteriorated by impurity ions contained in the adhesive, and the heat resistance temperature of the adhesive is high. Since the temperature is 100 to 150 ° C at the best, it has a drawback that the high heat resistance (400 ° C or higher) of polyimide cannot be fully utilized, so it is possible to reduce the specifications by wire bonding to IC chips that require high temperature mounting. Is forced. Also, in the case of a three-layer type printed circuit board, the typical film thickness of the copper foil is 18 μm or 35 μm. Therefore, in order to perform patterning at a pitch of 80 μm (copper wiring 40 μm, gap 40 μm) or less. The copper is too thick, the etching rate is significantly reduced, the circuit width on the copper foil surface side is significantly different from the circuit width on the adhesive surface side, or the whole is remarkably thinned by etching and the target circuit pattern cannot be obtained. There is also.

【0003】近年これらの欠点を解決するため、絶縁性
フィルム上に接着剤を介さないで各種の蒸着法、例えば
真空蒸着法、スパッタリング法あるいは各種イオンプレ
−ティング法により各種金属を蒸着した後に電解銅メッ
キを行うことにより得られる、通称“2層型”が提案さ
れている。これは、電解銅メッキで銅膜厚を自由に変化
でき、例えば8ミクロンの銅膜厚であれば60ミクロン
ピッチの回路パタ−ンが簡単に作成でき且つ、各種絶縁
性フィルムの耐熱温度がそのまま反映できる特徴を持っ
ている。
In recent years, in order to solve these drawbacks, electrolytic copper is deposited on an insulating film by various vapor deposition methods such as vacuum vapor deposition method, sputtering method or various ion plating methods without using an adhesive agent. A so-called "two-layer type", which is obtained by plating, has been proposed. This is because the copper film thickness can be freely changed by electrolytic copper plating. For example, if the copper film thickness is 8 μm, a 60 μm pitch circuit pattern can be easily created, and the heat resistant temperature of various insulating films can be kept unchanged. It has characteristics that can be reflected.

【0004】これらの2層型に関しては、特公平2−5
5943号公報に、ポリイミドフィルム上にクロムを蒸
着し、その上に銅を蒸着し、さらに電解銅メッキをする
ことにより錫または金メッキからのアンダ−カットが改
善できることが記載されている。
Regarding these two-layer types, Japanese Patent Publication No. 2-5
Japanese Patent Publication No. 5943 describes that undercutting from tin or gold plating can be improved by depositing chromium on a polyimide film, depositing copper on it, and then performing electrolytic copper plating.

【0005】また、特開昭63−185091号公報
に、銅スパッタリング後に高周波バイアススパッタ−
し、さらに電気銅メッキを行う高周波バイアススパッタ
リング法により密着力に優れた2層型回路基板が得られ
ることが記載されている。
Further, Japanese Patent Laid-Open No. 63-185091 discloses a high frequency bias sputtering after copper sputtering.
It is described that a two-layer type circuit board having excellent adhesion can be obtained by a high frequency bias sputtering method in which electrolytic copper plating is further performed.

【0006】その他、オ−ル湿式法で2層型回路基板を
作成する方法として、特開平7−216553号公報に
は、ポリイミド表面を苛性アルカリでエッチングし、そ
れに触媒を付与し、その後にニッケルなどの金属を無電
解析出させ、それを不活性ガス雰囲気中で熱処理した
後、電気銅メッキを行うことにより1.0Kgf/cm以上
の密着強度が得られることが記載されている。
In addition, as a method for producing a two-layer type circuit board by an all wet method, in JP-A-7-216553, a polyimide surface is etched with caustic, a catalyst is applied thereto, and then nickel is added. It is described that the adhesion strength of 1.0 Kgf / cm or more can be obtained by electrolessly depositing a metal such as the above, heat treating it in an inert gas atmosphere, and then performing electrolytic copper plating.

【0007】これら2層型は絶縁性フィルム/銅間の密
着性及び耐薬品性が3層品より弱いとされていることか
ら、それの改善を目的としたものである。しかしなが
ら、2層型の最大の欠点は銅層から絶縁性フィルム表面
に貫通する貫通穴(通称“ピンホ−ル”、以下単にピン
ホ−ルということがある。)である。ピンホ−ルがるた
めに回路パタ−ンのカケ、断線あるいは浮きが発生し8
0ミクロンピッチ以下のファインパタ−ンを収率良く作
製することが困難である。すなはち、上記蒸着法あるい
は湿式法で作成した2層型プリント回路用基板で、60
ミクロンピッチ(銅配線30ミクロン、ギャップ30ミ
クロン)プリント回路基板を作製した場合、配線幅の1
/3以上のカケが全回路パタ−ン中に少なくとも1箇所
以上あればその基板全体が不合格となる。そのため、前
記配線幅30ミクロンに対して10ミクロン以上のカケ
は不合格の対象となり、上記ピンホ−ルが10ミクロン
以上の大きさである場合にはパタ−ンのカケ、あるいは
断線が発生する可能性が大きい。
Since these two-layer type are considered to have weaker adhesiveness between the insulating film / copper and chemical resistance than the three-layer type, they are intended to improve it. However, the biggest drawback of the two-layer type is a through hole (commonly called "pinhole", hereinafter sometimes simply referred to as pinhole) penetrating from the copper layer to the surface of the insulating film. Because of pinholes, circuit pattern chipping, wire breakage, or floating may occur.
It is difficult to produce a fine pattern with a pitch of 0 micron or less with high yield. That is, the two-layer type printed circuit board prepared by the vapor deposition method or the wet method is used.
When a printed circuit board with a micron pitch (copper wiring 30 microns, gap 30 microns) is manufactured, the wiring width is 1
If at least one or more chips of / 3 or more are present in the entire circuit pattern, the entire board fails. Therefore, chips having a width of 10 microns or more with respect to the wiring width of 30 microns are rejected. If the pinhole has a size of 10 microns or more, chipping of the pattern or disconnection may occur. The nature is great.

【0008】各種蒸着法の場合、ピンホ−ルの発生原因
は絶縁性フィルム表面に付着しているゴミ、あるいは蒸
着時の金属の突沸などによる蒸着異常により部分的な未
蒸着部が発生し、それが蒸着膜表面から絶縁性フィルム
表面に貫通するピンホ−ルとなる。一般的に蒸着膜が数
百〜数万オングストロ−ムの場合、ピンホ−ル数はサブ
ミクロンのものから数百ミクロンのものが数百〜数万個
/m2発生する。そのため、蒸着膜のピンホ−ル発生を
被処理フィルムの全幅及び全長についてゼロにすること
は極めて難しいのが実情である。
In the case of various vapor deposition methods, the cause of the pinhole is dust that adheres to the surface of the insulating film, or vapor deposition abnormality due to bumping of metal during vapor deposition causes a partial non-vapor deposited portion. Serves as a pinhole penetrating from the surface of the deposited film to the surface of the insulating film. Generally, when the deposited film has a thickness of hundreds to tens of thousands of angstroms, a pinhole having a number of submicrons to hundreds of microns is generated in the hundreds to tens of thousands / m 2 . Therefore, it is extremely difficult to reduce the pinhole generation of the vapor deposition film to zero for the entire width and the entire length of the film to be processed.

【0009】ピンホ−ルのある蒸着膜に18〜35ミク
ロンの銅メッキを行っても数十ミクロン以上のピンホ−
ルは埋まらず、また仮に30ミクロン以下程度のピンホ
−ルが埋り、連続膜としての外観を呈したとしても、そ
れによりピンホ−ル箇所の銅メッキ層と絶縁性フィルム
間の密着力が得られるわけではなく、その箇所でエッチ
ングによる回路パタ−ン形成時に絶縁性フィルムからの
浮き、あるいは熱処理時のフクレなどが発生しプリント
回路基板の信頼性を著しく低下させている。
Even if a plated film having a pinhole is plated with copper having a thickness of 18 to 35 microns, a pinhole having a thickness of several tens of microns or more can be obtained.
However, even if the pinhole of about 30 microns or less is buried and the appearance as a continuous film is exhibited, the adhesive force between the copper plating layer and the insulating film at the pinhole is obtained. However, when the circuit pattern is formed by etching, floating from the insulating film or blistering at the time of heat treatment occurs at that portion, which significantly deteriorates the reliability of the printed circuit board.

【0010】また、オ−ル湿式法で2層型回路基板を作
製する場合においても、その発生メカニズムは異なるが
ピンホ−ルは発生する。即ち、絶縁性フィルムに触媒を
吸着させた後、金属を析出するための無電解メッキの工
程において、その析出反応が基本的に、被処理物の表面
で水素ガスの発生を伴う。その水素ガス発生箇所で金属
の未析出箇所が生じ、前記ピンホ−ルが発生する。その
他、苛性ソ−ダでポリイミド表面をエッチングし活性化
するとき、それが不備な箇所には次行程の触媒が吸着せ
ず、その箇所には銅が析出しないためにピンホ−ルが発
生する。本発明者らの確認試験では、18ミクロンの銅
メッキ後でサブミクロンのものから数百ミクロンのもの
が数百〜数千個/m2確認された。
Also, when the two-layer type circuit board is manufactured by the all wet method, pinholes are generated although the mechanism of occurrence is different. That is, in the step of electroless plating for depositing a metal after the catalyst is adsorbed on the insulating film, the deposition reaction basically involves generation of hydrogen gas on the surface of the object to be treated. An unprecipitated portion of metal is generated at the hydrogen gas generation portion, and the pinhole is generated. In addition, when the polyimide surface is activated by etching with a caustic soda, the catalyst in the next step is not adsorbed to the defective portion, and copper is not deposited at that portion, so that pinholes are generated. The confirmation test of the present inventors, those from those submicron several hundred microns was confirmed several hundreds to several thousands pieces / m 2 after copper plating 18 micron.

【0011】また、スルホ−ル付き3層型フレキシブル
プリント回路基板の製造方法は18ミクロンあるいは3
5ミクロンの銅箔を接着剤を介して絶縁性フィルムに張
合わせた後、プレスあるいはドリルなどで貫通穴加工を
行い、その箇所に触媒を吸着させた後に無電解メッキで
導通性を確保し、次いで電気銅メッキを行っている。そ
の場合の貫通穴内部の銅膜厚は導通信頼性が確保できる
15ミクロン程度が一般的である。そのため、18ミク
ロンの銅箔に銅メッキの15ミクロンが加算されるとト
−タル膜厚は33ミクロンになり、上記エッチング率が
著しく悪く、スルホ−ル付き基板では80ミクロンピッ
チの回路パタ−ンは作製することが難しい。
The method for manufacturing a three-layer flexible printed circuit board with a sulfol is 18 μm or 3
After sticking a 5 micron copper foil to the insulating film via an adhesive, through holes are processed with a press or a drill, etc., and the catalyst is adsorbed to the places, and electroconductivity plating is used to secure conductivity. Next, electrolytic copper plating is performed. In that case, the copper film thickness inside the through hole is generally about 15 μm, which can ensure the conduction reliability. Therefore, when 15 μm of copper plating is added to 18 μm copper foil, the total film thickness becomes 33 μm, and the above etching rate is extremely poor. Is difficult to make.

【0012】[0012]

【発明が解決しようとする課題】近年、電気・電子機器
のIC化及び高密度・高集積化が急速に進み、それに伴
いフレキシブルプリント回路基板のパタ−ン幅も150
〜200ミクロンピッチから80〜150ミクロンピッ
チへと進み、さらに現在では30〜80ミクロンピッチ
対応が要求されている。従って、本発明の目的は、80
ミクロンピッチ以下の超微細回路パターンを高収率で得
られる2層型プリント回路用基板および2層型プリント
回路基板を提供せんとするものである。また、本発明の
他の目的は、かかる2層型プリント回路用基板および2
層型プリント回路基板を取得する方法を提供せんとする
ものである。
In recent years, IC and high density / high integration of electric / electronic devices have been rapidly advanced, and the pattern width of the flexible printed circuit board has been increased to 150 with it.
Progressing from ˜200 micron pitch to 80 to 150 micron pitch, and nowadays, it is required to be compatible with 30 to 80 micron pitch. Therefore, the object of the present invention is 80
It is intended to provide a two-layer type printed circuit board and a two-layer type printed circuit board capable of obtaining an ultrafine circuit pattern of a micron pitch or less in a high yield. Another object of the present invention is to provide such a two-layer type printed circuit board and
A method of obtaining a layered printed circuit board is provided.

【0013】[0013]

【課題を解決するための手段】本発明者らの検討によれ
ば、本発明の目的は下記の本発明によって工業的に好都
合に達成された。
According to the studies made by the present inventors, the objects of the present invention have been industrially conveniently achieved by the following present invention.

【0014】[1]絶縁性フィルム上に導電性金属層と
銅メッキ層が順次形成されてなる2層型プリント回路用
基板において、該銅メッキ層及び該導電性金属層を貫通
して絶縁性フィルム表面に達する貫通穴の存在数が10
個/m2以下であり、かつ該貫通穴の最大長さが10ミ
クロン以下であることを特徴とする2層型プリント回路
用基板。
[1] In a two-layer type printed circuit board in which a conductive metal layer and a copper plating layer are sequentially formed on an insulating film, an insulating property is obtained by penetrating the copper plating layer and the conductive metal layer. The number of through holes reaching the film surface is 10
A two-layer type printed circuit board, wherein the number of holes / m 2 or less and the maximum length of the through holes is 10 μm or less.

【0015】[2]絶縁性フィルムがポリエチレンテレ
フタレ−ト、ポリフェニレンサルファイド、ポリエ−テ
ルケトン、芳香族ポリアミド、ポリアリレ−ト、ポリイ
ミド、ポリアミドイミド、およびポリエ−テルイミドの
群から選ばれたポリマーからなるフィルムであることを
特徴とする上記[1]の2層型プリント回路用基板。
[2] The insulating film is a film made of a polymer selected from the group consisting of polyethylene terephthalate, polyphenylene sulfide, polyetherketone, aromatic polyamide, polyarylate, polyimide, polyamideimide, and polyetherimide. The two-layer type printed circuit board according to [1] above.

【0016】[3]接着剤層のない絶縁性フィルムの片
面又は両面に蒸着により導電性金属層をもうけ、次に導
電性金属が蒸着されず絶縁性フィルムが露出した箇所に
水溶液による化学的方法により導電性金属層を吸着さ
せ、さらに電気銅メッキ層を形成することを特徴とする
上記[1]及び上記[2]の2層型プリント回路用基板
の製造方法。
[3] A conductive metal layer is provided on one or both sides of an insulating film having no adhesive layer by vapor deposition, and then a chemical method using an aqueous solution is applied to a portion where the conductive metal is not deposited and the insulating film is exposed. The method for producing a two-layer type printed circuit board according to the above [1] and [2], characterized in that the conductive metal layer is adsorbed by the above method and an electrolytic copper plating layer is further formed.

【0017】[4]導電性金属層、銅メッキ層及び絶縁
性フィルムを貫通する貫通穴を有することを特徴とする
上記[1]及び上記[2]の2層型プリント回路用基
板。
[4] The two-layer type printed circuit board according to the above [1] and [2], which has a through hole penetrating the conductive metal layer, the copper plating layer and the insulating film.

【0018】[5]接着剤層のない絶縁性フィルムの片
面又は両面に蒸着により導電性金属層をもうけた後、あ
るいは導電性金属層と銅メッキ層を順次もうけた後に、
該導電性金属層、銅メッキ層及び絶縁性フィルムを貫通
する穴加工を行い、穴加工により絶縁性フィルムが露出
した箇所及び絶縁性フィルムに導電性金属が蒸着されな
かった箇所に化学的方法により導電性金属層を吸着さ
せ、さらに電気銅メッキ層を形成することを特徴とする
上記[4]の2層型プリント回路用基板の製造方法。
[5] After providing a conductive metal layer by vapor deposition on one or both sides of an insulating film having no adhesive layer, or after sequentially providing a conductive metal layer and a copper plating layer,
A hole is drilled through the conductive metal layer, the copper plating layer and the insulating film, and a chemical method is applied to a portion where the insulating film is exposed by the hole drilling and a portion where the conductive metal is not deposited on the insulating film. The method for producing a two-layer type printed circuit board according to the above [4], which comprises adsorbing a conductive metal layer and further forming an electrolytic copper plating layer.

【0019】[6]前記絶縁性フィルムに貫通穴加工を
行った後、その両面及び貫通穴に蒸着により導電性金属
層をもうけ、ついで導電性金属が蒸着されず絶縁性フィ
ルムが露出した箇所に水溶液による化学的方法により導
電性金属層を吸着させ、さらに電気銅メッキ層を形成す
ることを特徴とする上記[4]の2層型プリント回路用
基板の製造方法。
[6] After the through hole is formed in the insulating film, a conductive metal layer is provided on both sides and the through hole by vapor deposition, and then the conductive metal is not deposited on the exposed portion of the insulating film. The method for producing a two-layer type printed circuit board according to the above [4], wherein a conductive metal layer is adsorbed by a chemical method using an aqueous solution, and an electrolytic copper plating layer is further formed.

【0020】[7]絶縁性フィルムと導電性金属層の間
に金属及びセラミックスからなる蒸着層をもうけたこと
を特徴とする上記[1]、上記[2]および上記[4]
の2層型プリント回路用基板。
[7] The above-mentioned [1], [2] and [4] characterized in that a vapor deposition layer made of metal and ceramics is provided between the insulating film and the conductive metal layer.
2-layer printed circuit board.

【0021】[8]上記[1]、上記[2]および上記
[4]の2層型プリント回路用基板に回路パターン形成
し、さらにニッケル、パラジウム、金、銀、スズ、ハン
ダ、ロジウム、白金及びそれらの化合物の群から選ばれ
たメッキを形成せしめたことを特徴とする2層型プリン
ト回路基板。
[8] A circuit pattern is formed on the two-layer type printed circuit board of the above [1], [2] and [4], and further nickel, palladium, gold, silver, tin, solder, rhodium, platinum. And a two-layer type printed circuit board characterized in that a plating selected from the group of these compounds is formed.

【0022】[0022]

【発明の実施の形態】本発明の最大の特徴は、絶縁性フ
ィルムに導電性金属層をもうけ、該導電性金属層の欠陥
により絶縁性フィルムが露出したピンホ−ル箇所、及
び、必要ならば、貫通穴加工により絶縁性フィルムが露
出した箇所に、好ましくは水溶液により、化学的方法で
導電性金属層を吸着させ、次いで電気銅メッキを行うこ
とである。
BEST MODE FOR CARRYING OUT THE INVENTION The most important feature of the present invention is to provide a conductive metal layer on an insulating film, a pinhole portion where the insulating film is exposed due to a defect of the conductive metal layer, and if necessary. That is, a conductive metal layer is adsorbed by a chemical method to a place where the insulating film is exposed by the through hole processing, preferably with an aqueous solution, and then electrolytic copper plating is performed.

【0023】即ち、絶縁性フィルムに公知の前処理であ
るコロナ処理やプラズマ処理を施しフィルム表面の親水
性の向上、さらに超音波クリ−ナ−などでゴミ除去を行
った後、蒸着法でニッケル、鉄、コバルト、銅、スズ、
パラジウム、クロム、及びそれらの化合物からなる導電
性金属層を通常500〜10000オングストロ−ム形
成する。蒸着法には真空蒸着、スパッタリングあるいは
イオンプレイティング法などがあり、中でも高エネルギ
−で製膜でき、膜質も緻密でピンホ−ルが比較的に少な
いスパッタリング法及びイオンプレイティング法が好ま
しい。導電性金属層の膜厚は次行程で化学的処理を受け
るためそれに耐える膜厚が必要である。即ち、膜厚が2
000オングストロ−ム以下であれば密着強度の低下が
見られ、7000オングストロ−ム以上であれば製造コ
ストが高くなるので2000〜7000オングストロ−
ムの範囲が好ましい。
That is, the insulating film is subjected to corona treatment or plasma treatment, which is a known pretreatment, to improve the hydrophilicity of the film surface, and dust is removed with an ultrasonic cleaner, and then nickel is deposited by a vapor deposition method. , Iron, cobalt, copper, tin,
A conductive metal layer made of palladium, chromium, and a compound thereof is usually formed in a thickness of 500 to 10000 angstrom. Vapor deposition methods include vacuum vapor deposition, sputtering, and ion plating methods. Among them, the sputtering method and ion plating method, which can form a film with high energy, have dense film quality, and relatively few pinholes, are preferable. The film thickness of the conductive metal layer is required to be resistant to it because it is chemically treated in the next step. That is, the film thickness is 2
If it is 000 angstroms or less, the adhesion strength is lowered, and if it is 7,000 angstroms or more, the manufacturing cost is high.
A range of m is preferred.

【0024】また、ピンホ−ルは導電性金属層の膜厚が
3000オングストロ−ム程度までは減少し、それ以上
では飽和状態になる傾向にあり、導電性金属層の膜厚は
3000〜5000オングストロ−ムの範囲が最適であ
る。
In the pinhole, the thickness of the conductive metal layer decreases to about 3000 angstroms, and the thickness tends to reach a saturation state when the thickness is more than 3000 angstroms. The conductive metal layer has a thickness of 3000 to 5000 angstroms. -The optimum range is

【0025】次に、導電性金属が蒸着されず絶縁性フィ
ルムが露出した箇所に、好ましくは水溶液により、化学
的方法によって導電性金属層を吸着させる。その方法
は、例えば、次のとおりである。すなわち、導電性金属
層を界面活性剤を含んだ前処理脱脂液で処理し、その後
に苛性ソ−ダ水溶液などの薬液中でピンホ−ル箇所の露
出フィルム表面の活性化を行い72ダイン以上のヌレが
確保できる状態にする。その後、パラジュ−ムあるいは
パラジュ−ムとスズの化合物などの導電性金属層を吸着
させる。導電性金属層の膜厚は電気銅メッキを考慮して
乾燥後の表面抵抗で0.01〜0.1Ω/□相当が好ま
しい。
Next, a conductive metal layer is adsorbed by a chemical method, preferably by an aqueous solution, on the place where the conductive film is not vapor-deposited and the insulating film is exposed. The method is, for example, as follows. That is, the conductive metal layer is treated with a pretreatment degreasing liquid containing a surfactant, and then the exposed film surface at the pinhole location is activated in a chemical solution such as an aqueous solution of caustic soda so as to have a thickness of 72 dyne or more. Make sure that you can get wet. Then, a conductive metal layer such as a palladium or a compound of palladium and tin is adsorbed. The thickness of the conductive metal layer is preferably 0.01 to 0.1 Ω / □ in terms of surface resistance after drying in consideration of electrolytic copper plating.

【0026】銅メッキ層の形成は、通常電解メッキ法で
行う。本発明において、電解メッキ法は銅メッキ析出時
に被処理物の表面からピンホ−ルの原因となる水素ガス
の発生を伴わない、すなはち電流効率100%の硫酸銅
メッキが好ましい。硫酸銅メッキ液は1次処理として銅
濃度が高く硫酸濃度が50g/l程度の低濃度硫酸タイ
プで0.1〜0.7ミクロンの銅メッキを行った後に、
2次処理として均一な膜厚と緻密な銅層が得られる硫酸
濃度が180g/l程度の高硫酸タイプで所定の膜厚ま
で銅メッキを行うことが好ましい。
The copper plating layer is usually formed by electrolytic plating. In the present invention, the electrolytic plating method is preferably copper sulfate plating having a current efficiency of 100%, which does not generate hydrogen gas which causes pinholes from the surface of the object to be treated during copper plating deposition. The copper sulfate plating solution is a low-concentration sulfuric acid type having a high copper concentration and a sulfuric acid concentration of about 50 g / l as the first treatment, and after performing copper plating of 0.1 to 0.7 micron,
As the secondary treatment, it is preferable to perform copper plating to a predetermined film thickness with a high sulfuric acid type having a sulfuric acid concentration of about 180 g / l that can obtain a dense copper layer with a uniform film thickness.

【0027】上記工程で得られた2層型プリント回路用
基板について透過光と実態顕微鏡を用いピンホ−ルを測
定した結果、ピンホ−ルの長径が2〜3ミクロンのもの
が0〜1個/m2であった。
The pinholes of the two-layer type printed circuit board obtained in the above step were measured with transmitted light and an actual microscope. As a result, 0 to 1 / pinhole having a major axis of 2 to 3 microns was obtained. It was m 2 .

【0028】ピンホ−ルの穴径と数が配線のカケや断線
に与える影響について30ミクロンの配線パタ−ン(6
0ミクロンピッチ)を作製し、その5,000本につい
てカケ及び断線を観察した結果を表1に示す。カケにつ
いては10ミクロン以上のものを不合格とした。
Regarding the influence of the diameter and number of the pinholes on chipping and disconnection of the wiring, the wiring pattern (6
Table 1 shows the results of observing cracks and wire breakages of 5,000 of them prepared. Regarding chips, those of 10 microns or more were rejected.

【0029】[0029]

【表1】 表1より、60ミクロンピッチ配線について良品率10
0%を達成するためにはピンホ−ル最大径30ミクロン
以下で、50個/m2以下を満たす必要がある。また、
配線幅が20あるいは10ミクロンになった場合を考慮
すると、ピンホ−ルの最大径は10ミクロン以下で且
つ、10個/m2以下が必須となる。
[Table 1] From Table 1, the yield rate of 60 micron pitch wiring is 10
In order to achieve 0%, it is necessary to satisfy the maximum pinhole diameter of 30 microns or less and 50 pieces / m 2 or less. Also,
Considering the case where the wiring width is 20 or 10 μm, the maximum diameter of the pinhole is required to be 10 μm or less and 10 pieces / m 2 or less.

【0030】また、蒸着により導電性金属層をもうけた
後に導電性金属層及び絶縁性フィルム層を貫通するスル
ホ−ル穴加工を行い、上記化学的方法により導電性金属
層を吸着させ、さらに電気銅メッキを行うことにより貫
通穴部と導電性金属層の銅膜厚がほぼ同じであるスルホ
−ル付きで、しかもピンホ−ルの少ない、あるいは無い
基板が得られる。穴加工は穴の径により、例えばφ0.
5mm程度であればドリルあるいはプレスによる機械加
工が好ましく、数十ミクロン以上であればエキシマレ−
ザ−などが好ましい。その他、スルホ−ル加工場所の導
電性金属層をエッチング液で溶解し、その後に絶縁性フ
ィルムを公知のエッチング液で化学的に穴加工すること
ができる。これらの加工方法は目的に応じて選択するこ
とが好ましい。また、前記穴加工は導電性金属層上に電
気銅メッキを行なった後に行なうことができる。その場
合、電気銅メッキの膜厚はエッチング率の低下を極力お
さえ且つ、耐熱フクレをさけるために数ミクロン程度が
好ましい。
In addition, after forming a conductive metal layer by vapor deposition, a sulcer hole drilling through the conductive metal layer and the insulating film layer is performed, and the conductive metal layer is adsorbed by the above-mentioned chemical method, and further, electric By plating with copper, it is possible to obtain a substrate having a through hole and a conductive metal layer having a copper film thickness of approximately the same and having little or no pinhole. Depending on the diameter of the hole, for example, φ0.
If it is about 5 mm, machining by a drill or press is preferable, and if it is several tens of microns or more, excimer
The etc. are preferred. In addition, the conductive metal layer at the location where the sulfol is processed can be dissolved with an etching solution, and then the insulating film can be chemically drilled with a known etching solution. These processing methods are preferably selected according to the purpose. Further, the drilling can be performed after electrolytic copper plating is performed on the conductive metal layer. In that case, the film thickness of the electrolytic copper plating is preferably about several microns in order to suppress the decrease in the etching rate as much as possible and to prevent heat-resistant blisters.

【0031】上記方法で作製した10ミクロンの銅膜厚
品と、従来の2層品で、18ミクロンの銅膜厚品にスル
ホ−ル加工を行い、その後10ミクロンの銅メッキを行
いト−タル膜厚28ミクロンのものを回路幅30ミクロ
ンのパタ−ニングを行い、そのエッチング率を測定し
た。エッチング率は図1のA、Bおよびhの値から下記
式により求めた。
A 10-micron copper-thickness product produced by the above method and a conventional two-layered copper-thickness product having a 18-micron thickness were subjected to a sulfol processing, and then 10-micron copper plating was performed, and a total was obtained. A film having a film thickness of 28 μm was patterned with a circuit width of 30 μm, and the etching rate was measured. The etching rate was calculated from the values of A, B and h in FIG. 1 by the following formula.

【0032】エッチング率=2h/B−A その結果、10ミクロンの銅膜厚品(本発明品)のエッ
チング率は、6.6であり、一方、28ミクロンの従来
の2層品のエッチング率は、3.6であった。
Etching rate = 2 h / BA As a result, the etching rate of the 10-micron copper film thickness product (the product of the present invention) is 6.6, while the etching rate of the conventional 2-layer product of 28 microns. Was 3.6.

【0033】従来の3層品のエッチング率は2.5〜
3.0程度であることから、6.6は飛躍的な改善であ
ること判る。
The etching rate of the conventional three-layer product is 2.5 to
Since it is about 3.0, it can be seen that 6.6 is a dramatic improvement.

【0034】また、前記スルホ−ル加工は蒸着による導
電性金属層を設ける前に行い、前記同様の工程で処理す
ることにより高エッチング率でピンホ−ルの少ない、あ
るいは無いスルホ−ル付き2層型プリント回路用基板を
達成することができる。
Further, the sulfol processing is carried out before forming the conductive metal layer by vapor deposition, and the same steps as described above are carried out to obtain a two-layer with a sulfur having a high etching rate and little or no pinhole. A printed circuit board for a mold can be achieved.

【0035】その他、プリント回路基板が高温耐熱雰囲
気中あるいは高温多湿中で使用される場合には、絶縁性
フィルムと導電性金属層の間に金属及びセラミックスか
らなるなる層を設けることにより達成することができ
る。金属及びセラミックスはチタン、クロム及びジルコ
ニウムが好ましく、酸素あるいは窒素雰囲気中でスパッ
タあるいはイオンプレ−ティングすることにより得られ
る。該酸化物及び窒化物はエッチング液である塩化第二
鉄及び塩化第二銅ではエッチングできないため、線間絶
縁抵抗の経時的安定性を確保するためチタン、クロム及
びジルコニウムとの酸化及び窒化率を99%以上にする
ことが好ましい。99%以下の場合には初期値と経時後
では線間絶縁抵抗は1桁程度変化する。また、膜厚につ
いては70オングストロ−ム以下のアイランド構造をし
た不連続膜が好ましい。連続膜の場合には、その後の導
電性金属膜との間で密着不良を起こすことがあり信頼性
に欠ける。
In addition, when the printed circuit board is used in a high temperature heat resistant atmosphere or in a high temperature and high humidity environment, it can be achieved by providing a layer made of metal and ceramics between the insulating film and the conductive metal layer. You can The metals and ceramics are preferably titanium, chromium and zirconium, and can be obtained by sputtering or ion plating in an oxygen or nitrogen atmosphere. Since the oxides and nitrides cannot be etched with ferric chloride and cupric chloride, which are etching solutions, the oxidation and nitridation rates of titanium, chromium and zirconium must be adjusted to ensure the stability of the line insulation resistance over time. It is preferably 99% or more. If it is less than 99%, the insulation resistance between lines changes by about one digit after the initial value. The film thickness is preferably a discontinuous film having an island structure of 70 Å or less. In the case of a continuous film, poor adhesion may occur between the continuous film and the conductive metal film, resulting in poor reliability.

【0036】絶縁性フィルムはプリント回路用基板に適
し且つ、蒸着、化学処理あるいはメッキに適したポリエ
チレンテレフタレ−ト、ポリフェニレンサルファイド、
ポリエ−テルケトン、芳香族ポリアミド、ポリアリレ−
ト、ポリイミド、ポリアミドイミド、ポリエ−テルイミ
ドなどを使用することができ、中でも高温耐熱性を有す
るポリイミドが最適である。
The insulating film is suitable for printed circuit boards and suitable for vapor deposition, chemical treatment or plating, polyethylene terephthalate, polyphenylene sulfide,
Polyetherketone, aromatic polyamide, polyaryle
, Polyimide, polyamideimide, and polyetherimide can be used, and among them, polyimide having high temperature heat resistance is most suitable.

【0037】また、上記2層型プリント回路用基板は銅
メッキ層上にエッチングレジストを塗布あるいはラミネ
−トし、UV露光、現像の後にエッチング液で回路パタ
−ンを形成し、部品実装部及び端子部以外の箇所にソル
ダ−レジストなどのマスキング剤をコ−ティングし、そ
の露出部にニッケル、パラジュ−ム、金、銀、スズ、ハ
ンダ、ロジュ−ム、白金またはそれらの化合物からなる
メッキ層を形成することにより本発明の2層型プリント
回路基板が得られる。
Further, in the above-mentioned two-layer type printed circuit board, an etching resist is applied or laminated on the copper plating layer, and after UV exposure and development, a circuit pattern is formed by an etching solution, and a component mounting portion and a component mounting portion are formed. A masking agent such as solder resist is coated on the parts other than the terminals, and the exposed part is plated with nickel, palladium, gold, silver, tin, solder, rhodium, platinum or a compound thereof. The two-layer type printed circuit board of the present invention is obtained by forming the.

【0038】かくして本発明によれば、2層型プリント
回路用基板で80ミクロンピッチ以下のファインパタ−
ンがスルホ−ル付きで、しかも高収率で作製できる。
Thus, according to the present invention, a fine pattern with a pitch of 80 μm or less on a two-layer type printed circuit board is used.
It can be produced in high yield with sulfone attached.

【0039】[0039]

【実施例】次に、実施例により、本発明を具体的に説明
するが、本発明は、これらに限定されるものではない。
EXAMPLES Next, the present invention will be specifically described by way of examples, but the present invention is not limited to these.

【0040】(実施例1)厚さ25ミクロンのロ−ル状
ポリイミドフィルム“カプトンV”(東レ・デュポン社
製)をコロナ放電処理で水が十分に濡れる72ダイン以
上まで処理し、次いで超音波洗浄機でゴミ及び異物の除
去を行った。核フィルムをスパッタリング装置にセット
し5×10-5ト−ルに排気した後、アルゴンガスで2×
10-3ト−ルに調整しニッケルをスパッタ電圧500V
で100オングストロ−ムの膜厚に蒸着し、核ニッケル
膜上に同様の方法で銅を3000オングストロ−ム蒸着
した。上記スパッタ操作を2回繰返し両面に銅層を形成
した。ピンホ−ル観察用として、片面をエッチアウトし
透過光と実態顕微鏡でピンホ−ル数をカウントした、そ
の結果を表2に示す。蒸着銅面を脱脂剤AZ−700
(カニング・ジャパン社製)で処理し、苛性ソ−ダにヒ
ドラジンを添加した混液中でピンホ−ルにより露出した
ポリイミド表面の活性化を行い、次にスズ・パラジュウ
ム混液中でスズ・パラジュウムを該表面に吸着させた。
その後、直に硫酸濃度50g/lの低濃度硫酸銅メッキ
液中で1A/dm2で0.5ミクロンの電気銅メッキを
行い、次いで硫酸濃度150g/lの高濃度硫酸銅メッ
キ液中で3A/dm2で8ミクロンの電気銅メッキを行
った。電気銅メッキ後のピンホ−ルを前記同様の方法で
カウントした結果を表2に示す。これにより、10ミク
ロン以下のピンホ−ルは1個/m2まで減少していた。
その後、感光性液体レジストをコ−ティングし60ミク
ロピッチ(銅導体30ミクロン−ギャップ30ミクロ
ン)の回路パタ−ン1024本のマスクを使い紫外線露
光と現像を行い、塩化第二鉄エッチング液で回路パタ−
ンを形成した。その回路パタ−ン50枚を150倍の実
態顕微鏡で観察しカケ(10ミクロン以上のカケは不合
格で、それが1024本中に1本以上あればその回路パ
タ−ンを不合格とする。)及び断線によるパタ−ンの良
否を判定した結果を表3に示す。これにより、100%
収率の回路パタ−ンが得られた。
Example 1 A roll-shaped polyimide film "Kapton V" (manufactured by DuPont Toray Co., Ltd.) having a thickness of 25 μm was treated by corona discharge treatment up to 72 dyne or more at which water was sufficiently wet, and then ultrasonic waves were applied. Dust and foreign substances were removed with a washing machine. The nuclear film was set in a sputtering device and evacuated to 5 × 10 −5 torr, then 2 × with argon gas.
Adjusted to 10 -3 torr and used nickel for sputtering voltage 500V.
Was evaporated to a film thickness of 100 angstroms, and copper was evaporated on the nuclear nickel film in the same manner as 3000 angstroms. The above-mentioned sputtering operation was repeated twice to form a copper layer on both surfaces. For pinhole observation, one side was etched out and the number of pinholes was counted with transmitted light and a real microscope. The results are shown in Table 2. Degreasing agent AZ-700 for evaporated copper surface
(Made by Canning Japan) to activate the exposed polyimide surface with pinholes in a mixed solution of hydrazine added to caustic soda, and then tin / palladium in a mixed solution of tin and palladium. Adsorbed on the surface.
Immediately thereafter, 0.5 μm electrolytic copper plating was performed at 1 A / dm 2 in a low concentration copper sulfate plating solution having a sulfuric acid concentration of 50 g / l, and then 3 A in a high concentration copper sulfate plating solution having a sulfuric acid concentration of 150 g / l. 8 micron electrolytic copper plating at / dm 2 . Table 2 shows the results of counting the pinholes after electrolytic copper plating by the same method as described above. As a result, the number of pinholes of 10 μm or less was reduced to 1 / m 2 .
After that, a photosensitive liquid resist was coated, and UV exposure and development were performed using 1024 masks of a circuit pattern of 60 micro pitch (30 μm of copper conductor-30 μm of gap), and the circuit was formed with an etching solution of ferric chloride. Pattern
Formed. Fifty circuit patterns are observed under a 150 × microscope, and chips (10% or more chips are rejected. If one or more of the 1024 lines are rejected, the circuit pattern is rejected. ) And the result of judging the quality of the pattern due to the disconnection are shown in Table 3. By this, 100%
A yielded circuit pattern was obtained.

【0041】次に、IC実装部及び端子部以外をポリイ
ミド系のレジストをコ−トした後、露出した銅回路パタ
−ン部に無電解ニッケルを5ミクロン、さらに無電解ボ
ンディング用金メッキを0.5ミクロン行い図2に示す
ファインピッチ2層型プリント回路基板を得た。
Next, after coating a polyimide-based resist except for the IC mounting portion and the terminal portion, electroless nickel of 5 μm and gold plating for electroless bonding were applied to the exposed copper circuit pattern portion. After performing 5 micron, a fine pitch two-layer type printed circuit board shown in FIG. 2 was obtained.

【0042】(比較例1)比較のため、実施例1と同じ
工程でニッケル及び銅をスパッタした後、ピンホ−ルを
カウントし、高濃度硫酸銅メッキ液で同様の条件で8.
5ミクロンの電解銅メッキを行い、銅膜厚を合せた後に
ピンホ−ルを同様の方法で測定した結果を表2に示す。
その後、同様の方法でパタ−ニングした回路パタ−ンに
ついて実態顕微鏡で観察した結果を表3に示す。これよ
り、電気銅メッキでピンホ−ルは約60%減少している
ものの、パタ−ニング後の収率は18%と悪く実用レベ
ルにはほど遠い。
(Comparative Example 1) For comparison, after nickel and copper were sputtered in the same process as in Example 1, the pinholes were counted and the high-concentration copper sulfate plating solution was used under the same conditions.
Table 2 shows the results of measuring the pinhole by the same method after performing electrolytic copper plating of 5 microns and adjusting the copper film thickness.
Then, the results of observing a circuit pattern patterned by the same method with an actual microscope are shown in Table 3. As a result, although the pinholes were reduced by about 60% by electrolytic copper plating, the yield after patterning was 18%, which is far from a practical level.

【0043】[0043]

【表2】 [Table 2]

【0044】[0044]

【表3】 (実施例2)厚さ50ミクロンのユ−ピレックス50S
(宇部興産社製)を用い実施例と同様の工程で前処理を
行い、75ダイン以上のヌレが確保できていることを確
認した。該フィルムをスパッタリング装置にセットし5
×105 ト−ルに排気した後、窒素ガスで2×103
−ル調整しジルコニウムを20オングストロ−ムに蒸着
し、次いで実施例1と同様の方法で銅を3000オング
ストロ−ム蒸着した。次にエキシマレ−ザ−でφ50ミ
クロンの貫通穴加工を行った後、実施例1と同様に湿式
法で導電性金属層を形成し、次いで電気銅メッキで銅層
を8ミクロン形成した。それに60ミクロンピッチのパ
タ−ニングを行った後、エッチング率を測定した結果、
6.8と図1の“A”と“B”の差の少ないシャ−プな
パタ−ンが得られた。
[Table 3] (Example 2) Upilex 50S having a thickness of 50 microns
(Manufactured by Ube Industries, Ltd.) was pretreated in the same process as in the example, and it was confirmed that wetting of 75 dyne or more was secured. Set the film in the sputtering device and
After evacuating to × 10 5 torr, 2 × 10 3 torr was adjusted with nitrogen gas to deposit zirconium to a thickness of 20 Å, and then copper was deposited to a thickness of 3000 Å in the same manner as in Example 1. . Next, after making through holes of φ50 μm with an excimer laser, a conductive metal layer was formed by a wet method as in Example 1, and then a copper layer was formed to 8 μm by electrolytic copper plating. After performing a 60 micron pitch pattern on it, the etching rate was measured.
6.8 and a sharp pattern with a small difference between "A" and "B" in FIG. 1 was obtained.

【0045】[0045]

【発明の効果】以上説明したように、本発明によれば、
従来収率が悪く量産化が難しいとされた80ミクロンピ
ッチ以下のスルホ−ル付きファインパタ−ンが高収率で
作製でき、電気・電子機器の高密度・高集積化の飛躍的
進歩が期待できる。
As described above, according to the present invention,
Fine patterns with sulphate of 80 micron pitch or less, which had been considered to be difficult to mass-produce in the past, can be produced with high yield, and dramatic progress in high density and high integration of electrical and electronic equipment is expected. it can.

【図面の簡単な説明】[Brief description of drawings]

【図1】:エツチング率測定用パターンを示す断面図FIG. 1 is a sectional view showing an etching rate measurement pattern.

【図2】:実施例1の2層型プリント回路基板の断面図FIG. 2 is a cross-sectional view of the two-layer printed circuit board according to the first embodiment.

【符号の説明】 1・・・絶縁性フィルム 2・・・銅層 3・・・エッチングレジスト 4・・・2層型プリント回路基板 5・・・絶縁性フィルム(カプトンV) 6・・・ニッケル蒸着層/銅蒸着層 7・・・低濃度硫酸銅層 8・・・高濃度硫酸銅層 9・・・無電解ニッケル/ボンディング用無電解金 10・・・30ミクロン銅回路パタ−ン 11・・・30ミクロンギャップ[Explanation of Codes] 1 ... Insulating film 2 ... Copper layer 3 ... Etching resist 4 ... Two-layer type printed circuit board 5 ... Insulating film (Kapton V) 6 ... Nickel Deposition layer / copper deposition layer 7 ... Low concentration copper sulfate layer 8 ... High concentration copper sulfate layer 9 ... Electroless nickel / Electroless gold for bonding 10 ... 30 micron copper circuit pattern 11. ..30 micron gap

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】絶縁性フィルム上に導電性金属層と銅メッ
キ層が順次形成されてなる2層型プリント回路用基板に
おいて、該銅メッキ層及び該導電性金属層を貫通して絶
縁性フィルム表面に達する貫通穴の存在数が10個/m
2以下であり、かつ該貫通穴の最大長さが10ミクロン
以下であることを特徴とする2層型プリント回路用基
板。
1. A two-layer type printed circuit board in which a conductive metal layer and a copper plating layer are sequentially formed on an insulating film, the insulating film penetrating the copper plating layer and the conductive metal layer. The number of through holes reaching the surface is 10 / m
2 or less, and two-layered printed circuit board, wherein the maximum length of the through hole is less than 10 microns.
【請求項2】前記絶縁性フィルムがポリエチレンテレフ
タレ−ト、ポリフェニレンサルファイド、ポリエ−テル
ケトン、芳香族ポリアミド、ポリアリレ−ト、ポリイミ
ド、ポリアミドイミド、およびポリエ−テルイミドの群
から選ばれたポリマーからなるフィルムであることを特
徴とする請求項1の2層型プリント回路用基板。
2. An insulating film made of a polymer selected from the group consisting of polyethylene terephthalate, polyphenylene sulfide, polyetherketone, aromatic polyamide, polyarylate, polyimide, polyamideimide, and polyetherimide. The two-layer type printed circuit board according to claim 1, wherein
【請求項3】接着剤層のない絶縁性フィルムの片面又は
両面に蒸着により導電性金属層をもうけ、次に導電性金
属が蒸着されず絶縁性フィルムが露出した箇所に化学的
方法により導電性金属層を吸着させ、さらに電気銅メッ
キ層を形成することを特徴とする請求項1及び2の2層
型プリント回路用基板の製造方法。
3. A conductive metal layer is provided on one or both sides of an insulating film having no adhesive layer by vapor deposition, and then a conductive metal is chemically deposited on the exposed portion of the insulating film without depositing conductive metal. 3. The method for manufacturing a two-layer type printed circuit board according to claim 1, wherein the metal layer is adsorbed and an electrolytic copper plating layer is further formed.
【請求項4】導電性金属層、銅メッキ層及び絶縁性フィ
ルムを貫通する貫通穴を有することを特徴とする請求項
1及び2の2層型プリント回路用基板。
4. The two-layer type printed circuit board according to claim 1, further comprising a through hole penetrating the conductive metal layer, the copper plating layer and the insulating film.
【請求項5】接着剤層のない絶縁性フィルムの片面又は
両面に蒸着により導電性金属層をもうけた後、あるいは
導電性金属層と銅メッキ層を順次もうけた後に、該導電
性金属層、銅メッキ層及び絶縁性フィルムを貫通する穴
加工を行い、穴加工により絶縁性フィルムが露出した箇
所及び絶縁性フィルムに導電性金属が蒸着されなかった
箇所に化学的方法により導電性金属層を吸着させ、さら
に電気銅メッキ層を形成することを特徴とする請求項4
の2層型プリント回路用基板の製造方法。
5. A conductive metal layer, which is obtained by depositing a conductive metal layer on one or both surfaces of an insulating film having no adhesive layer by vapor deposition, or by sequentially depositing a conductive metal layer and a copper plating layer. A hole is drilled through the copper plating layer and the insulating film, and the conductive metal layer is adsorbed by a chemical method at the location where the insulating film is exposed by the hole drilling and the location where the conductive metal is not deposited on the insulating film. And further forming an electrolytic copper plating layer.
2. A method for manufacturing a two-layer type printed circuit board.
【請求項6】前記絶縁性フィルムに貫通穴加工を行った
後、その両面及び貫通穴に蒸着により導電性金属層をも
うけ、ついで導電性金属が蒸着されず絶縁性フィルムが
露出した箇所に化学的方法により導電性金属層を吸着さ
せ、さらに電気銅メッキ層を形成することを特徴とする
請求項4の2層型プリント回路用基板の製造方法。
6. After the through hole is formed in the insulating film, a conductive metal layer is provided on both sides and the through hole by vapor deposition, and then the conductive metal is not deposited and the insulating film is exposed at the exposed area. 5. The method for manufacturing a two-layer type printed circuit board according to claim 4, wherein the conductive metal layer is adsorbed by a static method, and an electrolytic copper plating layer is further formed.
【請求項7】絶縁性フィルムと導電性金属層の間に金属
及びセラミックスからなる蒸着層をもうけたことを特徴
とする請求項1、2および4の2層型プリント回路用基
板。
7. The two-layer type printed circuit board according to claim 1, wherein a vapor deposition layer made of metal and ceramics is provided between the insulating film and the conductive metal layer.
【請求項8】請求項1、2および4の2層型プリント回
路用基板に回路パターン形成し、さらにニッケル、パラ
ジウム、金、銀、スズ、ハンダ、ロジウム、白金及びそ
れらの化合物の群から選ばれたメッキを形成せしめたこ
とを特徴とする2層型プリント回路基板。
8. A circuit pattern is formed on the two-layer type printed circuit board according to any one of claims 1, 2 and 4, and is further selected from the group consisting of nickel, palladium, gold, silver, tin, solder, rhodium, platinum and compounds thereof. A two-layer type printed circuit board, which is characterized in that the formed plating is formed.
JP12409396A 1996-04-22 1996-04-22 Two-layer type printed circuit board and manufacturing method thereof Pending JPH09289368A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12409396A JPH09289368A (en) 1996-04-22 1996-04-22 Two-layer type printed circuit board and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12409396A JPH09289368A (en) 1996-04-22 1996-04-22 Two-layer type printed circuit board and manufacturing method thereof

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2002204287A Division JP2003046223A (en) 2002-07-12 2002-07-12 Method of manufacturing two-layer printed circuit board

Publications (1)

Publication Number Publication Date
JPH09289368A true JPH09289368A (en) 1997-11-04

Family

ID=14876757

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12409396A Pending JPH09289368A (en) 1996-04-22 1996-04-22 Two-layer type printed circuit board and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JPH09289368A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013084975A (en) * 2012-12-12 2013-05-09 Tatsuta Electric Wire & Cable Co Ltd Shielding film for printed wiring board and method for manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013084975A (en) * 2012-12-12 2013-05-09 Tatsuta Electric Wire & Cable Co Ltd Shielding film for printed wiring board and method for manufacturing the same

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