JPH09288965A - Manufacture of electron emitter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently cause electron emission at low gate voltages and achieve stabilization of radiation currents resulting from a chip end and its surface configuration. SOLUTION: An SiO2 layer is formed on a silicon substrate 11 and machined into a predetermined size to form an insulating-layer pattern 13, and after a chip 14 is formed by the plasma etching of the top of the silicon substrate 11 using a fluorine gas with the pattern 13 as a mask, an SiO2 layer 15 is formed on the silicon substrate 11 and the insulating layer pattern 13. After an SiO2 layer 16 is further formed on the surface of the chip 13, a gate electrode layer 17 is formed on the SiO2 layer 15, and after the stack of the insulating layer pattern 13, the SiO2 layer 15, and the gate electrode layer 17 formed on the chip 14 is removed by etching, the end of the chip 14 is subjected to anisotropic etching using an alkali metal hydroxide.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an electron-emitting device using field emission, and more particularly to a method for forming a semiconductor electron-emitting chip.

[0002]

2. Description of the Related Art FIG. 2 is a diagram showing a structure of, for example, a Spindt-type electron-emitting device as an electron-emitting device that has been conventionally proposed. FIG. 2 (a) is an enlarged cross-sectional view of an essential part, and FIG.
Is a plan view from above. In FIG. 2, a silicon insulating film 3 having a mortar-shaped opening 2 is formed in a substantially central portion thereof on a low resistance silicon substrate 1 having a size of about 2 mm square, and a bottom portion inside the opening 2 is formed. A minute conical projection (hereinafter referred to as a chip) 4 made of the same silicon member is formed integrally on the exposed silicon substrate 1.

Further, the opening 2 on the silicon insulating film 3
In the peripheral portion of the gate electrode 5 made of, for example, Mo material or the like.
Are formed so that the openings 6 are aligned with the openings 2 of the silicon insulating film 3. In this case, the gate electrode 5 is
The inner diameter of the opening 6 is smaller than that of the opening 2 of the silicon insulating film 3, and the peripheral edge of the opening 6 is formed close to the tip of the chip 4 at an interval of about 1 to 2 μm. Has become.

In such a structure, a DC drive voltage of 50 to 250 V, which makes the gate electrode 5 a positive voltage, is applied between the gate electrode 5 and the silicon substrate 1 to concentrate the electric field on the tip portion of the chip 4. As a result, electrons were taken out from the tip of the chip 4 into a vacuum. This phenomenon causes electrons to be emitted from a solid body into a vacuum based on the quantum mechanical tunneling phenomenon, and is also called a field emitter or a cold emitter.

Generally, an electron in a metal or semiconductor cannot be normally ejected into a vacuum because it is lower than a vacuum level by a work function qφ (eV), but a strong electric field (10 ⁹ V) from the outside like this field emitter. / M or more), the potential barrier becomes extremely thin, and electrons can tunnel through that part and jump out into a vacuum. Utilizing this electron emission, for example, a light source that emits an electron beam to a fluorescent screen. It is possible to manufacture an electron-emitting device for display tubes.

In the electron-emitting device having such a structure, the semiconductor used as the electrode material has a relatively high work function or electron affinity (energy required to extract electrons from a substance into a vacuum) of 4 to 6 eV. Chip 4
In order to efficiently cause electron emission from the
It is necessary to sharpen the tip of the chip 4 to have a radius of curvature of about 10 nm, or to make the opening diameter of the opening 6 of the gate electrode 5 as small as possible to bring the inner peripheral edge thereof extremely close to the tip of the chip 4. there were.

[0007]

However, in such a structure of the electron-emitting device, the work function or electron affinity (energy required to extract electrons from a substance into a vacuum) of a commonly used electrode material is large. Since a high driving voltage has to be applied, this driving voltage causes ionization of the residual gas, the ions sputter-etch the surface of the chip 4, and the chip 4 is easily damaged, which makes the operation unstable. Along with this, the life becomes short. Further, the emission current becomes unstable and the electron emission efficiency fluctuates greatly due to the contamination state of the tip portion of the chip 4 due to the sputtering and the effect of the residual gas in the vacuum.

That is, when silicon is used as the electron-emitting device, as shown in the band energy diagram of FIG. Unless high energy of 4 eV or more is applied to the electron e ⁻ existing in B (conduction band: conduction band), E. It cannot exceed A (electron affinity). However, when a high voltage is applied, the band bends, and internal electrons are tunneled through the thin barrier and released into the vacuum. In addition, as shown in FIG. 3B, when the surface charge of silicon is large, the electrons e ⁻ are forced to the inside of the depletion layer, and extra energy is required for the electrons e ⁻ to exceed the depletion layer. This inevitably requires a high voltage to be applied, and it is necessary to apply an electric field necessary to draw out electrons into the vacuum evenly exceeding the electron affinity to each chip with variations in the shape of the tip of the chip. Have difficulty. Therefore, when trying to obtain a large electron emission current, there is a problem that local current concentration occurs and the chip 4 is damaged. It should be noted that in FIGS. B indicates a valence band.

Further, the electron affinity itself changes due to contamination of the chip surface due to gas adhesion and the like, damage to the chip due to plasma gas used during chip manufacture, and damage to the chip due to collision of ions accelerated by a strong external electric field. However, there is a problem that the emission current is greatly changed.

Therefore, the present invention has been made to solve the above-mentioned conventional problems, and its purpose is to:
An object of the present invention is to provide a method for manufacturing an electron-emitting device capable of efficiently emitting electrons with a low gate voltage. Another object of the present invention is to provide a method of manufacturing an electron-emitting device that can stabilize the emission current due to the tip of the chip and its surface shape and improve the reliability of the electron emission characteristics. .

[0011]

In order to achieve the above-mentioned object, the method of manufacturing an electron-emitting device according to the present invention comprises a step of forming a conical protrusion on a silicon substrate by plasma etching using a fluorine-based gas. The conical protrusions are anisotropically etched using an alkali metal hydroxide to sharpen the conical protrusions so that the conical protrusions have a uniform shape. is there.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. 1 (a) to (i)
FIG. 4A is a cross-sectional view in each step for explaining an embodiment of a method for manufacturing an electron-emitting device according to the present invention. First, as shown in FIG. 1A, the surface of a low resistance n-type silicon substrate [crystal orientation (110) plane] 11 having a specific resistance of several Ω · cm is oxidized by a thermal oxidation method to a thickness of about 0.4 μm. SiO
_Two layers 12 are formed. Next, this SiO ₂ layer 12 is photoetched into a square of about 5 μm square with a hydrofluoric acid etchant to form a square insulating layer pattern 13 as shown in FIG. 2B.

Then, as shown in FIG. 1 (c), the silicon substrate 1 is formed by using the insulating layer pattern 13 as an etching mask.
1 is plasma-etched and processed into a substantially conical shape to form a chip 14. This plasma etching is for forming the tip of the chip 14, and CF ₄ + O ₂
A high-frequency plasma is generated in the mixed gas, and radicals F in the plasma chemically react with the silicon substrate 11, etching progresses, and the upper portion of the silicon substrate 11 under the rectangular insulating layer pattern 13 described above is chipped. Process into a shape. Here, the reaction product becomes a Si _X F _Y gas and is discharged out of the system. In this case, the plasma etching forms a prototype of the chip 14 having a height of about 1.5 μm.

Next, as shown in FIG. 1D, a SiO ₂ layer 15 is vapor-deposited on the silicon substrate 11 and the insulating layer pattern 13 by electron beam vapor deposition to a thickness of about 1.5 μm.
In this case, the SiO ₂ layer 15 is not formed by the vapor deposition method because the tip end has the insulating layer pattern 13 on the surface (inclined surface) of the chip 14.

Next, thermal oxidation of the silicon substrate 11 is performed again so that the surface of the chip 14 has a thickness of about 1 as shown in FIG.
A μ ₂ SiO ₂ layer 16 is formed. Next, as shown in FIG. 1F, a molybdenum (Mo) metal is vapor-deposited on the SiO ₂ layer 15 by electron beam vapor deposition to a thickness of about 0.3 μm to form a gate electrode layer 17.

Next, when etching is performed using an HF-based etchant, the SiO ₂ layer 16 on the surface of the chip 14 and the multilayer film structure (insulating layer pattern 13, SiO ₂ layer 15) mounted on the tip of the chip 14 are etched. , Gate electrode layer 17)
Are dissolved, and SiO _{2 on} the periphery of the chip 14 is further dissolved.
The inner sidewall of layer 15 is side etched. Next, as shown in FIG. 1 (h), the gate electrode layer 17 formed on the SiO ₂ layer 15 is etched to remove unnecessary portions with an etchant containing hydrofluoric acid and nitric acid, thereby forming a predetermined shape. The gate electrode 18 of is formed.

Next, the gate electrode structure thus formed is immersed in a potassium hydroxide (KOH) solution having a predetermined concentration for a predetermined time, and the chip 14 is anisotropically etched.
By this anisotropic etching process, the tip 14 having a rounded tip is shaped into a tip 19 having a sharp tip as shown in FIG. 1 (i), and the sharpness of each tip 19 is constant. Becomes In addition, the chip 19 shaped by performing anisotropic etching on the chip 14 is formed.
The surface contamination and surface level are reduced, and an electron-emitting device capable of stable electron emission is completed.

In the silicon substrate used for forming the chip, the shape of the tip of the chip is determined by the crystal orientation of the silicon substrate.
For example, if the (110) plane of a silicon substrate is used, it becomes an octagonal pyramid, and similarly, if the (100) plane becomes a quadrangular pyramid,
Similarly, the (111) plane has a triangular pyramid.

In the above-described embodiment, the anisotropic etching using the KOH solution utilizes the fact that the silicon substrate has etching characteristics depending on the crystal orientation, and as another etchant, Ethylenediamine or hydrazine can be used.

When single crystal silicon is etched by using these etchants, the etching rate greatly differs depending on the crystal orientation plane, and there are a plane having a remarkably high etching rate and a plane having a remarkably high etching rate, and the ratio becomes about 600 times. It may extend. In the case of the KOH etchant mentioned above,
The etching rate ratio between the (110) plane and the (111) plane of silicon is about this.

Further, in the above-described embodiment, the reason why the anisotropic etching is performed in the final step is that the tip 14 is already plasma-etched to have a substantially conical shape, and only the tip portion of the tip 14 is formed. If anisotropic etching is performed, it can be performed easily in a short time.

The chip 14 has been subjected to various treatments and contaminations (contamination due to the attachment of other atoms other than the intended one) during various manufacturing processes.
The surface layer of No. 4 was significantly damaged. This damage is
Surface levels are formed on the silicon surface, pushing up the barrier height and pushing electrons near the surface into the interior, which is a major obstacle to field emission (see FIG. 3). Since the surface damage of the silicon can be almost removed by the anisotropic etching in the final step, the clean surface of the silicon can be used in a normal state.

Further, in the above-described embodiment, the chip 1
Plasma etching was performed to mold the shape of No. 4, and anisotropic etching was performed at the final stage. This is because the shapes of a large number of chips 14 are fixed and height is adjusted by plasma etching. This is because the tip portion is etched, and when anisotropic etching is performed from the beginning, the shapes of the chips 14 become irregular, and the heights of the chips 14 are often formed differently.

[0024]

As described above, according to the method for manufacturing an electron-emitting device according to the present invention, after the pyramidal protrusion is formed on the silicon substrate by plasma etching using a fluorine-based gas, the pyramidal protrusion is formed. By sharpening the tips of the pyramidal protrusions by anisotropic etching using an alkali metal hydroxide, the tips of the multiple pyramidal protrusions can be made uniform in shape, so that electrons can be generated at a low gate voltage. It is possible to achieve efficient emission and to stabilize the electron emission current caused by the tip of the chip and its surface shape, which can greatly improve the reliability of electron emission characteristics. The effect is obtained.

[Brief description of drawings]

FIG. 1 is a cross-sectional view in each step for explaining an embodiment of a method for manufacturing an electron-emitting device according to the present invention.

FIG. 2 is a diagram illustrating a configuration of a conventional electron-emitting device.

FIG. 3 is a diagram showing band energy and band bending of n-type silicon.

[Explanation of symbols]

11 ... Silicon substrate, 12 ... SiO ₂ layer, 13 ... Insulating layer pattern, 14 ... Conical protrusion (chip), 15 ... SiO ₂
Layer, 16 ... SiO ₂ layer, 17 ... Gate electrode layer, 18 ... Gate electrode, 19 ... Chip.

Claims (1)

[Claims] 1. A silicon substrate, a conical protrusion formed so as to project on the silicon substrate, an insulating layer formed around the conical protrusion on the silicon substrate, and the insulating layer formed on the insulating layer. A gate electrode that covers a peripheral portion of the conical protrusion and is provided with an opening near the tip of the conical protrusion, and supplies a DC drive voltage between the silicon substrate and the gate electrode. In the method of manufacturing an electron-emitting device in which electrons are emitted from the tip end of the conical protrusion into a vacuum by forming a first insulating layer on the silicon substrate, the first insulating layer is formed in a predetermined manner. A step of forming an insulating layer pattern by processing the insulating layer pattern as a mask, and forming a conical protrusion on the silicon substrate by plasma etching using a fluorine-based gas by using the insulating layer pattern as a mask; Forming a second insulating layer on the substrate and the insulating layer pattern; forming a third insulating layer having a thickness smaller than that of the second insulating layer on the surface of the conical protrusion; A step of forming a gate electrode layer on the second insulating layer; the insulating layer pattern formed on the conical protrusions;
A step of etching away the laminated structure of the insulating layer and the gate electrode layer, and a step of subjecting at least the tip of the conical protrusion to anisotropic etching using an alkali metal hydroxide. Method of manufacturing electron-emitting device.