JPH09283722A - Method of increasing surface area of capacitor structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily keep a capacitor structure at required capacity by forming a pad polysilicon layer and utilizing the side area increasing with increase of the thickness of this layer. SOLUTION: A pad polysilicon layer 3 and partial sections 'of an NSG layer 2 on a Si substrate 1 are etched to form contact holes 4, a second polycrystalline Si layer 5 is formed at 615-635 deg.C above the Si layer 3 and in the contact holes 4 and a roughly cut hemispherical polycrystalline Si layer 6 is formed at 575 deg.C so that the surface area is a capacitor's surface area. The capacitor area is limited and both the Si layers 6, 5 and part of the Si layer 3 are etched to expose the side faces 31 and partial sections 21 of the NSG layer 2. Owing to the surface are of the Si layer 6 and side faces 31 a capacitor structure is obtained which is capable of required capacity easily in a 0.38μm process.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for increasing the surface area of a capacitor structure, and more particularly to a method for increasing the surface area of a capacitor structure applied to a 0.38 μm process or less.

[0002]

2. Description of the Related Art Taking a semiconductor process of a 16M dynamic RAM currently manufactured as an example, a capacitor structure is usually formed with one rough-cut hemispherical polycrystalline silicon layer, and this rough-cut hemispherical polycrystalline silicon hemisphere is formed. The specific surface area is utilized to form the capacitor surface area required for the process.

A method of forming the surface area of this conventional capacitor structure will be described with reference to FIGS. 2A to 2E are flowcharts of a conventional method for forming a surface area of a capacitor structure.

In FIG. 2A, NSG (Nondop) is formed on a silicon substrate 1 by chemical vapor deposition (CVD) or low pressure CVD.
ed Silicon Glass) layer 2, a contact hole is patterned by photolithography, and the NSG layer 2 is partially etched to form a contact hole 3.

FIG. 2 (b) shows a low pressure chemical vapor deposition (LPC) method.
VD) above NSG layer 2 and contact hole 3
It is shown that a polycrystalline silicon layer 4 having a thickness of 500 Å is formed therein.

In FIG. 2C, a rough-cut hemispherical polycrystalline silicon layer 5 having a thickness of 850 Å is formed above the polycrystalline silicon layer 4 by low pressure CVD, and the hemispherical polycrystalline silicon layer 5 is formed. It has been shown that the surface area is the capacitor surface area.

In FIG. 2D, a capacitor area is defined by photolithography, a part of the hemispherical polycrystalline silicon layer 5 and the polycrystalline silicon layer 4 are etched, and a partial area 21 of the NSG layer 2 is formed. Have been shown to be exposed.

In FIG. 2 (e), ONO (oxide-on-nitride-on-on-) is formed by low pressure CVD over a portion of the region 21 of the hemispherical polycrystalline silicon layer 5 and the NSG layer 2.
Oxide layer 6; another polycrystalline silicon layer 7 is formed above the ONO layer 6 by low pressure CVD; and a portion of the polycrystalline silicon layer 7 and ONO layer 6 by photolithography and etching techniques. It has been shown to etch areas to expose a portion of NSG layer 2. This ONO layer 6 always functions as a dielectric layer between the lower capacitor plate and the upper capacitor plate in the manufacturing process of the dynamic RAN.

[0009]

However, the method of forming the surface area of the capacitor required for the process by forming the hemispherical polycrystalline silicon layer is currently facing a serious problem.

That is, once the process technology is 0.45μ
When the m process is improved to 0.38 μm process,
In order to reduce the production cost according to the reduction of the wafer area and the increase of the number of wafer elements on the wafer area,
As the process technology becomes smaller and smaller, it is necessary to increase the surface area of the capacitor structure in order to secure the capacity required for the capacitor structure. In other words, the thickness of the formed hemispherical polycrystalline silicon layer must be increased. As a result, the hemispherical polycrystalline silicon layer fills the contact hole to the extent that the entire surface area of the hemispherical polycrystalline silicon layer is reduced. Therefore, the conventional method for forming the hemispherical polycrystalline silicon layer to form the capacitor surface area required for the process is 0.38.
When applied to a capacitor structure formed by the μm process, there arises a problem of insufficient capacity.

From this, a new process capable of maintaining a required capacity by forming a capacitor structure even in the 0.38 μm process is required,
The present invention meets this need.

A main object of the present invention is to provide a method of increasing the capacity of a capacitor structure by increasing the lateral area of the capacitor structure.

[0013]

A method of increasing the surface area of a capacitor structure according to the present invention comprises: (a) forming a first polycrystalline silicon layer over a silicon substrate having an oxide layer;
(B) A contact hole is patterned to form a contact hole by etching an oxide layer and a part of the first polycrystalline silicon layer, and (c) Above the first polycrystalline silicon layer and the contact hole. Forming a second polycrystalline silicon layer therein, and (d) forming a third polycrystalline silicon layer having the surface area of the capacitor as the surface area of the capacitor above the second polycrystalline silicon layer, and e). The third polycrystalline silicon layer, the second polycrystalline silicon layer, and the first
A portion of the polycrystalline silicon layer of
Exposing a side surface of the polysilicon layer and a partial area of the oxide layer, the surface area of the third polysilicon layer increased by the thickness of the first polysilicon layer, and the exposed surface area of the third polysilicon layer. The side surface of the first polycrystalline silicon layer increases the surface area of the capacitor.

Preferably, prior to the step (a), the step (a ₁ ) of forming an oxide layer on the silicon substrate is performed. The oxide layer in the step (a ₁ ) is usually formed of NSG having a thickness of about 2700 to 3300Å.
It is preferably a (Nondoped Silicon Glass) layer.

The oxide layer is preferably formed by a CVD method. Further, it is desirable that the oxide layer, the first polycrystalline silicon layer, the second polycrystalline silicon layer, or the third polycrystalline silicon layer be formed by a low pressure CVD method.

The thickness of the first polycrystalline silicon layer formed in the step (a) is usually 2000-5.
It is preferably about 000Å. The first polycrystalline silicon layer formed in step (a) is preferably pad polysilicon.

The contact holes in step (b) are preferably formed by photolithography and etching techniques.

Preferably, the thickness of the second polycrystalline silicon layer formed in step (c) is usually 450.
It is preferably about 550 Å, preferably 475 to 525 Å, particularly about 500 Å. The temperature for forming the second polycrystalline silicon layer in the step (c) is
It is preferably 635 to 651 ° C.

The third polycrystalline silicon layer in step (d) is preferably rough-cut hemispherical polycrystalline silicon. The thickness of the third polycrystalline silicon layer formed in the step (d) is 775 to 93.
5Å. The temperature for forming the third polycrystalline silicon layer in the step (d) is usually 570 to 570.
About 580 ° C, preferably 573 to 577 ° C, especially about 5
It is preferably 75 ° C.

The method of etching a part of the third polycrystalline silicon layer, the second polycrystalline silicon layer and the first polycrystalline silicon layer in the step (e) is preferably photolithography and etching. Made by technology.

Preferably, after step (e), a dielectric layer is further formed (e ₁ ) above the third polysilicon layer and a partial area of the oxide layer, and (e ₂ ) this dielectric layer is formed. Forming a fourth polycrystalline silicon layer above the layer,
(E ₃ ) Etching the fourth polycrystalline silicon layer and a partial area of the dielectric layer to expose a portion of the oxide layer.

The dielectric layer or the fourth polycrystalline silicon layer is preferably formed by a low pressure CVD method.

The dielectric layer in step (e ₁ ) is
It is preferably an ONO (oxide-on-nitrido-on-oxide) layer.

The thickness of the fourth polycrystalline silicon layer formed in the step (e ₂ ) is usually 1100 to 13
It is preferably about 00Å, particularly about 1200Å.

The method of etching the fourth polycrystalline silicon layer and the dielectric layer in the step (e ₃ ) is as follows.
Preferably, photolithography and etching techniques are used.

[0026]

By the steps (a) to (e) of the present invention,
The surface area of the third polycrystalline silicon layer increased by the thickness of the first polycrystalline silicon layer and the exposed side surfaces of the first polycrystalline silicon layer increase the surface area of the capacitor. Increases capacity.

That is, by simply increasing the number of processes for forming the pad polysilicon layer (first polycrystalline silicon layer), the side area increased by the thickness of the pad polysilicon layer can be used to easily increase the number of layers to 0. In the 3 μm process, the capacitor structure can be maintained at a required capacity, and its adaptability can elastically adjust to a desired capacity.

An embodiment of the present invention will be described below with reference to the drawings. Needless to say, the technical scope of the present invention should not be limited to this embodiment, and various changes and modifications are allowed without departing from the technical idea of the appended claims and the detailed description.

1 (a)-(f) are method flow charts of a preferred embodiment of the present invention. First, in FIG. 1 (a), a thickness of 3000 Å is obtained by CVD or low pressure CVD.
An NSG (Nondoped Silicon Glass) layer 2 is formed on the silicon substrate 1.

Then, by the CVD or low pressure CVD method,
A pad polysilicon layer 3 having a thickness of 2000 to 5000Å is formed above the NSG layer 2.

Next, in FIG. 1B, the contact holes are patterned by photolithography, and the partial regions of the pad polysilicon layer 3 and the NSG layer are etched to form the contact holes 4.

Then, in FIG. 1C, low pressure CVD
Method, a second polycrystalline silicon layer 5 having a thickness of 500Å is formed above the pad polysilicon layer 3 and in the contact hole 4 under the condition of the deposition temperature of 615 to 635 ° C.

Further, in FIG. 1D, low pressure CVD
According to the method, at a deposition temperature of 575 ° C., a thickness of 775-
The rough-cut hemispherical polycrystalline silicon layer 6 of 935 Å is formed above the second polycrystalline silicon layer 5 so that the surface area thereof becomes the surface area of the capacitor.

Further, referring to FIG. 1E, the capacitor area is defined by photolithography, and the hemispherical polycrystalline silicon layer 6, the second polycrystalline silicon layer 5 and a part of the pad polysilicon layer 3 are removed. Etching to expose the side surface 31 of the pad polysilicon layer and the partial area 21 of the NSG layer 2, and the surface area of the hemispherical polycrystalline silicon layer 6 increased by the thickness of the pad polysilicon layer 3. Side surface 3 of the exposed pad polysilicon layer 3
1 increases the surface area of the capacitor.

Further, in FIG. 1 (f), low pressure CVD
The ONO (oxide-on-nitride-on-oxide) layer 7 having a thickness of 75Å is formed by the dynamic RAM.
Is formed above the hemispherical polycrystalline silicon layer 6 and the partial area 21 of the NSG layer 2 so as to always act as a dielectric layer between the lower capacitor plate and the upper capacitor plate in the process of FIG. 7, a fourth polycrystalline silicon layer 8 having a thickness of 1200Å is formed on the upper side of 7 by a low pressure CVD method, and the fourth polycrystalline silicon layer 8 and the ON layer are formed by photolithography and etching techniques.
A partial area of the O layer 7 is etched to expose a part of the NSG layer 2.

[0036]

As can be seen from the steps of the method for increasing the surface area of a capacitor structure shown in this embodiment, by increasing the number of processes for forming the pad polysilicon layer, the thickness of the pad polysilicon layer is increased. The increased lateral area can be used to maintain the required capacity of the capacitor structure in the 0.38 μm process relatively easily. Further, it can be elastically adjusted to a desired capacity due to its applicability. That is, the present invention is
The capacity required for the capacitor structure can be adjusted simply by controlling the thickness of the pad polycrystalline silicon layer. For example, if the pad polysilicon layer has a thickness of 2000 Å, the capacity reaches 25 fF / cell, and if the pad polysilicon layer has a thickness of 5000 Å, the capacity reaches 37 fF / cell. On the other hand, when the conventional technology is applied to the 0.38 μm process to form the capacitor structure, the capacity reaches only 18 fF / cell, and it is not possible to meet the demand for higher capacity. From this, it is clear that the effect of the present invention is improved.

In summary, according to the method of the present invention, it is easy to achieve 0.3 without increasing the number of process steps.
It is possible to obtain a capacitor structure that can maintain the required capacity in the 8 μm process.

[Brief description of drawings]

FIG. 1 is a method flow chart of a preferred embodiment of the present invention.

FIG. 2 is a flow chart of a method of forming a conventional capacitor structure.

Claims (9)

[Claims] 1. A method of increasing the surface area of a capacitor structure, comprising: (a) forming a first polycrystalline silicon layer above a silicon substrate having an oxide layer, and (b) patterning a contact hole to form an oxide layer. And etching a part of the first polycrystalline silicon layer to form a contact hole,
(C) forming a second polycrystalline silicon layer above the first polycrystalline silicon layer and in the contact hole;
(D) forming a third polycrystalline silicon layer having a capacitor surface area which is the configured surface area above the second polycrystalline silicon layer, and e) the third polycrystalline silicon layer and the second polycrystalline silicon layer. The polycrystal silicon layer and a part of the first polycrystal silicon layer are respectively etched to expose a side surface of the first polycrystal silicon layer and a partial area of the oxide layer, and the first polycrystal silicon layer. The third increased by the layer thickness
Increasing the surface area of the capacitor by the surface area of the polycrystalline silicon layer and the exposed side surfaces of the first polycrystalline silicon layer, the method of increasing the surface area of the capacitor structure. 2. Prior to said step (a), (a ₁ )
A step of forming an oxide layer on the silicon substrate by a CVD method is performed, and the oxide layer has a thickness of 2700 to
The method according to claim 1, wherein the method is 3300Å. 3. The oxide layer, the first polycrystalline silicon layer, the second polycrystalline silicon layer or the third polycrystalline silicon layer is formed by a low pressure CVD method. Item 2. The method according to Item 2. 4. The first polysilicon layer formed in step (a) is pad polysilicon.
Poly) layer, having a thickness of 2000-5000Å. 5. The method according to claim 1, wherein the contact hole in the step (b) is formed by photolithography and etching technique. 6. The thickness of the second polycrystalline silicon layer formed in the step (c) is 450 to 550Å, and the temperature for forming this polycrystalline silicon layer is 615 to 6
It is 35 degreeC, The method of Claim 1 characterized by the above-mentioned. 7. The third polycrystalline silicon layer in the step (d) is rough-cut hemispherical polycrystalline silicon, and the thickness of the third polycrystalline silicon layer is 775 to 93.
It is in the range of 5Å, and the temperature that forms it is 570-58.
It is 0 degreeC, The method of Claim 1 characterized by the above-mentioned. 8. The method of etching a part of the third polycrystalline silicon layer, the second polycrystalline silicon layer and the first polycrystalline silicon layer in the step (e) is a photolithography method. A method according to claim 1, characterized in that it is made by an etching technique. 9. After step (e), further comprising:
(E ₁ ) forming a dielectric layer above the third polycrystalline silicon layer and a partial area of the oxide layer, the dielectric layer having an ONO (oxide-on-nitride) thickness of 67.5 to 82.5Å. -On-oxide) layer and (e ₂ ) low pressure C
A fourth polycrystalline silicon layer is formed above the dielectric layer by the VD method, and the thickness of this layer is 1100 to 1300Å, and (e ₃ ) the fourth polycrystalline silicon layer and the dielectric layer. 3. The method according to claim 2, comprising the step of etching the partial areas to expose a part of the oxide layer.