JPH09283704A - Chip composite electronic component - Google Patents

Chip composite electronic component

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Publication number
JPH09283704A
JPH09283704A JP8962196A JP8962196A JPH09283704A JP H09283704 A JPH09283704 A JP H09283704A JP 8962196 A JP8962196 A JP 8962196A JP 8962196 A JP8962196 A JP 8962196A JP H09283704 A JPH09283704 A JP H09283704A
Authority
JP
Japan
Prior art keywords
electrode
upper electrode
dielectric
chip
protective film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8962196A
Other languages
Japanese (ja)
Other versions
JP3865428B2 (en
Inventor
Shinichi Makita
紳一 牧田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koa Corp
Original Assignee
Koa Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koa Corp filed Critical Koa Corp
Priority to JP08962196A priority Critical patent/JP3865428B2/en
Publication of JPH09283704A publication Critical patent/JPH09283704A/en
Application granted granted Critical
Publication of JP3865428B2 publication Critical patent/JP3865428B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To provide a chip composite electronic component in which a wider setting range of the capacitance of a capacitor and the resistance of a resistor is designed. SOLUTION: A first electrode 3 and a second electrode 4 are formed on a surface of an electrical insulation substrate with split grooves, apart for each unit chip substrate 2. A first upper electrode 7 whose area in designed to obtain a prescribed capacitance is formed on an upper face of a dielectric material 6 formed on an upper face of the first electrode 3. A first protective film 10 is formed to cover the dielectric material 6 and the first upper electrode 7 while leaving a second upper electrode 8 exposed that is formed on an upper face of the first upper electrode 7. A resistance film 11 is formed over an upper face of the first protective film 10 and also on part of the second upper electrode 8. A second protective film 12 is formed over an upper electrode 9 and the resistance film 11 while leaving part of the first electrode 3 and the second electrode 4 exposed. A CR chip composite component 1 is formed by splitting the substrate along the split grooves.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、基板上に電極、誘
電体および抵抗皮膜が積層形成されたチップ複合電子部
品に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip composite electronic component in which electrodes, a dielectric and a resistance film are laminated on a substrate.

【0002】[0002]

【従来の技術】従来、この種のチップ複合電子部品(以
下、「CRチップ型複合部品」という。)としては、例
えば図2に示す構造のものが知られている。
2. Description of the Related Art Conventionally, as this type of chip composite electronic component (hereinafter referred to as "CR chip type composite component"), for example, a structure shown in FIG. 2 is known.

【0003】この図2に示す従来のCRチップ型複合部
品21は、図2(a)に示すように、絶縁性の基板22上
に、離間して一対の電極23,24をそれぞれ形成し、図2
(b)に示すように、一方の電極23の上面から離間する
電極23,24間の基板22上に亘って誘電体25を印刷形成し
ている。さらに、誘電体25の上面には、図2(c)に示
すように所定のコンデンサ容量値となる面積を覆って中
間電極26が形成され、図2(d)に示すように、中間電
極26の一部を露出して誘電体25を覆って例えばガラス質
の絶縁性の第1の保護膜27が被覆形成されている。そし
て、図2(e)に示すように、第1の保護膜27にて被覆
されずに露出する中間電極26の上面には抵抗皮膜28が形
成され、図2(f)に示すように、抵抗皮膜28および他
方の電極24に跨がって上部電極29が形成され、図2
(g)に示すように、一対の電極23,24の一部を露出し
て誘電体25、中間電極26、抵抗皮膜28および上部電極29
を覆って例えば合成樹脂の絶縁性の第2の保護膜30が被
覆形成されている。
As shown in FIG. 2A, the conventional CR chip type composite component 21 shown in FIG. 2 has a pair of electrodes 23 and 24 formed on an insulating substrate 22 so as to be spaced apart from each other. Figure 2
As shown in (b), a dielectric 25 is formed by printing over the substrate 22 between the electrodes 23, 24 separated from the upper surface of the one electrode 23. Further, as shown in FIG. 2C, an intermediate electrode 26 is formed on the upper surface of the dielectric 25 so as to cover an area having a predetermined capacitor capacitance value. As shown in FIG. 2D, the intermediate electrode 26 is formed. Is covered with a first protective film 27 made of, for example, glass and has an insulating property so as to cover a part of the dielectric 25 and to expose the dielectric 25. Then, as shown in FIG. 2E, a resistance film 28 is formed on the upper surface of the intermediate electrode 26 which is exposed without being covered with the first protective film 27, and as shown in FIG. The upper electrode 29 is formed across the resistance film 28 and the other electrode 24, and
As shown in (g), a part of the pair of electrodes 23, 24 is exposed to expose the dielectric 25, the intermediate electrode 26, the resistive film 28, and the upper electrode 29.
An insulating second protective film 30 made of, for example, synthetic resin is formed so as to cover the above.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、上記図
2に示す従来のCRチップ型複合部品21は、抵抗皮膜28
を中間電極26の上面に設け、この抵抗皮膜28と他方の電
極24とを上部電極29にて接続する構成であるため、抵抗
皮膜28の形成可能範囲に限りがあり、大きな抵抗値が得
られない問題がある。
However, the conventional CR chip type composite part 21 shown in FIG.
Is formed on the upper surface of the intermediate electrode 26, and the resistance film 28 and the other electrode 24 are connected by the upper electrode 29.Therefore, the range in which the resistance film 28 can be formed is limited, and a large resistance value can be obtained. There is no problem.

【0005】本発明は、上記問題点に鑑みなされたもの
で、抵抗値の設定範囲が大きく採れるチップ複合電子部
品を提供することを目的とする。
The present invention has been made in view of the above problems, and an object of the present invention is to provide a chip composite electronic component in which a resistance value can be set in a large range.

【0006】[0006]

【課題を解決するための手段】請求項1記載のチップ複
合電子部品は、絶縁性のチップ基体と、このチップ基体
上にそれぞれ離間して形成された一対の電極と、これら
一対の電極の一方の上面に形成された誘電体と、この誘
電体の上面に設けられた上部電極と、この上部電極の一
部を露出して前記誘電体を覆って設けられた絶縁性の第
1の保護膜と、前記上部電極および前記他方の電極間に
形成された抵抗皮膜と、前記一対の電極のそれぞれ一部
を露出して前記囲部、前記誘電体および前記上部電極を
覆って設けられた絶縁性の第2の保護膜とを具備したも
ので、一対の電極の一方の上面に誘電体を形成し、この
誘電体の上面に上部電極を形成し、この上部電極の一部
を露出し誘電体を覆って絶縁性の第1の保護膜を形成
し、上部電極および他方の電極間に抵抗皮膜を形成する
ため、抵抗皮膜は第1の保護膜の上面に被覆した状態と
なり、上部電極から他方の電極までの距離が長く採れ、
抵抗皮膜の抵抗値の増大が可能となり、抵抗値の設定範
囲を大きく採れる。
A chip composite electronic component according to claim 1 is an insulating chip base, a pair of electrodes formed separately on the chip base, and one of the pair of electrodes. Formed on the upper surface of the dielectric, an upper electrode provided on the upper surface of the dielectric, and an insulating first protective film provided by exposing a part of the upper electrode and covering the dielectric. And a resistance film formed between the upper electrode and the other electrode, and an insulating property that exposes a part of each of the pair of electrodes and covers the surrounding portion, the dielectric, and the upper electrode. A second protective film, a dielectric is formed on the upper surface of one of the pair of electrodes, an upper electrode is formed on the upper surface of the dielectric, and a part of the upper electrode is exposed to expose the dielectric. To form an insulating first protective film to cover the upper electrode and To form the inter-electrode to the resistance film of square, resistive film becomes a state of being coated on the upper surface of the first protective film, caught long distance from the upper electrode to the other electrode,
The resistance value of the resistance film can be increased, and the resistance value setting range can be widened.

【0007】請求項2記載のチップ複合電子部品は、請
求項1記載のチップ複合電子部品において、上部電極
は、誘電体の上面に所定の容量値となる面積を覆って設
けられた第1の上部電極とこの第1の上部電極の上面に
設けられた第2の上部電極とを備え、第1の保護膜は、
第2の上部電極を露出して前記誘電体および第1の上部
電極を覆って設けられたもので、誘電体の上面に所定の
容量値となる面積で第1の上部電極を形成し、この第1
の上部電極の上面に第2の上部電極を形成し、第2の上
部電極を露出し誘電体および第1の上部電極を覆って第
1の保護膜を形成するため、誘電体の所定の容量値が確
保できるとともに、第2の上部電極を最小限の面積で形
成することにより上部電極が縮小し、容易に小型軽量化
が図れ、コストが低減する。
A chip composite electronic component according to a second aspect is the chip composite electronic component according to the first aspect, in which the upper electrode is provided on the upper surface of the dielectric so as to cover an area having a predetermined capacitance value. An upper electrode and a second upper electrode provided on the upper surface of the first upper electrode are provided, and the first protective film is
The second upper electrode is exposed to cover the dielectric and the first upper electrode, and the first upper electrode is formed in an area having a predetermined capacitance value on the upper surface of the dielectric. First
Forming a second upper electrode on the upper surface of the upper electrode of the first electrode, exposing the second upper electrode, and covering the dielectric and the first upper electrode to form the first protective film, a predetermined capacitance of the dielectric is formed. The value can be secured, and by forming the second upper electrode with a minimum area, the upper electrode can be reduced in size, the size and weight can be easily reduced, and the cost can be reduced.

【0008】[0008]

【発明の実施の形態】以下、本発明のチップ複合電子部
品の実施の一形態の構成を図面を参照して説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of an embodiment of a chip composite electronic component of the present invention will be described below with reference to the drawings.

【0009】図1(g)において、1はチップ複合電子
部品であるCRチップ型複合部品で、このCRチップ型
複合部品1は、例えばアルミナ焼結体にて略直方体の平
板状に形成された電気絶縁性を有するチップ基体2を有
している。そして、このチップ基体2の上面には、対向
する一対の縁に位置し離間して、例えば銀(Ag)−白
金(Pt)系や銀(Ag)−パラジウム(Pd)系の導
電ペーストにて一対の第1の電極3および第2の電極4
がそれぞれ形成されている。
In FIG. 1 (g), reference numeral 1 denotes a CR chip type composite component which is a chip composite electronic component. The CR chip type composite component 1 is formed of, for example, an alumina sintered body into a substantially rectangular parallelepiped flat plate shape. It has a chip base 2 having electrical insulation. Then, on the upper surface of the chip substrate 2, a pair of opposing edges are located and separated from each other by, for example, a silver (Ag) -platinum (Pt) -based or silver (Ag) -palladium (Pd) -based conductive paste. A pair of first electrode 3 and second electrode 4
Are formed respectively.

【0010】また、一方の面積の大きい第1の電極3の
上面には、離間する第1の電極3および第2の電極4間
のチップ基体2上に亘ってペロブスカイト型鉛系複合酸
化物を含有するペーストなどにて形成された強誘電材料
の誘電体6が被覆形成されている。
On the upper surface of the first electrode 3 having a large area, a perovskite-type lead-based complex oxide is provided over the chip substrate 2 between the first electrode 3 and the second electrode 4 which are separated from each other. A dielectric material 6 made of a ferroelectric material formed of a contained paste or the like is formed by coating.

【0011】さらに、誘電体6の上面には、第1の電極
3および第2の電極4と同材料の例えば銀(Ag)−白
金(Pt)系や銀(Ag)−パラジウム(Pd)系の導
電ペーストにて第1の上部電極7が所定の面積で被覆形
成されている。すなわち、コンデンサの容量は、 C=ε0 εr S/d C:コンデンサの容量 ε0 :真空中の誘電率 εr :比誘電率 S:誘電体の被覆面積 d:誘電体の膜厚 で表され、コンデンサ容量Cは誘電体6の被覆面積に比
例することから、第1の上部電極7を所定の面積で被覆
形成して所望のコンデンサ容量が設定される。
Furthermore, on the upper surface of the dielectric 6, for example, a silver (Ag) -platinum (Pt) system or a silver (Ag) -palladium (Pd) system made of the same material as the first electrode 3 and the second electrode 4 is used. The first upper electrode 7 is formed to cover a predetermined area with the conductive paste. That is, the capacitance of the capacitor is C = ε 0 ε r S / d C: capacitance of the capacitor ε 0 : dielectric constant in vacuum ε r : relative permittivity S: coating area of the dielectric d: film thickness of the dielectric Since the capacitor capacitance C is proportional to the coating area of the dielectric body 6, the desired capacitor capacitance is set by coating the first upper electrode 7 with a predetermined area.

【0012】また、この第1の上部電極7の上面には、
第1の電極3、第2の電極4および第1の上部電極7と
同材料の例えば銀(Ag)−白金(Pt)系や銀(A
g)−パラジウム(Pd)系の導電ペーストにて第2の
上部電極8が被覆形成され、第1の上部電極7および第
2の上部電極8にて上部電極9が構成されている。
On the upper surface of the first upper electrode 7,
The same material as that of the first electrode 3, the second electrode 4 and the first upper electrode 7, for example, silver (Ag) -platinum (Pt) system or silver (A).
g) -Palladium (Pd) -based conductive paste covers and forms the second upper electrode 8, and the first upper electrode 7 and the second upper electrode 8 form the upper electrode 9.

【0013】そして、第2の上部電極8を露出し、誘電
体6および第1の上部電極7を覆って例えば珪酸鉛ガラ
スや硼珪酸鉛ガラスなどのガラス皮膜状の絶縁性の第1
の保護膜10が被覆形成されている。
Then, the second upper electrode 8 is exposed and the dielectric 6 and the first upper electrode 7 are covered to cover the dielectric 6 and the first upper electrode 7.
The protective film 10 is formed by coating.

【0014】また、露出する第2の上部電極8の上面に
は、第1の保護膜10の上面から第2の上部電極8の上面
に亘って例えば酸化ルテニウム(RuO2 )を主成分と
するルテニウム系のペーストなどにて抵抗皮膜11が被覆
形成されている。なお、この抵抗皮膜11の抵抗値は、 R=ρl/S R:抵抗値 ρ:比抵抗 l:抵抗皮膜11の長さ寸法 S:抵抗皮膜11の断面積 で表され、抵抗値Rは長さlに比例する。
On the exposed upper surface of the second upper electrode 8, the main component is, for example, ruthenium oxide (RuO 2 ) from the upper surface of the first protective film 10 to the upper surface of the second upper electrode 8. The resistance film 11 is formed by coating with a ruthenium-based paste or the like. The resistance value of the resistance film 11 is represented by R = ρl / S R: resistance value ρ: specific resistance l: length dimension of the resistance film 11 S: cross-sectional area of the resistance film 11, and the resistance value R is a long value Proportional to l.

【0015】そして、一対の第1の電極3および第2の
電極4の一部である端部縁部分を露出し、誘電体6、第
1の上部電極7、第2の上部電極8および抵抗皮膜11を
覆って例えばエポキシ系やポリイミド系などの合成樹脂
にて第2の保護膜12が被覆形成されて、CRチップ型複
合部品1が形成されている。
Then, the edge portions which are a part of the pair of the first electrode 3 and the second electrode 4 are exposed to expose the dielectric 6, the first upper electrode 7, the second upper electrode 8 and the resistor. A second protective film 12 is formed by covering the film 11 with a synthetic resin such as an epoxy resin or a polyimide resin to form the CR chip type composite component 1.

【0016】次に、上記CRチップ型複合部品1の製造
動作を図面を参照して説明する。
Next, the manufacturing operation of the CR chip type composite component 1 will be described with reference to the drawings.

【0017】図示しないアルミナ焼結体よりなる電気絶
縁性の基板に、あらかじめ図1(a)に示す各チップ基
体2毎に分割されるように、表面に線状で深さ方向が略
V字状の分割溝を縦横に形成しておく。
An electrically insulating substrate made of an alumina sintered body (not shown) is linear on the surface and is approximately V-shaped in the depth direction so as to be divided in advance for each chip substrate 2 shown in FIG. 1 (a). -Shaped dividing grooves are formed vertically and horizontally.

【0018】そして、表面の各チップ基体2毎に分割溝
によって区画された単位片毎に、図1(a)に示すよう
に、各チップ基体2の長さ方向の両端部に長手方向の略
中央から一端側に偏位した位置で離間して相対するよう
に、例えば銀(Ag)−白金(Pt)系や銀(Ag)−
パラジウム(Pd)系の導電ペーストを例えば10μm
〜12μmの膜厚で印刷し、例えば約850℃で約10
分間焼成して、各チップ基体2毎に第1の電極3および
第2の電極4を相対して形成する。
Then, as shown in FIG. 1A, for each unit piece partitioned by a dividing groove for each chip base 2 on the front surface, at the longitudinal end portions of each chip base 2 in the longitudinal direction. For example, silver (Ag) -platinum (Pt) -based or silver (Ag)-is so arranged as to face each other while being offset from the center to one end side.
Palladium (Pd) -based conductive paste is, for example, 10 μm
Print with a film thickness of ~ 12 μm, for example, about 10 at about 850 ° C.
After firing for a minute, the first electrode 3 and the second electrode 4 are formed facing each other for each chip substrate 2.

【0019】次に、図1(b)に示すように、チップ基
体2の表面に分割溝で縦横に区分された各単位片毎の第
1の電極3の上面に、例えばペロブスカイト型鉛系複合
酸化物および有機質ビヒクルを含有する強誘電ペースト
を約35μm〜40μmの膜厚で印刷し、850℃で1
0分間焼成して第1の電極3の上面に強誘電性の誘電体
6を形成する。
Next, as shown in FIG. 1 (b), for example, a perovskite-type lead-based composite is formed on the upper surface of the first electrode 3 of each unit piece vertically and horizontally divided by a dividing groove on the surface of the chip substrate 2. A ferroelectric paste containing an oxide and an organic vehicle is printed at a film thickness of about 35 μm to 40 μm, and is printed at 850 ° C. for 1 hour.
By firing for 0 minutes, the ferroelectric dielectric 6 is formed on the upper surface of the first electrode 3.

【0020】そして、この誘電体6の上面に、図1
(c)に示すように、第1の電極3および第2の電極4
と同材質の例えば銀(Ag)−白金(Pt)系や銀(A
g)−パラジウム(Pd)系の導電ペーストを例えば1
0μm〜12μmの膜厚で所定のコンデンサ容量が得ら
れる面積で印刷し、例えば約850℃で約10分間焼成
して、各チップ基体2毎に第1の上部電極7を形成す
る。
Then, on the upper surface of this dielectric body 6, as shown in FIG.
As shown in (c), the first electrode 3 and the second electrode 4
Same material as silver (Ag) -platinum (Pt) system or silver (A
g) -palladium (Pd) -based conductive paste, for example, 1
The first upper electrode 7 is formed for each chip base 2 by printing in an area where a predetermined capacitor capacity is obtained with a film thickness of 0 μm to 12 μm and baking at, for example, about 850 ° C. for about 10 minutes.

【0021】さらに、この第1の上部電極7の上面に、
図1(d)同材質の例えば銀(Ag)−白金(Pt)系
や銀(Ag)−パラジウム(Pd)系の導電ペーストを
例えば20μmの膜厚で印刷し、例えば約850℃で約
10分間焼成して、各チップ基体2毎に第2の上部電極
8を形成する。
Further, on the upper surface of the first upper electrode 7,
FIG. 1 (d) A conductive paste of the same material, for example, silver (Ag) -platinum (Pt) or silver (Ag) -palladium (Pd), is printed with a film thickness of 20 μm, for example, at about 850 ° C. for about 10 By firing for a minute, the second upper electrode 8 is formed for each chip substrate 2.

【0022】そして、図1(e)に示すように、第2の
上部電極8を露出し、誘電体6および第1の上部電極7
を覆って例えば珪酸鉛ガラスなどのガラスフリットと有
機質ビヒクルとよりなるガラスペーストを約20μmで
印刷し、例えば約850℃で約10分間焼成して、各チ
ップ基体2毎に第1の保護膜10を形成する。
Then, as shown in FIG. 1E, the second upper electrode 8 is exposed, and the dielectric 6 and the first upper electrode 7 are exposed.
And a glass paste made of a glass frit such as lead silicate glass and an organic vehicle is printed at a thickness of about 20 μm and baked at, for example, about 850 ° C. for about 10 minutes to provide a first protective film 10 for each chip substrate 2. To form.

【0023】次に、図1(f)に示すように、露出する
第2の上部電極8の上面に、第1の保護膜10の上面から
第2の上部電極8の上面に亘って例えば酸化ルテニウム
(RuO2 )を主成分とするルテニウム系の導電ペース
トを約30μm〜40μmの膜厚で印刷し、例えば約8
50℃で約10分間焼成して、各チップ基体2毎に抵抗
皮膜11を形成する。
Next, as shown in FIG. 1F, on the exposed upper surface of the second upper electrode 8, for example, oxidation is performed from the upper surface of the first protective film 10 to the upper surface of the second upper electrode 8. A ruthenium-based conductive paste containing ruthenium (RuO 2 ) as a main component is printed with a film thickness of about 30 μm to 40 μm, and for example, about 8 μm.
By firing at 50 ° C. for about 10 minutes, the resistance film 11 is formed for each chip substrate 2.

【0024】そして、図1(g)に示すように、各単位
片毎の端部縁部分である一対の第1の電極3および第2
の電極4の一部を露出し、誘電体6、第1の上部電極
7、第2の上部電極8および抵抗皮膜11を覆って例えば
エポキシ系やポリイミド系などの合成樹脂を印刷し、例
えば200℃で約30間加熱して、各チップ基体2毎に
第2の保護膜12を被覆形成する。
Then, as shown in FIG. 1 (g), a pair of the first electrode 3 and the second electrode 3 which are the edge portions of each unit piece.
Part of the electrode 4 is exposed, the dielectric 6, the first upper electrode 7, the second upper electrode 8 and the resistance film 11 are covered, and a synthetic resin such as an epoxy or polyimide resin is printed. By heating at 30 ° C. for about 30 minutes, the second protective film 12 is coated and formed on each chip substrate 2.

【0025】この後、分割溝から基板を分割してCRチ
ップ型複合部品1を形成する。
After that, the substrate is divided from the dividing grooves to form the CR chip type composite component 1.

【0026】上記実施の形態によれば、一方の第1の電
極3の上面に形成した誘電体6の上面に上部電極9を形
成し、この上部電極9の一部を露出して誘電体6を覆っ
て絶縁性の第1の保護膜10を形成し、上部電極9および
他方の第2の電極4間に第1の保護膜10の上面に亘って
抵抗皮膜11を形成するため、従来のものに比して抵抗皮
膜11の長さを長く採れ、抵抗皮膜11の抵抗値を増大で
き、積層状態や材料の設定などにより、電極と同程度の
極めて低い抵抗値から大きな抵抗値まで設定でき、抵抗
値の設定範囲を大きく採れる。
According to the above embodiment, the upper electrode 9 is formed on the upper surface of the dielectric 6 formed on the upper surface of the one first electrode 3, and a part of the upper electrode 9 is exposed to expose the dielectric 6. To form an insulating first protective film 10 and to form a resistance film 11 between the upper electrode 9 and the other second electrode 4 over the upper surface of the first protective film 10. The length of the resistance film 11 can be made longer than that of the one, and the resistance value of the resistance film 11 can be increased, and the resistance value can be set from an extremely low resistance value similar to the electrode to a large resistance value depending on the laminated state and material settings. The resistance value can be set in a large range.

【0027】また、上部電極9を第1の上部電極7およ
び第2の上部電極8の2層構造としたため、所定のコン
デンサ容量となる面積で第1の上部電極7を形成し、第
2の上部電極8は必要面積のみ、すなわち誘電体6およ
び抵抗皮膜11を介した第1の電極3から第2の電極4へ
の回路構成を形成するのに必要な第1の上部電極7より
小さい面積で形成するのみでよく、大きなコンデンサ容
量を容易に設定できるとともに、上部電極9を縮小で
き、容易に小型軽量化が図れ、コストを低減できる。
Further, since the upper electrode 9 has a two-layer structure of the first upper electrode 7 and the second upper electrode 8, the first upper electrode 7 is formed in an area that provides a predetermined capacitor capacity, and the second upper electrode 7 is formed. The upper electrode 8 has only a required area, that is, an area smaller than that of the first upper electrode 7 required to form a circuit configuration from the first electrode 3 to the second electrode 4 through the dielectric 6 and the resistance film 11. It is possible to easily set a large capacitor capacity, reduce the size of the upper electrode 9, easily reduce the size and weight, and reduce the cost.

【0028】したがって、コンデンサ容量および抵抗値
の双方の設定範囲を容易に大きく設定できるCRチップ
型複合部品1を容易に小型軽量化でき、安価に提供でき
る。
Therefore, the CR chip type composite component 1 in which both the setting range of the capacitor capacity and the setting value of the resistance value can be easily set can be easily reduced in size and weight, and can be provided at low cost.

【0029】なお、上記実施の形態において、必要に応
じて電極を複数設けたり、誘電体6および抵抗皮膜11を
複数積層形成してもできる。
In the above embodiment, a plurality of electrodes may be provided or a plurality of dielectrics 6 and resistive films 11 may be formed in a laminated manner, if necessary.

【0030】また、CRチップ型複合部品1の端面、さ
らには裏面に亘って、第1の電極3および第2の電極4
に連続させて第1の端部電極および第2の端部電極、第
1の裏面電極および第2の裏面電極を、第1の電極3お
よび第2の電極4と同材質にて同様に印刷形成してもよ
い。
Further, the first electrode 3 and the second electrode 4 are provided over the end surface of the CR chip type composite component 1 and further over the back surface thereof.
Then, the first end electrode and the second end electrode, the first back surface electrode and the second back surface electrode are similarly printed with the same material as the first electrode 3 and the second electrode 4. You may form.

【0031】そして、誘電体6は、ペロブスカイト型鉛
系複合酸化物に限らず、いずれの誘電材料にて形成して
もよい。さらに、同様に、第1の保護膜10をガラス質に
て形成し、第2の保護膜12を合成樹脂にて形成したが、
いずれの絶縁性材料にて形成してもできる。そして、第
1の電極3および第2の電極4についても、銀(Ag)
−白金(Pt)系や銀(Ag)−パラジウム(Pd)系
に限らず、いずれの導電材料にて形成してもよく、ま
た、各第1の電極3、第2の電極4、誘電体6、上部電
極9、抵抗皮膜11、第1の保護膜10および第2の保護膜
12は、蒸着など印刷形成に限られるものではない。
The dielectric 6 is not limited to the perovskite type lead-based composite oxide and may be formed of any dielectric material. Further, similarly, the first protective film 10 is made of glass and the second protective film 12 is made of synthetic resin.
It can be formed of any insulating material. Then, for the first electrode 3 and the second electrode 4 as well, silver (Ag)
-Platinum (Pt) -based or silver (Ag) -palladium (Pd) -based may be used, and may be formed of any conductive material, and each first electrode 3, second electrode 4, dielectric 6, upper electrode 9, resistance film 11, first protective film 10 and second protective film
12 is not limited to print formation such as vapor deposition.

【0032】[0032]

【発明の効果】請求項1記載のチップ複合電子部品によ
れば、一対の電極の一方の上面に形成した誘電体の上面
に上部電極を形成し、この上部電極の一部を露出し誘電
体を覆って絶縁性の第1の保護膜を形成し、上部電極お
よび他方の電極間に抵抗皮膜を形成するため、抵抗皮膜
は第1の保護膜の上面に被覆した状態となり、上部電極
から他方の電極までの距離を長く採れ、抵抗皮膜の抵抗
値を容易に増大でき、抵抗値の設定範囲を大きく採れ
る。
According to the chip composite electronic component of the first aspect, the upper electrode is formed on the upper surface of the dielectric formed on the upper surface of one of the pair of electrodes, and a part of the upper electrode is exposed to expose the dielectric. To form an insulative first protective film and form a resistance film between the upper electrode and the other electrode, so that the resistance film covers the upper surface of the first protective film, and The distance to the electrode can be made long, the resistance value of the resistance film can be easily increased, and the setting range of the resistance value can be made large.

【0033】請求項2記載のチップ複合電子部品によれ
ば、請求項1記載のチップ複合電子部品に加え、誘電体
の上面に所定の容量値となる面積で第1の上部電極を形
成し、この第1の上部電極の上面に第2の上部電極を形
成し、第2の上部電極を露出し誘電体および第1の上部
電極を覆って第1の保護膜を形成するため、誘電体の所
定の容量値が大きな設定範囲で確保できるとともに、第
2の上部電極を最小限の面積で形成することにより上部
電極を縮小でき、容易に小型軽量化でき、コストを低減
できる。
According to the chip composite electronic component of the second aspect, in addition to the chip composite electronic component of the first aspect, the first upper electrode is formed on the upper surface of the dielectric with an area having a predetermined capacitance value, A second upper electrode is formed on the upper surface of the first upper electrode, and the second upper electrode is exposed to cover the dielectric and the first upper electrode to form a first protective film. The predetermined capacitance value can be ensured in a large setting range, and by forming the second upper electrode with a minimum area, the upper electrode can be reduced in size, the size and weight can be easily reduced, and the cost can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明のチップ複合電子部品の実施の一形態の
製造工程を示す説明図である。
FIG. 1 is an explanatory view showing a manufacturing process of an embodiment of a chip composite electronic component of the present invention.

【図2】従来例のチップ複合電子部品の製造工程を示す
説明図である。
FIG. 2 is an explanatory view showing a manufacturing process of a conventional chip composite electronic component.

【符号の説明】[Explanation of symbols]

1 チップ複合電子部品であるCRチップ型複合部品 2 チップ基体 3 第1の電極 4 第2の電極 6 誘電体 7 第1の上部電極 8 第2の上部電極 9 上部電極 10 第1の保護膜 11 抵抗皮膜 12 第2の保護膜 1 CR chip type composite part which is a chip composite electronic part 2 Chip base 3 First electrode 4 Second electrode 6 Dielectric 7 First upper electrode 8 Second upper electrode 9 Upper electrode 10 First protective film 11 Resistive film 12 Second protective film

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 絶縁性のチップ基体と、 このチップ基体上にそれぞれ離間して形成された一対の
電極と、 これら一対の電極の一方の上面に形成された誘電体と、 この誘電体の上面に設けられた上部電極と、 この上部電極の一部を露出して前記誘電体を覆って設け
られた絶縁性の第1の保護膜と、 前記上部電極および前記他方の電極間に形成された抵抗
皮膜と、 前記一対の電極のそれぞれ一部を露出して前記囲部、前
記誘電体および前記上部電極を覆って設けられた絶縁性
の第2の保護膜とを具備したことを特徴とするチップ複
合電子部品。
1. An insulative chip base, a pair of electrodes formed on the chip base separately from each other, a dielectric formed on one upper surface of the pair of electrodes, and an upper surface of the dielectric. Formed between the upper electrode and the other electrode, an upper electrode provided on the upper electrode, an insulating first protective film that exposes a part of the upper electrode and covers the dielectric. A resistive film and an insulating second protective film that exposes a part of each of the pair of electrodes and covers the surrounding portion, the dielectric, and the upper electrode. Chip composite electronic component.
【請求項2】 上部電極は、誘電体の上面に所定の容量
値となる面積を覆って設けられた第1の上部電極とこの
第1の上部電極の上面に設けられた第2の上部電極とを
備え、 第1の保護膜は、第2の上部電極を露出して前記誘電体
および第1の上部電極を覆って設けられたことを特徴と
する請求項1記載のチップ複合電子部品。
2. The upper electrode comprises a first upper electrode provided on an upper surface of a dielectric material so as to cover an area having a predetermined capacitance value, and a second upper electrode provided on an upper surface of the first upper electrode. The chip composite electronic component according to claim 1, wherein the first protective film is provided so as to expose the second upper electrode and cover the dielectric and the first upper electrode.
JP08962196A 1996-04-11 1996-04-11 Chip composite electronic components Expired - Fee Related JP3865428B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP08962196A JP3865428B2 (en) 1996-04-11 1996-04-11 Chip composite electronic components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP08962196A JP3865428B2 (en) 1996-04-11 1996-04-11 Chip composite electronic components

Publications (2)

Publication Number Publication Date
JPH09283704A true JPH09283704A (en) 1997-10-31
JP3865428B2 JP3865428B2 (en) 2007-01-10

Family

ID=13975834

Family Applications (1)

Application Number Title Priority Date Filing Date
JP08962196A Expired - Fee Related JP3865428B2 (en) 1996-04-11 1996-04-11 Chip composite electronic components

Country Status (1)

Country Link
JP (1) JP3865428B2 (en)

Also Published As

Publication number Publication date
JP3865428B2 (en) 2007-01-10

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