JPH09282891A - Semiconductor apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a constitution enabling a semiconductor device using a multi-value memory cell storing 2-bit or more information to be compact. SOLUTION: A bit line pair consisting of a bit line BL1 and a bit line BLB1 is separated to an area 1 and an area 2 by a transfer gate 1. Accordingly, the bit line BL1 is electrically divided to a bit line A1 of the area 1 and a bit line B1 of the area 2. At the same time, the bit line BLB1 is electrically separated to a bit line A2 of the area 1 and a bit line B2 of the area 2. A couple capacitor CC is set between the bit lines A1 and B2, and a couple capacitor CC is installed between the bit lines A2 and B1.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a semiconductor device, and more particularly, to a semiconductor memory device for a multi-valued memory cell.

[0002]

2. Description of the Related Art In recent years, the size of semiconductor devices has been further reduced, and this tendency has been increasing. For this reason, a multi-valued memory capable of storing multi-bit information in one memory cell has been developed in order to reduce the size of a storage device which is a kind of semiconductor device.

In this multi-valued memory, the threshold value of a memory cell is changed in multiple steps in an EEP-ROM so that information of 1 bit or more of one memory cell can be stored, D
There are various methods such as a method in which a charge stored in a memory cell in a RAM is divided into multiple stages so that information of one bit or more in one memory cell can be stored.

Since the semiconductor memory device using these multi-valued memory cells can store multi-valued information in one cell, cells that can store only 1-bit information in one cell (hereinafter referred to as 1 It is possible to reduce the number of memory cells as compared with a conventional memory device including a bit cell), and thus to reduce the size of the memory device, and thus the semiconductor device having the memory device as one component. It is a thing.

However, a semiconductor memory device using a multi-valued cell must use a circuit configuration different from the conventional circuit configuration for driving a 1-bit cell due to the peculiarity of the cell.

[0006] For example, in a 1-bit cell, one sense amplifier is usually provided for each bit line, but a DRAM using a 4-value multi-valued cell is disclosed in Japanese Patent Laid-Open No. Sho 63-63.
As described in JP-A-149900, three sense amplifiers are required for one bit line. This is shown in FIG.

The operation of the conventional example shown in FIG. 7 will be briefly described below.

For each memory cell connected to the word lines WL0 to WL255, 0 when the power supply voltage is Vcc,
(1/3) Vcc, (2/3) Vcc, Vcc, total 4
Information is stored. The dummy cells connected to the dummy word lines DWL1 and DWL2 have (1/6) Vcc and the dummy word lines DWL3 and DWL4.
And (5/6) Vcc are stored in advance in the dummy cells connected to the dummy word lines DWL5 and DWL6.

Here, the read operation of the data stored in the cell 1 composed of the n-type MOS transistor and the capacitor will be described. The cells in the figure, including the dummy cells, have the same configuration as the cell 1.

First, the gate selection line TG becomes high level (hereinafter referred to as H level), and the word lines WL0 to 85.
And region 1 consisting of dummy word lines DWL1 and DWL2, region 2 consisting of word lines WL86-171 and dummy word lines DWL3-4, and region 3 consisting of word lines WL172-255 and dummy word lines DWL5-6. , Are connected to bit lines BL1 and BLB1.

After precharging, the word line WL0 becomes H level, and the information in the cell 1 is read to the bit line BL1. Here, the information in the cell 1 is, for example, (2/3) Vc
c.

After that, the gate selection line TG becomes low level (hereinafter referred to as L level), and the regions 1, 2 and 3 are electrically isolated from each other.

After that, the bit line BL to which the cell 1 is connected is connected.
The dummy cell connected to the bit line BLB1 corresponding to 1 is activated, and the information of the dummy cell is read. That is, the dummy word lines DWL2, DWL4, DWL6 go to the H level.

Next, the sense amplifier activation signal SEN is set to H.
Level, and the sense amplifiers SA11, SA12, SA
13 is activated. Thus, in the area 1, the data of the bit line BL1 is (2/3) Vcc, and the data of the bit line BLB1 is the data of the dummy cell (1/1).
6) Since it is Vcc, the sense amplifier SA11 outputs an H level to the data line D1, and outputs an L level to the data line D1 bar. Similarly, in the region 2, the data on the bit line BL1 is (2/3) Vcc and the data on the bit line BLB1 is (1/2) Vcc, which is the data of the dummy cell. Therefore, the sense amplifier SA12 is connected to the data line D2. Output an H level and output an L level to the data line D2 bar. In the area 3, the data of the bit line BL1 is (2
/ 3) Vcc and the data on the bit line BLB1 is (5/6) Vcc, which is the data of the dummy cell. Therefore, the sense amplifier SA13 outputs an L level to the data line D3 and an H level to the data line D3 bar. Output. That is, the data lines D1, D2, and D3 respectively have H, H,
An L-level signal is output.

Then, the data on these data lines are processed from the 3-bit information to 2-bit information by the data output circuit and output to the external device as 2-bit information. This is because the amount of information stored in the memory cell is quaternary, and the information can be originally expressed by 2 bits.

With the above description, the read operation of the conventional example shown in FIG. 7 is completed. The description of the write operation and the like is omitted.

[0017]

By the way, although a multi-valued cell has been developed, a sense amplifier having the same sensitivity as that of the conventional one is currently used. That is, the sense amplifier used in the 1-bit cell DRAM is used as it is. Therefore, assuming that the sense amplifier can sense when the difference between the memory cell information and the dummy cell information is equal to or more than ΔV, the capacity of the capacitor of the multi-level cell is, for example, three times the capacity of the 1-bit cell in the case of the 4-level cell. Is required.

In order to realize this triple capacity,
A configuration as shown in FIG. 9 can be considered. This is shown in FIG.
It will be described in comparison with the configuration of the bit cell.

In FIG. 8, an area of 2 × 2 is secured for one cell. And, of these, the area of 1 × 1 becomes the capacitor. Note that the distance between the capacitors is set to one. The configuration of FIG. 9 realizes triple capacity by using this cell arrangement as it is.
That is, one quaternary cell is realized with a cell area of two 1-bit cells in FIG. Here, the area of the capacitor is 1 × 3, and therefore, a capacity three times as large as one bit cell can be obtained.

However, this structure is not sufficient to reduce the size of the device. That is, with the configuration shown in FIG. 10, the capacitance of the capacitor is √3 × √3, and one cell area is (1 + √3) × (1 + √3),
That is, the area is about 7.5. This is smaller than one cell area of 2 × 4 in FIG. 9, which contributes to downsizing of the device.

However, even if the cell structure of FIG. 9 is used, in the structure of FIG. 7 in which three sense amplifiers are provided for one bit line, on the contrary, the area is increased and the multi-value cell is used. The merit was not fully exerted.

This will be described below with reference to FIGS. 11 and 12. FIG. 11 is a schematic configuration diagram in the case of storing 4-level information using a 1-bit cell. in this case,
Two 1-bit cell groups are formed, and two sense amplifiers are provided. Here, since the ratio of the area of the cell array section to the area including the sense amplifier section and the I / O outlet is usually 5: 1 to 3: 1, the ratio is described so as to be reflected. FIG. 12 is a schematic configuration diagram in the case where the same amount of information as in FIG. 11 is realized by a 4-level cell. In FIG. 12, three sense amplifiers are provided because one bit line requires three sense amplifiers. Note that the cell area ratios in FIGS. 11 and 12 are the same as the cell area ratios in FIGS. 8 and 10, and the sense amplifier uses the same sense amplifier in both FIGS. 11 and 12.

As is clear from comparing FIGS. 11 and 12, the area of FIG. 11 is (4 × 1) × 2 + (1 × 1) × 2.
= 10, and the area of FIG. 12 is 7.5+ (1 × 1) ×
3 = 10.5.

That is, when 4-valued information is required,
It can be seen that the device may be downsized when the device is configured using 1-bit cells.

That is, a DRAM using a conventional multi-valued cell
Then, in some cases, the size of the apparatus may be increased contrary to the purpose of developing the multi-value cell.

Therefore, it is an object of the present invention to provide a semiconductor device which meets the development purpose of a multi-valued cell, that is, a semiconductor device which uses a multi-valued cell and is smaller than a semiconductor device using a 1-bit cell.

[0027]

To this end, a semiconductor device according to the present invention comprises a first conductive means connected to form a conductive path between a first wiring and a second wiring. A second conductive means connected to form a conductive path between the third wiring and the fourth wiring, one end connected to the first wiring, and the other end connected to the fourth wiring. Connected first
A second capacitor having one end connected to the second wiring and the other end connected to the third wiring;
A first input terminal is connected to the first wiring, a second input terminal is connected to the third wiring, and applied to the first and second input terminals according to a first signal. Compare the potentials,
First comparing means for outputting the result to the first wiring and outputting an inverted signal of the result to the third wiring;
Is connected to the second wiring, a fourth input terminal is connected to the fourth wiring, and a potential applied to the third and fourth input terminals in response to a second signal is Comparing the result to the second wiring, and outputting an inverted signal of the result to the fourth wiring, the first and second conductive means comprising: In response to the third signal,
The method is characterized in that the conductive path is formed.

[0028]

With this structure, the semiconductor device according to the present invention has the first wiring and the second wiring electrically connected and the third wiring and the fourth wiring electrically connected similarly. The first and second conductive means electrically separate each other. Therefore, when the first comparison means performs the comparison operation in response to the first signal, the potentials of the fourth wiring and the second wiring are changed by the first and second capacitors.

That is, if the potential of the first wiring rises, the potential of the fourth wiring also rises, and if the potential of the third wiring falls, the potential of the second wiring also falls. After this change, the second
The 2-bit information can be immediately obtained from the information on the first and second wirings by operating the comparison means.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a circuit configuration of a memory cell section and a sense amplifier section showing a first embodiment of the present invention.
Here, as in the case of the conventional example, a configuration having a 4-level memory cell is shown. Therefore, the power supply voltage is Vcc for each memory cell.
Then, 0, (1/3) Vcc, (2/3) Vcc,
Any one of four pieces of information of Vcc is stored.
That is, these are 0, 1, 2, 3 for the external device.
It corresponds to four pieces of information. In addition, the dummy cells that existed in the conventional example do not exist.

A plurality of bit line pairs (BL1, BLB1)-
A plurality of memory cells are connected to (BLn, BLBn) (n represents an integer) and a plurality of word lines WL. The memory cell has an n-type MO as shown in cell 1.
It is composed of an S transistor and a capacitor. The memory cells other than the cell 1 have the same configuration.

In FIG. 1, a total of two sense amplifiers are provided for each bit line pair. Each bit line pair is divided into a region 1 and a region 2 by an n-type MOS transistor T1 whose gate is connected to the gate selection line TG. The stray capacitance CS1 generated in the bit line in the region 1 and the stray capacitance CS2 generated in the bit line in the region 2 are designed to have a ratio of 2: 1. To achieve such a capacity ratio,
There are a method of making a difference in the number of word lines in each area, and a method of actually providing a capacitor in a bit line although the number of word lines in each area is the same.

A coupling capacitor CC is provided for each bit line pair. This connection relationship is as shown in FIG.

FIG. 2 is a device schematic diagram showing an example of a semiconductor memory device formed on one chip by using the circuit shown in FIG. The multi-valued memory cell array 1 in this figure corresponds to the circuit shown in FIG.

This semiconductor memory device receives an RAS signal, a CAS signal, a write enable signal WE, and an output enable signal OE from an external device, for example, a CPU of a microprocessor, and reads data from the memory cell array 1 or the memory cell array 1 Write data to.

The operation of the semiconductor memory device will be described in detail below.

First, the case of reading data will be described. Here, in order to simplify the explanation, it is assumed that the data reading is to read the information of the cell 1 in FIG. Also,
It is assumed that the cell 1 stores information on (2/3) Vcc.

First, the control circuit 6 sets the bit line pair to (1 /
2) It is precharged to Vcc. At this time, the gate selection line TG is at the high active level, and therefore the MOS transistor T1 operates and the regions 1 and 2 are operated.
Are electrically connected.

When the RAS signal becomes low active level, the address information input to the address input terminal 11 is latched by the row address buffer 7 and the column address buffer 8. The row address buffer 7 immediately outputs the latched row address to the row decoder 5. At this time, the RAS signal becomes the low active level, so that the control circuit 6 stops the precharge operation of the bit line pair.

Since the control circuit 6 sets the row decoder activation signal SS1 to the high active level at the same time that the RAS signal becomes the active level, the row decoder 5 decodes the row address latched by the row address buffer 7. As a result, in the multi-valued memory cell array 1,
Word line WL1 goes to high active level, and cell 1
Information (2/3) Vcc is output to the bit line BL1.

It should be noted that when the information of the cell 1 is output to the bit line BL1, the potential of the bit line BL1 does not become the potential of that information. That is, when (2/3) Vcc which is the information of the cell 1 is output to the bit line BL1, the potential of the bit line BL1 does not become (2/3) Vcc. It changes from the precharged potential by a minute potential ΔV to be {(1/2) Vcc + ΔV}.
In FIG. 1, since the sense amplifier uses the same sense amplifier as the conventional example, this potential ΔV is designed to be a voltage at which the sense amplifier can perform a comparison operation. By the way, the information of cell 1 is 0, (1/3) Vcc,
When it is Vcc, the potential of the bit line BL1 is
{(1/2) Vcc-3ΔV}, {(1/2) Vcc-
ΔV}, {(1/2) Vcc + 3ΔV}.

After outputting the information from the cell 1 to the bit line, the control circuit 6 sets the gate selection line TG to the low inactive level to make the MOS transistor T1 inoperative and electrically separate the region 1 from the region 2. . Therefore, the bit line BL
1 is divided into bit line A1 and bit line B1, and bit line BLB1 is divided into bit line A2 and bit line B2. Further, the control circuit 6 sets the gate selection line TG to the inactive level and simultaneously sets the sense amplifier 1 activation signal SA1 to the high active level to operate the sense amplifier SA11 in the region 1. As a result, the sense amplifier SA11 outputs {(1/2) Vcc of the bit line Al.
+ ΔV} is compared with (1/2) Vcc of the bit line A2. Since the potential of the bit line A1 is larger, the bit line A1 is set to Vcc and the bit line A2 is set to 0 as a result.
That is, since .DELTA.V is very small, the potentials of both bit line A1 and bit line A2 increase or decrease by approximately (1/2) Vcc.

Therefore, as the potential of the bit line A1 rises, the potential of the bit line B2 rises by ΔV due to the increase / decrease of this potential, and the potential of the bit line A2 falls and the bit line B1 rises. Potential is ΔV
Just descend. That is, the potential of the bit line B2 is {(1
/ 2) Vcc + ΔV}, and the potential of the bit line B1 becomes (1/2) Vcc.

Here, the potential change ΔV of the bit lines B1 and B2 in the area 2 is obtained by previously adjusting the capacitance of the couple capacitor CC.

Specifically, if the memory capacity is Cs, the capacity of the divided bit line B1 is CB1, the highest voltage stored in the cell is VCC, and the lowest voltage is GND, the signal difference Vr of the voltage read from the cell is Since the transfer switch T1 is turned on during reading, the effective bit line capacitance is 3CB1, and Vr = VCC / (1 + 3CB1 / C
s). Therefore, the signal difference 2ΔV between each level is
2ΔV = VCC / (3 × (1 + 3CB1 / Cs)). The potential change xV obtained by the bit line having the potential of VCC / 2 with the amplitude of VCC / 2 in the couple capacitance CC is x
V = VCC / 2 (2CB / Cc + 1), which is Δ
Cc required to be equal to V is 2 from xV = ΔV
From CB1 / Cc + 1 = 3 (1 + 3CB1 / Cs), CB
1 / Cs >> 1, CB1 / Cc >> 1, so 2CB1 /
Cc = 9CB1 / Cs and Cc = Cs / 18. Therefore, the coupling capacitance between bit lines is about 1/18 of the cell capacitance.
Should be attached.

Next, the control circuit 6 sets the sense amplifier 2 activation signal SA2 to a high active level to operate the sense amplifier SA12. The control circuit sets the sense amplifier 2 activation signal SA2 to the active level after the potentials of the bit lines A1 and A2 are stabilized. For this purpose, it is possible to control the sense amplifier 2 activation signal SA2 to an active level after a certain time elapses from the time when the sense amplifier 1 activation signal SA1 is changed to an active level using a means such as a timer and a delay circuit. Good.

As a result, the sense amplifier SA12 has {(1/2) Vcc + ΔV} of the bit line B2 and {(1/2) Vcc + ΔV-ΔV} = (1/2) of the bit line B1.
Since the potential of the bit line B1 is smaller than that of Vcc, the potential of the bit line B1 is set to 0 and the potential of the bit line B2 is set to Vcc.

After that, the CAS signal becomes low active level, and the column address buffer 8 outputs the latched column address to the column decoder 4. The column decoder 4 decodes the column address when the SS2 signal becomes the high active level, and the bit line pair (BL) among the bit line selection lines CSL is decoded.
1, BLB1) is set to a high active level. As a result, the n-type MOS transistor T2 connected to the data lines D1 and D2 operates and outputs the data on the bit line pair (BL1, BLB1) to the data output buffer 10. At this time, the data lines D2 and D1 are
(Vcc, 0), that is, the information of (1,0) is output.

The data output buffer 10 keeps the output enable signal OE at the low active level while the output enable signal OE is at the low active level.
Data is output from the terminal 12 to an external device. Also, CA
In response to the change of the S signal to the high inactive level,
The control circuit 6 sets both the sense amplifier 1 activation signal SA1 and the sense amplifier 2 activation signal SA2 to the low inactive level, and deactivates the sense amplifiers SA11 and SA12.

Next, the control circuit 6 controls the gate selection signal line T
The area 1 and the area 2 are electrically connected to each other by setting G to an active level. That is, the bit line A1 and the bit line B1 are electrically connected, and the bit line A2 and the bit line B2 are electrically connected. As a result, the stray capacitances CS1 and CS2 are
The electric charge stored in the stray capacitances CS1 and CS
The potentials of 2 become equal. Since the capacitance ratio of the stray capacitances CS1 and CS2 is 2: 1, if the respective capacitances are 2C and 1C, the potential Va at this time is represented by the following formula.

Va = {2C × Vcc + 1C × 0} ÷ {2C + 1C} = (2/3) Vcc That is, the information stored in the cell 1 before the read operation is obtained.

Thereafter, the control circuit 6 sets the row decoder activation signal SS1 to the row inactive level to deactivate the row decoder 5, writes the information of (2/3) Vcc to the cell 1 and inactivates the word line WL1. Level.

After that, the control circuit 6 precharges the bit line pair.

This completes the data read cycle from the memory cell.

In the above description, the cell 1 has been described, but it goes without saying that data can be read from other cells by the same operation.

In the above example, the information of the memory cell is described as (2/3) Vcc, but 0 (0
V, that is, the ground level. ), (1 /
3) The same operation is performed in the case of Vcc and Vcc. This will be briefly described below.

[When Information of Cell 1 is (1/3) Vcc] When the information of the cell is read to the bit line BL1, the potential of the bit line BL1 becomes {(1/2) Vcc-ΔV}.

When the sense amplifier SA11 is activated, the bit line A1 becomes 0, and the bit line A2.
Becomes Vcc. Therefore, in the region 2 that is not electrically connected to the region 1, the coupling capacitor CC
Therefore, the bit line B1 becomes {(1/2) Vcc-ΔV + Δ
V} = (1/2) Vcc, and the bit line B2 is {(1
/ 2) Vcc-ΔV}. Therefore, after that, the sense amplifier SA12 operates so that the bit line B1 becomes Vc.
c, and the bit line B2 becomes 0. Therefore, at this time, (0, Vcc), that is, (0, 1) information is output to the data lines D1 and D2 connected to the bit line BL1.

The potential Va of the bit line BL1 when the regions 1 and 2 are electrically connected is: Va = {2C × 0 + 1C × Vcc} ÷ {2C + 1C} = (1/3) Vcc 1 can store the information before reading again.

[When Information of Cell 1 is 0] When the information of the cell is read to the bit line BL1, the potential of the bit line BL1 becomes {(1/2) Vcc-3ΔV}.

By the sense amplifier SA11, the bit line A
1 becomes 0, and the bit line A2 becomes Vcc. Therefore,
In the area 2 which is not electrically connected to the area 1,
The bit line B1 is {(1/2) Vcc-3ΔV + ΔV} =
{(1/2) Vcc-2ΔV}, and the bit line B2 becomes {(1/2) Vcc-ΔV}. So after this,
The bit line B1 is activated by the operation of the sense amplifier SA12.
Becomes 0, and the bit line B2 becomes Vcc. Therefore, at this time, the data line D1, which is connected to the bit line BL1,
Information (0, 0) is output to D2.

The potential Va of the bit line BL1 when the region 1 and the region 2 are electrically connected is Va = {2C × 0 + 1C × 0} ÷ {2C + 1C} = 0. Information can be stored again.

[When Information of Cell 1 is Vcc] When the information of the cell is read to the bit line BL, the potential of the bit line BL becomes {(1/2) Vcc + 3ΔV}.

By the sense amplifier SA11, the bit line A
1 becomes Vcc, and the bit line A2 becomes 0. Therefore,
In the area 2 which is not electrically connected to the area 1,
Bit line B1 is {(1/2) Vcc + 3ΔV−ΔV} =
It becomes {(1/2) Vcc + 2ΔV}, and the bit line B2 becomes {(1/2) Vcc + ΔV}.

Therefore, after that, the sense amplifier SA12 operates so that the bit line B1 becomes Vcc and the bit line B2 becomes 0. Therefore, at this time, the data lines D1 and D2 connected to the bit line BL1 have (Vcc, V
cc) That is, the information of (1, 1) is output.

The potential Va of the bit line BL1 when the regions 1 and 2 are electrically connected is Va = {2C × Vcc + 1C × Vcc} ÷ {2C + 1C} = Vcc Information can be stored again.

As described above, in the present embodiment,
If the data on the data line D1 is MSB and the data on the data line D2 is LSB, (D1, D2) = (0, 0), (0 ,
Information of 1), (1, 0), and (1, 1) will be read, respectively. That is, when outputting data, the information of the data line can be output as it is. Therefore, unlike the conventional example, it is not necessary to convert data from 3 bits to 2 bits when outputting data.

The above operation can be more easily understood from the potential change diagram of the bit line A1 and the bit line A2 in FIG.

Next, the case of writing data will be described. Here, in order to simplify the explanation, it is assumed that data is written in the cell 1 in FIG. Also,
Information on (2/3) Vcc is stored in the cell 1.

When the RAS signal goes low active level, the row address buffer 7 and the column address buffer 8 latch the address information input to the address input terminal 11. The row address buffer 7 immediately outputs the latched row address to the row decoder 5. At this time, the RAS signal becomes the low active level, so that the control circuit 6 stops the precharge operation of the bit line pair.

Since the control circuit 6 sets the row decoder activation signal SS1 to the high active level at the same time that the RAS signal becomes the active level, the row decoder 5 decodes the row address latched by the row address buffer 7. As a result, in the multi-valued memory cell array 1, the word line WL1 becomes the high active level, and the cell 1 is electrically connected to the bit line BL1.

The control circuit 6 controls the write enable signal WE.
Goes to the low inactive level, the gate select line T
G is set to low inactive level and transistor T
Area 1 and area 2 are electrically separated from each other.
Therefore, the bit line BL1 is the bit line A1 and the bit line B1.
The bit line BLB1 is divided into the bit line A2 and the bit line B2.

When the write enable signal WE is at the low active level, the data input buffer 9 latches the information on the data terminal 12 input from the external device.
Then, the latched information is immediately output to the data lines D1 and D2.

The column address buffer 8 outputs the latched column address to the column decoder 4 when the CAS signal becomes low active level. The column decoder 4 is activated when the CAS signal becomes low active level, decodes the column address, and selects the bit line pair (BL) among the bit line selection lines CSL.
1, CBL1 corresponding to BLB1) is set to a high active level. As a result, the transistor T2 connected to the data lines D1 and D2 operates, and the information on the data lines, that is, (D1, D2) = (1,0), is transferred to the bit lines B1 and A.
each of the above is incorporated.

Next, the control circuit 6 sets the sense amplifier 1 activation signal SA1 to the active level to operate the sense amplifier SA11.

Then, like the read operation, the control circuit 6 sets the sense amplifier 2 activation signal SA2 to the active level after a fixed time to operate the sense amplifier SA12.

The control circuit 6 causes the sense amplifier activating signal SA1, when the CAS signal becomes inactive level,
SA2 is made inactive, and sense amplifier SA11,
SA12 is set to non-operation.

After that, the RAS signal becomes inactive level, the gate selection line TG becomes active level, and the transistor T1 operates to electrically connect the region 1 and the region 2. Therefore, the potential Va of the bit line BL1 is expressed by the following equation, as in the read operation.

Va = {2C × Vcc + 1C × 0} ÷ {2C + 1C} = (2/3) Vcc After that, the control circuit 6 sets the row decoder activation signal SS1 to the row active level and deactivates the row decoder 5. As a result, the row decoder 5 sets the selected word line WL1 to the row inactive level, so that the data on the bit line BL1 is (2/3) Vcc.
After being stored in the capacitor of cell 1, cell 1 is electrically isolated from bit line BL1.

Then, the control circuit 6 performs precharge.

With the above, the data write cycle from the memory cell is completed.

In the above description, the cell 1 has been described, but it goes without saying that data can be written in other cells by the same operation.

In the above example, the information to be written in the memory cell is described as (2/3) Vcc.
The output to the data line of the data input buffer 9 is (D1,
D2) = (0,0), (D1, D2) = (0,1),
When (D1, D2) = (1, 1), 0 (0 V, that is, ground level), (1/3) Vcc, and Vcc are set in the cell 1 as in the above-described operation. Written.

Next, the case of the refresh operation will be described. Here, for simplification of description, it is assumed that the information on the word line WL1 in FIG. 1 is refreshed. In addition,
In the example shown in this figure, the refresh operation of the CAS BEFORE RAS system is shown.

When the CAS signal becomes low active level, the control circuit 6 outputs the address information RA of the word line WL1 to the row decoder 5 from the refresh address counter in the control circuit 6. In addition, the control circuit 6
Simultaneously sets the row decoder activation signal SS1 to the high active level, so that the row decoder 5 decodes the address information RA and sets the word line WL1 to the high active level. As a result, information on the cells 1 and 2 connected to the word line WL1 is output to the corresponding bit lines BL1 and BL2.

After that, the RAS signal becomes low active, so that the control circuit 6 makes the gate selection line TG low inactive. Therefore, the region 1 and the region 2 are electrically separated. At the same time, the control circuit 6 activates the sense amplifier 1 activation signal SA1 to activate the sense amplifier SA11, the sense amplifier SA21, and the like.

Next, the control circuit 6 activates the sense amplifiers SA12, SA22, etc. after a predetermined time, as in the read operation and the write operation.

Thereafter, when the RAS signal becomes the high inactive level, the control circuit 6 sets the sense amplifier activating signals SA1 and SA2 to the low inactive level, and deactivates the sense amplifier. Further, at this time, the control circuit 6 sets the gate selection line TG to the high active level, so that the regions 1 and 2 are electrically connected.

Finally, since the CAS signal becomes the high inactive level, the control circuit 6 sets the row decoder activation signal SS1 to the low inactive level. Since the row decoder 5 is inoperative, the word line WL1 is at the row inactive level. Therefore, the information of each memory cell on the word line WL1 is refreshed and stored again. Further, at this time, the control circuit 6 increments the content of the internal refresh address counter by 1 to obtain the information indicating the address address of the next word line WL2. Here, the content of the refresh counter is 1
Although it is assumed that the number increases one by one, it may decrease one by one.

This completes the refresh cycle.

As described above, according to the configurations shown in FIGS. 1 and 2, 2-bit information can be immediately input / output to / from the data line.
This eliminates the need for the conventional data output circuit for converting 3-bit information into 2-bit information. Further, since no dummy memory cell is required, further miniaturization of the device is promoted.

Next, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 4 is a circuit configuration of a memory cell section and a sense amplifier section showing a second embodiment of the present invention.
In the first embodiment, the multi-valued memory cell is a cell capable of storing 4-level information, but here it is possible to store m-bit (m is an integer of 2 or more) information. Shows the configuration of. Therefore, assuming that the power supply voltage is Vcc, 0, {1 / (m-1)} Vcc, {2
/ (M-1)} Vcc, ..., {(m-2) / (m-
1)}, Vcc, and a total of m pieces of information are stored. Further, as in the first embodiment, no dummy cell exists.

A plurality of bit line pairs (BL1, BLB1) to
A plurality of memory cells are connected to (BLn, BLBn) (n represents an integer) and a plurality of word lines WL. The memory cell has a structure including an n-type MOS transistor and a capacitor as shown in the cell 1 of FIG. 1 in the first embodiment. It should be noted that FIG. 4 shows a configuration corresponding to only the n-th bit line pair for simplification of description, and further illustrates a plurality of word lines and memory cells that are omitted.

Although the basic configuration is the same as that of the first embodiment shown in FIG. 1, there are regions 1 to m defined by the transistor T1. Also,
The capacitance ratio of the stray capacitances CS1, CS2, ..., CSm is m:
The ratio is m-1: to: 1. Further, the sense amplifiers SAn1, SAn2, ...
m sense amplifiers of nm are provided, and data lines D1 to Dm are provided corresponding to each region. In order to realize such a capacity ratio, the method of making the number of word lines in each region different and the number of word lines in each region are the same,
There is a method of actually providing a capacitor on the bit line.

In each area, a couple capacitor C
C is provided. This connection relationship is as shown in FIG.

Using the circuit shown in FIG. 4, a semiconductor memory device having the same structure as the semiconductor memory device shown in FIG. 2 in the first embodiment can be realized. The differences are as follows.

Control circuit 61 sequentially activates sense amplifier activation signals SA1, ..., SAm at regular time intervals.

The operation of each of the sense amplifiers SAn1, ..., SAnm is similar to that of the sense amplifiers SA11, SA12 in FIG.

The data output buffer 101 and the data input buffer 91 are different from the data output buffer 10 and the data input buffer 9 of FIG. 2 in that they are connected to the data lines D1 to Dm.

Except for the above differences, the semiconductor memory device of FIG. 7 operates similarly to the semiconductor memory device of FIG.

With this structure, in the present embodiment, multi-bit information of 2 bits or more can be immediately input / output to / from the data line. When such multi-bit information is realized by using multi-valued memory cells, the characteristics of multi-valued memory cells become remarkable, and when realizing a semiconductor memory device having a similar information amount by using conventional 1-bit cells. In comparison, the size of the device can be significantly reduced. Further, since no dummy memory cell is required, further miniaturization of the device is promoted.

Finally, a third embodiment of the present invention will be described.

FIG. 5 is a circuit configuration of a memory cell section and a sense amplifier section showing a third embodiment of the present invention.
Here, as in the case of the conventional example, a configuration having a 4-level memory cell is shown. Therefore, the power supply voltage is Vcc for each memory cell.
Then, 0, (1/3) Vcc, (2/3) Vcc,
Any one of four pieces of information of Vcc is stored.
In addition, the dummy cells that existed in the conventional example do not exist.

A plurality of bit line pairs (BL1, BLB1) to
A plurality of memory cells are connected to (BLn, BLBn) (n represents an integer) and a plurality of word lines WL. The memory cell has a structure including an n-type MOS transistor and a capacitor as shown in the cell 1 of FIG. 1 in the first embodiment.

In FIG. 5, the bit line pair (BLn, BLB
n) is provided with a total of two sense amplifiers SAn1 and SAn2. Each bit line pair is divided into a region 1 and a region 2 by an n-type MOS transistor T1 whose gate is connected to the gate selection line TG. The region 1 is further divided into a region 11 and a region 12 by the n-type MOS transistor T3 whose gate is connected to the gate selection line TGi. Similarly, the region 2 includes the gate selection line T
N-type MOS transistor T4 whose gate is connected to Gj
Is further divided into a region 21 and a region 22.

Therefore, the bit line BLn is connected to the bit line AB.
1, AA1, BB1, BA1 are separated into four, and the bit line BLBn is divided into bit lines AB2, AA2, BB2, BA.
It is separated into 4 of 2. The stray capacitance generated on the bit lines in the regions 11, 12, 21, and 22 has the same capacitance C in all regions.
SC. To achieve such a capacity ratio,
There are a method of making the number of word lines in each region the same, a method of providing a capacitor for a bit line and adjusting the same. In this figure, the word lines WL0 to WL255 are provided in the region 2, the word lines WL256 to WL511 are provided in the region 1, and at least the number of word lines in the regions 1 and 2 is the same.

A coupling capacitor CC is provided for each bit line pair. This connection relationship is as shown in FIG.

FIG. 6 is a device schematic diagram showing an example of a semiconductor memory device formed in one chip by using the circuit shown in FIG. The multi-valued memory cell array 111 in this figure corresponds to the circuit shown in FIG.

In this semiconductor memory device, the same reference numerals are given to the components that perform the same operations as those of the semiconductor memory device shown in FIG. 2 in the first embodiment. Therefore, a component different from that of FIG. 2, that is, the address discrimination circuit 131.
This will be described below.

The address discrimination circuit 131 receives the refresh address information RA from the row address buffer 7 or the control circuit 6 and determines whether the address information corresponds to either the area 1 or the area 2 word line. When the received address information is the word line in the area 1, the gate selection line TGj is set to the low inactive level and the areas 21 and 22 are electrically connected during each of the data read, data write, and refresh cycles. The gate select line TGi is separated, and the regions 11 and 12 are electrically connected to each other at a high active level. When the received address information is the word line of the area 2, the gate selection line TGj is set to the high active level and the areas 21 and 22 are electrically connected during each cycle of data read, data write, and refresh. Then
The region 11 and the region 12 are electrically separated by setting the gate selection line TGi to the low inactive level.

As a result, when the region 22 and the region 21 are electrically separated, the regions separated by the gate selection line TG are the region 1 and the region 21, and the floating capacitance ratio of these regions is 2 :. It becomes 1. In addition, the areas 11 and 12
Are electrically separated, the regions separated by the gate selection line TG are the regions 2 and 12, and the ratio of the stray capacitances of these regions is 2: 1.

Therefore, the configuration other than the multi-valued memory cell array 111 and the address discrimination circuit 131 may be the same as the configuration of FIG. 2 shown in the first embodiment.

In the present embodiment, 2-bit information can be immediately output to the data line. This eliminates the need for the conventional data output circuit for converting 3-bit information into 2-bit information. Further, since no dummy memory cell is required, further miniaturization of the device is promoted. Further, it is not necessary to adjust the number of word lines provided in each region and adjust the ratio of the stray capacitance in each region, which is an advantage that the design is easy.

As described above, in the first, second and third embodiments, as long as it does not violate the basic concept of the present invention, among the constituent elements which operate in response to each signal, the constituent elements which are high active are It does not matter to make it low active, make low inactive high inactive, or vice versa. Similarly, the n-type MOS transistor may be a p-type.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a memory unit and a sense amplifier unit of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a semiconductor memory device implementing the first embodiment of the present invention.

FIG. 3 is a timing chart showing potential changes of bit lines A1 and A2 of the present invention.

FIG. 4 is a circuit diagram showing a memory section and a sense amplifier section of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a memory section and a sense amplifier section of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 6 is a block diagram of a semiconductor memory device that realizes a third embodiment of the present invention.

FIG. 7 is a circuit diagram showing a memory section and a sense amplifier section of a conventional semiconductor memory device.

FIG. 8 is a schematic diagram of the configuration of a conventional 1-bit cell.

FIG. 9 is a schematic configuration diagram of a 2-bit cell.

FIG. 10 is a schematic diagram of the configuration of another 2-bit cell.

FIG. 11 is a schematic configuration diagram for obtaining 2-bit information using a conventional 1-bit cell.

FIG. 12 is a schematic configuration diagram of a conventional 2-bit memory cell array semiconductor memory device.

[Explanation of symbols]

 1 Multilevel Memory Cell Array 2 Sense Amplifier 1 3 Sense Amplifier 2 4 Column Decoder 5 Row Decoder 7 Row Address Buffer 8 Column Address Buffer 9 Data Input Buffer 10 Data Output Buffer 11 Address Terminal 12 Data Terminal 111 Multilevel Memory Cell Array 131 Address Discrimination Circuit Two

Claims (9)

[Claims] 1. A conductive path is formed between a first conductive means connected to form a conductive path between a first wiring and a second wiring, and a third wiring and a fourth wiring. Second conductive means connected to form, a first capacitor having one end connected to the first wiring and the other end connected to the fourth wiring, and one end connected to the second wiring. A second capacitor connected to the third wiring, the other end connected to the third wiring, a first input end connected to the first wiring, and a second input end connected to the third wiring. , Comparing the potentials applied to the first and second input terminals according to the first signal, outputting the result to the first wiring, and outputting the inverted signal of the result to the third wiring. A first comparing means for outputting and a third input end connected to the second wiring, a fourth input end connected to the fourth wiring, a second Comparing the potentials applied to the third and fourth input terminals according to the signal of No. 3, outputting the result to the second wiring, and outputting an inverted signal of the result to the fourth wiring. 2. The semiconductor integrated circuit according to claim 2, wherein the first and second conductive means form the conductive path according to a third signal. 2. The semiconductor integrated circuit according to claim 1, wherein the first and second conductive means are first conductivity type MOS transistors which receive the third signal at their gates. 3. A third capacitor is further connected to each of the first and third wirings, and a fourth capacitor is further connected to each of the second and fourth wirings. 3. The semiconductor integrated circuit according to claim 2, wherein the capacitance of the second capacitor and the capacitance of the fourth capacitor are different. 4. A stray capacitance between the first wiring and the third wiring is a first capacitance, and a stray capacitance between the second wiring and a fourth wiring is a second capacitance, 3. The semiconductor integrated circuit according to claim 2, wherein the first capacitance and the second capacitance are different. 5. The semiconductor integrated circuit according to claim 1, wherein the second signal is applied after the first signal. 6. A plurality of multi-valued memory cells are connected to each of the first to fourth wirings.
6. The semiconductor integrated circuit according to any one of 5 to 6. 7. A multi-valued memory cell array, first and second sense amplifiers, and a control circuit, wherein the control circuit activates the first sense amplifier and then activates the second sense amplifier. A semiconductor device characterized in that a sense amplifier is activated to sense cell information of the multi-valued memory cell array. 8. A memory for storing N-bit data in one cell, wherein the sense of each bit is sequentially sensed from MSB to LSB, and the sense level of the lower bit is changed by using the sense result of the upper bit. Multi-valued memory. 9. The multi-valued DRAM according to claim 8, wherein the cell is a dynamic cell, and the means for changing the sense level of the lower bit is performed by coupling the capacitance between bit lines.