JPH09282882A - Detection circuit for transition of address - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a detection circuit by which the transition of an address signal is detected even when the address signal is inverted repeatedly at short time intervals by a method wherein the rise and the fall of the address signal are detected respectively by separate circuits. SOLUTION: In a rise detection circuit 30, a first-stage CMOS inverter 31 is constituted of a large-channel-width PMOSFET and of a small-channel-width NMOSFET, and a second-stage CMOS inverter 32 is constituted of a small- channel-width PMOSFET and of a large-channel-width NMOSFET. On the basis of the difference in a driving force between the FET's forming a pair, third-stage inverters 31 to 33 respond differently to the rise and the fall of an address signal ADR. Consequently, a circuit in which NMOSFET's 35, 36 are connected in series is set surely to continuity at the rise of the address signal ADR, and it sets an enable signal to 'L'. A fall detection circuit 40 responds to the fall of the address signal ADR via an inverter 44.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a ROM and a RAM.
Etc. to an address transition detection circuit for detecting a transition of an address signal in the memory.

[0002]

2. Description of the Related Art Asynchronous SRAM (Static Random Access)
In memory such as Memory), the switching operation of the transistor is prohibited during the period when the address signal is transiting,
There is a configuration in which unnecessary current consumption does not flow. FIG. 5 shows an example of the configuration of a conventional address transition detection circuit used for this type of memory.

In FIG. 5, 1 is an EXNOR circuit, and 11
˜13 are inverters, 2 is an N-channel MOSFET, and these constitute a portion corresponding to the 1-bit address signal ADR of the address data having a predetermined number of bits. Here, the EXNOR circuit 1 receives the address signal ADR and the signal A obtained by delaying and inverting the address signal ADR by the three-stage inverters 11 to 13. The source of the N-channel MOSFET 2 is grounded, and the output signal B of the EXNOR circuit 1 is input to the gate thereof. As for the other bits forming the address data, a circuit having the same structure as that shown in FIG. 5 is provided. The drains of the N-channel MOSFETs 2, 2, ... Of the circuit corresponding to each bit are pulled up to the power supply via the common resistor R. An enable signal EN obtained from a connection point between each drain of the N-channel MOSFETs 2, 2, ... And one end of the resistor R is used to control permission / prohibition of a switching operation of a transistor in the memory. That is, when the enable signal EN is at H level, the switching operation of the transistors in the memory is permitted,
If the level and the switching operation are prohibited.

FIG. 6 is a waveform diagram showing the operation of this address transition detection circuit. As shown in this figure, when level inversion occurs in the address signal ADR, the address signal AD
Until the level inversion of R appears in the output signal A of the inverter 13, the respective levels of the two input signals ADR and A to the EXNOR circuit 1 are in agreement. Therefore, during this period, a positive pulse is output from the EXNOR circuit 1 as the signal B.
Is output as an N-channel MOSFET2
Is turned on. As a result, the enable signal EN becomes L
The level is set, and control is performed to prohibit the switching operation of the transistors in the memory. The same applies when there is a transition of the address signal corresponding to another bit.

[0005]

The conventional address transition detection circuit described above delays the address signal ADR and compares the delayed address signal with the current address signal ADR to determine the level of the address signal ADR. However, there is a problem in that the transition cannot be reliably detected depending on the mode of the temporal change of the address signal ADR.

FIG. 7 shows an example thereof. First,
The address signal ADR shown in FIG.
The rising and falling edges are alternately repeated at time intervals substantially equal to the delay times 1 to 13. When this address signal ADR is delayed and inverted by the inverters 11 to 13, the signal A shown in FIG. 7B is output from the inverter 13. As shown in these figures,
When the level of the address signal ADR is repeatedly inverted at a time interval substantially equal to the delay time of the inverters 11 to 13, during that time, the signal A of the inverter 13 and the address signal ADR are
When one rises, the other will fall in reverse, and the levels of both will not match.
For this reason, even though the address signal ADR changes, no pulse is supplied to the gate of the N-channel MOSFET 2 and the enable signal EN does not fall.

The present invention has been made in view of the above-mentioned circumstances, and provides an address transition detection circuit capable of stably detecting the transition of an address signal regardless of the mode of the temporal change of the address signal. It is intended to be provided.

[0008]

The present invention comprises a rising edge detection circuit for detecting a rising edge of an address signal, and a falling edge detection circuit for detecting a falling edge of the address signal. Another feature of the present invention is an address transition detection circuit, which outputs a signal indicating a transition of an address signal when a falling edge is detected.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments will be described to make the present invention easier to understand. Such an embodiment shows one aspect of the present invention, and does not limit the present invention, and can be arbitrarily changed within the scope of the present invention.

FIG. 1 is a circuit diagram showing the configuration of an address transition detection circuit according to an embodiment of the present invention. This figure is
The structure of a portion corresponding to a 1-bit address signal ADR among the respective bits forming the address data is shown.
For other bits, circuits similar to those shown in the drawing are provided. The output terminals 20, 20 ... Of the circuit corresponding to each bit are pulled up to the power source via the common resistor R, as in the configuration shown in FIG. The enable signal EN obtained from the common connection point between the output terminals 10, 10 ... And the resistor R is used as a signal indicating address transition.

The circuit shown in FIG. 1 comprises a rise detection circuit 30 for detecting the rise of the address signal ADR and a fall detection circuit 40 for detecting the fall of the address signal ADR, which are connected in parallel.

First, the rising detection circuit 30 includes three-stage inverters 31 to 33, and N-channel MOSFETs 35 and 36 connected in series between the output terminal 20 and the ground line.
It is composed of Here, N channel MOSF
The address signal ADR is directly input to the gate of the ET 36. On the other hand, a signal D obtained by delaying and inverting the address signal ADR by the inverters 31 to 33 is input to the gate of the N-channel MOSFET 35.

All of these three-stage inverters are CMs.
Although it is an OS inverter, the first-stage inverter 31
2A is configured by a P-channel MOSFET 31P having a large channel width WP and an N-channel MOSFET 31N having a small channel width WN, as shown in FIG. In addition, as shown in FIG. 2B, the second-stage inverter 32 is a P-channel MOS with a small channel width WP.
FET 32P and N channel MO with large channel width WN
It is composed of an SFET 32N.

FIG. 3 shows each of these inverters 31 and 3
FIG. 4 is a waveform diagram showing the operation of FIG. 2, and FIGS.
Shows respective output signal waveforms obtained from the inverters 31 and 32 when the input signal shown in FIG.

As shown in FIG. 3B, the inverter 31
The output signal of 1 rises immediately in response to the fall of the input signal, but slowly falls with respect to the rise of the input signal. This is because the driving force of the P-channel MOSFET 31P of the inverter 31 is large,
This is because the driving force of the N-channel MOSFET 31N is small. Therefore, when a positive pulse with a short pulse width is input, the inverter 31 causes the input signal to fall when the output signal starts to fall in response to the rising edge of the input signal. Will stand up before it completely falls.

On the other hand, the inverter 32 is a P channel MO.
The driving force of the SFET 32P is small and the N-channel MOSF
The driving force of ET32N is large. Therefore, as shown in FIG. 3C, the output signal of the inverter 32 immediately falls in response to the rising of the input signal, but rises slowly with respect to the falling of the input signal.

Therefore, the three-stage inverters 31 to 33 are
In response to the fall of the address signal ADR, the gate voltage of the N-channel MOSFET 35 is raised quickly, but with respect to the rise of the address signal ADR,
It cannot respond immediately and will not respond at all when a positive pulse with a short pulse width is given as the address signal ADR.

N-channel MOSFETs 35 and 36
One is directly driven by the address signal ADR, while the other is the three-stage inverters 31 to 31 described above.
It is driven by a signal D obtained from 33. Therefore,
The series circuit composed of these N-channel MOSFETs 35 and 36 will behave as follows.

A. Behavior at rising edge of address signal ADR N-channel MO due to rising edge of address signal ADR
The SFET 36 is immediately turned on. On the other hand, since the input signal D to the gate of the N-channel MOSFET 35 falls or does not fall much later than this, the N-channel MOSFET 35 is turned on for at least a fixed time after the rise of the address signal ADR.
Maintain state. Therefore, the N-channel MOSFET 35
When the address signal ADR rises, the series circuit composed of 36 and 36 maintains the ON state as a whole for at least a fixed time.

B. Behavior at falling edge of address signal ADR N-channel MO due to falling edge of address signal ADR
The SFET 36 is immediately turned off. Therefore, the series circuit composed of the N-channel MOSFETs 35 and 36 immediately becomes OF when the address signal ADR falls.
The state becomes the F state.

Next, the fall detection circuit 40 has three stages of inverters 41 to 41 similar to the rise detection circuit 30.
43 connected in series between the output terminal 20 and the ground wire
Channel MOSFETs 45 and 46,
Further, it has an inverter 44 which supplies a signal E obtained by inverting the address signal ADR to these.

P which constitutes the inverters 41 and 42,
The relationship of the channel width of the MOSFET of each N channel is the same as that of the above-described inverters 31 and 32 (see FIGS. 2A and 2B). That is, the inverters 41 to 4
Similarly to the inverters 31 to 33, 3 is an N-channel MOSFET that responds quickly to the fall of the input signal.
Although the input signal F for 45 is increased, it does not immediately respond to the rising edge of the input signal.

The address signal AD is applied to the gates of the first-stage inverter 41 and the N-channel MOSFET 46.
A signal E obtained by inverting R by the inverter 44 is supplied. Therefore, when the address signal ADR falls, the series circuit composed of the N-channel MOSFETs 45 and 46 maintains the ON state as a whole for at least a fixed time, and immediately after the address signal ADR rises, the OF signal is turned off.
The state becomes the F state.

According to the above configuration, the address signal ADR
Rising edge and falling edge of rising edge detection circuit 3
Since they are independently detected by the 0 and the fall detection circuit 40, the transition can be reliably detected even in a situation where the level of the address signal ADR is inverted at an extremely short time interval. FIG. 4 shows an example of the operation.

First, assume that the level of the address signal ADR is repeatedly inverted at short time intervals as shown in FIG. At this time, since the inverters 31 to 33 do not respond to the positive pulse having the short pulse width, the waveform of the output signal D becomes as shown in FIG. 4 (b). Therefore, FIG.
In each hatched period, the address signal ADR and the signal D both become H level, and the series circuit composed of the N-channel MOSFETs 35 and 36 is turned on.
State.

On the other hand, in the fall detection circuit 40, the signal E obtained by inverting the address signal ADR is the inverters 41-4.
3 (see FIG. 4 (c)), the inverters 41 to 43 do not respond to a positive pulse having a short pulse width, and therefore the waveform of the output signal F thereof is that shown in FIG. 4 (d). Becomes Therefore, in each hatched period in FIG. 4D, the signals E and F are both at the H level, and the series circuit including the N-channel MOSFETs 45 and 46 is in the ON state.

As described above, when the address signal ADR rises, the N-channel MOSFETs 35 and 36 are always turned on, and when the address signal ADR falls, the N-channel MOSFET 4 is always generated.
Since 5 and 46 are turned on, the address signal AD
Whenever the transition of R occurs, the enable signal EN becomes L level (see FIG. 4 (e)).

The embodiment described above is merely an example of one aspect of the present invention, and the scope of application of the present invention is not limited to this. Various modifications are possible without departing from the technical idea of the present invention. Can be modified. For example, in the above-described embodiment, by appropriately setting the ratio of the channel widths WP and WN of the MOSFETs of the P and N channels, it is possible to quickly respond to one of rising and falling of the input signal and to respond to the other. A slow responding inverter was constructed. However, this type of inverter
This configuration may be adopted because it can be configured by appropriately setting the ratio of the channel lengths LP and LN of the MOSFETs of P and N channels (FIGS. 2A and 2B).
reference).

[0029]

As described above, according to the present invention, the rising circuit for detecting the rising edge of the address signal and the falling circuit for detecting the falling edge of the address signal are provided. Since the signal indicating the transition of the address signal is output by outputting the detection of the rising edge or the falling edge, the transition of the address signal can be detected stably regardless of the mode of the temporal change of the address signal. There is an effect that can be.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an address transition detection circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of inverters 31 and 32 in the same embodiment.

FIG. 3 is a waveform diagram showing operations of the inverters 31 and 32.

FIG. 4 is a waveform diagram showing an operation of the same embodiment.

FIG. 5 is a circuit diagram showing a configuration of a conventional address transition detection circuit.

FIG. 6 is a waveform diagram showing an operation of the address transition detection circuit.

FIG. 7 is a waveform chart showing an operation of the address transition detection circuit.

[Explanation of symbols]

30 ... Rise detection circuit, 40 ... Fall detection circuit.

Claims (1)

[Claims] 1. A rise detection circuit for detecting a rise of an address signal, and a fall detection circuit for detecting a fall of the address signal, wherein the rise or fall of the address signal is detected. The address transition detection circuit is characterized by outputting a signal indicating a transition of the address signal.