JPH09274571A - Interruption delay device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an interruption delay device which is provided between a circuit for generating an interruption signal to a computer and the computer, enables synchronous communication between computers and prevents the performance of foreground program execution from being lowered. SOLUTION: An interruption delay circuit 2 is provided with fixed time delay means 21-24 for inputting 2a the interruption signal generated from an interruption generation circuit 3 and outputting an enable signal inputted from an enable input terminal 2c to an output terminal 2b while delaying the valid start time of the inputted interruption signal as long as a number (n) of internal clock signals based on the previously set number (n) of steps of a shift register 21 when that enable signal is a negative logic level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt delay device for inputting an interrupt signal generated to a computer and delaying it for a predetermined time or an arbitrary time and outputting it.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional interrupt generation circuit and CPU.
It is a diagram showing a connection configuration with, as shown in the figure,
In the conventional computer system, the interrupt generation circuit 3
The interrupt request signal output from the CPU is directly input to the CPU 1. FIG. 5 is a diagram showing a configuration when an inter-computer communication system is configured using the circuit of FIG.
The figure shows a system in which the CPU 1A and the CPU 1B communicate with each other.

CPUs 1A and 1B of the system shown in FIG.
Has their own communication devices 5A and 5B and interrupt generation devices 3A and 3B, respectively. The interrupt generating device generates an interrupt signal to the CPU according to a change in the state of the communication device. In the system as shown in FIG. 5, the communication program is
When the background operation is performed separately from the application program, the program is operated by the interrupt operation from the interrupt generation device.

For example, when the CPU 1A receives data from the CPU 1B, the interrupt generator 3A generates an interrupt signal when the communication device 5A receives the data, and C
PU1A becomes an interrupt operation, and the interrupt program of CPU1A operates. This interrupt program stores the data from the communication device in the memory space of the CPU 1A.
On the other hand, the communication device 5B notifies the CPU 1B of the completion of the transmission to the CPU 1A through the interrupt generating device 3B. At this time, the CPU 1B becomes an interrupt operation and C
The interrupt program on PU1B operates. This interrupt program sends the data to be sent to CPU1A next to the CPU.
Transfer from the memory space of 1B to the communication device 5B.

[0005]

However, when a program that changes the state only by this interrupt signal is created by using the conventional circuit as shown in FIG. 4, in order to synchronize with the communication target. There is a drawback that the load of the required CPU becomes large. For example, when the operation of the interrupt program of the CPU 1A in FIG. 5 is slow, it is necessary to delay the operation start of the interrupt program of the CPU 1B.
That is, in such a case, unless the operation start of the interrupt program of the CPU 1B is delayed, the CPU 1A cannot receive the data when the CPU 1B transmits the next data, and thus the CPU 1A cannot receive the data. In order to avoid such a situation, an operation to delay the operation start of the interrupt program of the CPU 1B is required.

In the conventional method, when the interrupt program of the CPU 1B is delayed, a loop program is inserted at a place where the interrupt program is entered, and the start of the interrupt program is apparently delayed. When this method is adopted, the loop program excludes the execution of the foreground program (application program that is not driven by an interrupt), which causes a problem that the execution time of the foreground program is reduced and the performance is degraded. Further, it is possible to use another system interrupt such as a timer interrupt in order to solve this problem. However, the use of a separate system of interrupts has the drawback of complicating circuits and programs, and the performance of the foreground is only slightly improved.

[0007]

An interrupt delay device according to the present invention is an interrupt delay device having a hardware structure provided between a circuit for generating an interrupt signal to a computer and the computer. An internal clock signal of which the valid start time of this interrupt signal is n
Fixed time delay means for delaying and outputting by the number, or variable time delay for delaying and outputting by m number of internal clock signals whose effective start time of the interrupt signal is m arbitrarily set by the program It is equipped with means. As a result, when the computer is used in a communication system provided on the transmitting side and the receiving side, it is possible to perform synchronous communication between the computers and eliminate the need to secure a delay time by looping a program as in the conventional case. The performance of the foreground program execution can be improved.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. FIG. 1 is a diagram showing the configuration of an interrupt delay device according to the first embodiment of the present invention. In FIG. 1, 1 is C
UP and 2 are interrupt delay circuits according to the first embodiment,
n-bit shift register 21, OR gates 22 and 23
And an AND gate 24. Reference numeral 3 is an interrupt generation circuit. FIG. 2 is a waveform diagram for explaining the operation of FIG. 1, in which (a) an input / output signal waveform of the n-bit shift register 21 and (b) of FIG. 2 are input / output signals of the interrupt delay circuit 2. Waveforms are shown respectively.

The operation of the circuit of FIG. 1 will be described with reference to FIG. The interrupt signal circuit 3 supplies an interrupt signal of negative logic as shown in the input signal waveform of FIG. 2A via the input terminal 2a of the interrupt delay circuit 2 to the n-bit shift register 21 in the circuit 2. And OR gates 22 and 23. The n-bit shift register 21 outputs the input signal n as shown in the output signal waveform of FIG.
The output is delayed by the clock, and this output signal is supplied to one of the inputs of the OR gate 22. This OR gate 22
Since the interrupt signal from the input end 2a is directly supplied to the other input of, the output signal of the OR gate 22 is
It falls with a delay of n bits from the falling edge of the input interrupt signal, and rises with a delay of only the time required for the gate operation from the rising edge of the interrupt signal. The output signal of the OR gate 22 is supplied to one of the inputs of the AND gate 24.

At the enable input terminal 2c of FIG. 1, the delay operation of the interrupt delay circuit 2 is enabled or disabled, that is, the interrupt signal supplied to the input terminal 2a is delayed by n clock signals. An enable signal is externally supplied to determine whether the output is to be performed or to be output without any delay. This enable signal is shown in FIG.
(B), the delay operation is valid at the negative logic level and the delay operation is invalid at the positive logic level. That is, the enable signal is supplied to the signal inverting input terminal of the OR gate 23 via the enable input terminal 2c, and the interrupt signal is supplied to the signal non-inverting input terminal of the gate 23 via the input terminal 2a. The output signal of the logical sum gate 23 is supplied to one input of the logical product gate 24, and the output signal of the logical sum gate 22 is supplied to the other input of the gate 24.

Therefore, as shown in FIG. 2B, when the enable signal is at the negative logic level, the positive logic level signal obtained by inverting the enable signal from the output terminal of the OR gate 23 is input to one of the inputs of the AND gate 24. To be supplied to
Only the falling edge of the interrupt signal supplied from the OR gate 22 to the other input of the AND gate 24 is delayed by n bits, and the rising edge is not delayed so much, and the signal is output from the AND gate 24 to the output terminal 2b. . When the enable signal is at the positive logic level, the interrupt signal from the input terminal 2a is directly supplied from the output end of the logical sum gate 23 to one input of the logical product gate 24, and the logical sum gate 22 outputs the same signal as above. Is supplied to the other input of the AND gate 24, so that the interrupt signal is output from the AND gate 24 from the input terminal 2a to the output terminal 2b almost unchanged (delayed only by the time required for the gate operation).

According to the first embodiment, the delay time can be determined in advance by the clock signal for n clocks, and the occurrence of the interrupt can be delayed by n clocks. By delaying this interrupt, when used in the communication system as shown in FIG. 5, it is not necessary to loop the program to secure time, and the performance of the foreground program execution can be improved.

Embodiment 2 FIG. FIG. 3 is a diagram showing the configuration of the interrupt delay device according to the second embodiment of the present invention. In FIG. 3, 1 and 3 are the same as those in FIG. A programmable interrupt delay circuit 4 according to the second embodiment includes a register 41, a selector 42, n D flip-flops (hereinafter referred to as D-FF) 43, and an OR gate 44. In FIG. 3, a register input signal, which is programmable data defining the delay time of the programmable interrupt delay circuit 4, is externally supplied to the register 41 via the register input terminal 4c. The selector 42, based on the data input to the register 41, n D-F
One of the output signals of F43 is selected and used as the output signal of the selector 42. Therefore, by changing the data of the input signal input to the register 41, n D
It means that the number n of stages of the shift register constituted by the FF 43 is changed to an arbitrary number.

The operation of FIG. 3 will be described. The interrupt generation circuit 3 has an input terminal 4a of the programmable interrupt delay circuit 4.
An interrupt signal of negative logic is supplied to the n D-FFs 43 and the OR gate 44 via. The output of each of the n FFs is input to the selector 42, and the selector 42
Is n D based on the data input to the register 41.
The output signal of any one of the FF43 is selected, output from the output terminal of the selector 42, and supplied to one of the inputs of the OR gate 44. Since the interrupt signal is directly supplied to the other input of the logical sum gate 44 from the input terminal 4a, the output side of the gate 44 is delayed by the specified number of clocks from the falling point of the input interrupt signal. A signal that rises after being delayed by the time required for the gate operation from the time of rising of the interrupt signal and rising of the interrupt signal is output and supplied to the output terminal 4b.

According to the second embodiment, it is possible to delay the occurrence of the interrupt by the designated number of clocks. As a result of making the delay time variable by the program, the performance of the foreground program execution can be further improved as compared with the first embodiment. The present invention can be used to synchronize communicating computers in an interrupt driven communication system. The second embodiment is particularly effective when the processing speed of the other computer to be transmitted cannot be specified. That is, it is possible to communicate several times, measure the frequency of communication errors, and determine the optimum delay time based on the result.

[0016]

As described above, according to the present invention, in the interrupt delay device having a hardware configuration provided between the circuit for generating an interrupt signal to the computer and the computer, the generated interrupt signal Fixed delay means for delaying the valid start time of the interrupt signal by n internal clock signals whose preset number is n, or outputting the valid start time of the interrupt signal by a program. Since the variable time delay means for delaying and outputting by m the number of the internal clock signals whose number is arbitrarily set as m is provided, the above computer is used for the communication system provided on the transmitting side and the receiving side. In this case, synchronous communication between the above-mentioned computers is made possible, and a program is looped as in the conventional case to secure a delay time. It is no longer required, there is an effect of improving the performance of the foreground program execution.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an interrupt delay device according to a first embodiment of the present invention.

FIG. 2 is a waveform chart for explaining the operation of FIG.

FIG. 3 is a diagram showing a configuration of an interrupt delay device according to a second embodiment of the present invention.

FIG. 4 is a diagram showing a connection configuration between a conventional interrupt generation circuit and a CPU.

5 is a diagram showing the configuration of the circuit of FIG. 4 during inter-computer communication.

[Explanation of symbols]

 1 CPU 2 Interrupt delay circuit 3 Interrupt generation circuit 4 Programmable interrupt delay circuit 21 n-bit shift register 22,23 Logical OR gate 24 Logical AND gate 41 Register 42 selector 43 n D-FF 44 Logical OR gate

Claims (1)

[Claims] 1. An interrupt delay device having a hardware configuration, which is provided between a circuit for generating an interrupt signal to a computer and the computer, inputs the generated interrupt signal, and activates the interrupt signal. Fixed time delay means for delaying and outputting by n number of internal clock signals whose preset number is n, or m is a number arbitrarily set by the program for the effective start time of the interrupt signal. Internal clock signal m
An interrupt delay device comprising variable time delay means for delaying and outputting the number of pieces.