JPH09270950A - Image input device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the occurrence of a flicker by outputting only the video of one field from a video signal and discarding other data in a (vertical frequency × flicker period of camera) field. SOLUTION: This image input device is provided with a detection means (signal processing circuit 14) for detecting the presence or absence of the flicker and obtaining the generation period of the flicker, a control means 15, a storage means and external I/F 17 outputting video data to PC. The control means 15 realized by a microcomputer obtains the charge quantity of the plural images obtained from an image pickup means in the generation period of the flicker and selects one picture. The storage means is provided with an image memory 16 for storing the image selected by the control means 15, and it is controlled by a memory control circuit 18.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flicker countermeasure for reducing an image flicker under fluorescent lamp illumination in an image input device using a solid-state image pickup device.

[0002]

2. Description of the Related Art An image taken under fluorescent lighting is flickered and very unsightly. In this case, the power supply frequency is fp (Hz) and the vertical frequency of the camera is fv (H
z), the flicker period T becomes the least common multiple T [s] of 1 / (2fp) and 1 / fv, which causes flicker in (T × fv) field units. For example, when the power supply frequency is 50 Hz and the vertical scanning frequency of the camera is 60 Hz, the flicker frequency is 0.05 [s].
Therefore, flicker occurs in a 3-field cycle.

As a conventional flicker countermeasure for a television camera, as described in Japanese Patent Publication No. 6-20276, paying attention to the periodicity of the flicker, the gain of each field causing the flicker is periodically changed. A method and a method of controlling the timing of the electronic shutter have been proposed as described in Japanese Patent Laid-Open No. 6-209427. Further, a method of adjusting the shutter speed to the blinking cycle of the fluorescent lamp (for example, in an area where the power supply frequency is 50 Hz, the fluorescent lamp blinks at 100 Hz, the electronic shutter is fixed to 1/100 s) is often used.

By the way, the television camera as described above is
When connecting to an external device such as a personal computer (hereinafter, referred to as “PC”), the CPU (Central Processing Unit) of the external device supplies the processing power or the interface power to the TV camera, for example. It is impossible to capture a moving image of 60 fields / second with sufficient resolution. Therefore, a buffer memory is provided at the output of the image sensor to enable transmission by matching the processing speed on the PC side.

[0005]

By the way, when a television camera is connected to a PC or the like, it is difficult to transmit all fields as shown in the conventional example. In addition, since the conventional television camera is intended for displaying on a TV, the NTSC (National Television System Committ)
e), the signal based on the standard such as PAL (Phase Alternative by Line) method was output, but when connecting to a PC or the like, since the PC or the like has an image memory, necessary pixels In many cases, it is sufficient to transfer the numbers at a certain frame rate, and there are few restrictions on the blanking period and the horizontal scanning frequency. Therefore, it is an object to easily perform flickerless in such a case.

[0006]

In order to solve the above-mentioned problems, an image input device according to the present invention is an image input device for transmitting an image picked up by an image pickup means to an external device as a digital signal. In the above, a detection unit that detects the presence or absence of flicker and obtains the flicker occurrence period, and a control unit that obtains the charge amounts of a plurality of images obtained from the imaging unit within the flicker occurrence period and selects one image. The storage unit stores an image selected by the control unit, and an output unit that outputs the image stored in the storage unit to an external device at each flicker generation cycle.

According to a second aspect of the invention, in addition to the first aspect of the invention, the control means selects an image having the largest charge amount within the flicker generation cycle.

Further, according to a third aspect of the present invention, in the image input device for transmitting the image picked up by the image pickup means to the external device as a digital signal, the power source frequency detecting means is provided, and the above-mentioned power source frequency is detected according to the detected power source frequency. The vertical scanning frequency of the image pickup means is changed to prevent the occurrence of flicker.

The invention according to claim 4 is based on claim 3
In addition to the invention described in (1) above, a drive unit for the image pickup means capable of selecting a vertical scanning frequency, a detection means for detecting the presence or absence of flicker and obtaining the flicker generation cycle, and the flicker is detected by the detection means. A control means for changing the vertical scanning frequency of the driving device, and a storage means for storing the image output by the imaging means in accordance with the vertical scanning frequency,
And an output unit for outputting the contents of the storage unit to an external device at a constant cycle.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the image input apparatus of the present invention will be described below.

[First Embodiment] In the first embodiment of the image input apparatus of the present invention, the vertical frequency of the camera is fv (H
z), where T is the flicker period, (T × fv)
By outputting only the video of one field from the video signal of the field and discarding the data of other fields,
Make flicker invisible. Further, when the field data is discarded, the brightest field is left and only the video is output to obtain a good S / N image.

FIG. 1 is a block diagram of an image input device according to an embodiment of the present invention. In FIG. 1, the image input device includes a CCD (Charge Coupled Device) 10, a CCD drive circuit 11, a preprocessing circuit 12 for performing CDS (Correlated Double Sampling) and AGC (Auto Gain Control), and A.
DC (Analog Digital Converter) 13, signal processing circuit 1
4, a control means 15 realized by a microcomputer, an image memory 16 for storing image data, an external I / F 17 for outputting video data to a PC, and a memory control circuit 18 for controlling the image memory.

Then, the subject image is picked up by the CCD 10 and converted into an electric signal.
After the DS processing and the AGC processing, the ADC 13 converts the digital signal. Further, the driving circuit 11 is the CCD 1
In addition to generating various pulses for driving 0, electronic shutter control is performed. Further, the digital signal output from the ADC 13 is separated into a luminance signal and a color signal by the signal processing circuit 14, white balance processing, gamma correction, and the like are performed, and the image memory 16 is written in synchronization with the image clock WCK. 16 are stored. The data in the image memory 16 is read in synchronization with the read clock RCK and output to the PC by the external I / F 17.

Here, when the subject is illuminated by a fluorescent lamp that blinks at a power source frequency of 50 Hz and the vertical scanning frequency of the camera is 60 Hz, the signal is output from the signal processing circuit 14 as shown in FIG. The resulting video signal causes flicker in a 3-field cycle. In FIG. 2, (X) is the blinking cycle of the fluorescent lamp, (a) and (b)
Is a pulse output from the drive circuit 11 to the CCD 10, (a) is a charge sweep pulse, and (b) is a charge read pulse. While the charge sweep pulse (a) is being output, the signal charge is discharged to the deep portion of the substrate of the CCD 10, so the charge is accumulated after the charge sweep pulse is stopped, and the charge read pulse (b) causes the charge to be accumulated. Is read. Therefore, the shutter function can be realized by controlling the width of the charge sweep pulse.

Further, (A) represents the amount of electric charge output from the CCD. (C) is the vertical synchronization signal VD of the camera. Therefore, the control means 15 causes the signal processing circuit 14 to
The average value data LA of the screen brightness is received for each field, the brightest field is obtained, and the field write pulse WF is output to the memory control circuit. The memory control circuit 18 writes the data of the field indicated by WF in the image memory 16 and outputs it to the PC over 3 fields. In FIG. 2, (d) is a write signal WF output from the control means 15 to the memory control circuit 18, which is a pulse which becomes “H” in the brightest field period. The control circuit 18 inputs the write signal WF, the clock CLK and the horizontal synchronizing signal HD from the drive circuit 11, and controls the image memory.

2 (e) to 2 (h) show control pulses output to the image memory, all of which are "L" active pulses. (E) is a reset pulse (WRST) of the write address counter, (f) is a control pulse WE of the write operation, resets the write address counter at the head of the brightest field, and writes data in order from address 0. I'm out. (G) is a reset pulse RRST for the read address counter, (h) is a control pulse RE for the read operation, and the image data written in the image memory is read over three fields. Note that the WE and RE signals are at the “H” level during writing and reading, which cuts horizontal blanking. (B) shows the size of the video data output to the PC, in which the flicker component is eliminated and the field data in which the charges are most accumulated are output.

FIG. 3 shows the operation of the control means 15. First, the variables and arrays are initialized (S
1). FN is a variable that identifies the field being processed and has a value from 0 to 5. FMAXN is a variable for holding the field number having the largest amount of accumulated charge, and takes a value from 0 to 5. LA [N] is an array for substituting the luminance average of each field. Since N takes only a value from 0 to 5, when a negative number is obtained in the following process, 6 is added to make it a positive number and the process is performed. F
LC is a counter used to detect flicker conditions.

When the vertical synchronizing signal VD rises (S
2) The brightness average value of the previous field is read from the signal processing circuit and substituted into the array LA [N] (S3). The magnitude change between the read luminance average value LA [N] and the luminance average value LA [N-1] one field before is large, and the luminance average value LA [N-3] three fields before is obtained. If the values are the same, it is determined that flicker may occur (S4), and the variable FLC is incremented (S5). If the above conditions are not satisfied, it is determined that the flicker state is not present, and the variable FLC is cleared (S
6). When three fields are continuously in the flicker state (S7), the field having the largest charge amount is obtained, and the field NO is assigned to FMAXN.

The field number is incremented so as to make one cycle of 6 fields (S9, S10, S11),
If the next field NO matches FMAXN (S1
2), WF is set to "H" (S13), and the memory control circuit is instructed to write. WF is "L" one field later
become.

When the control is performed as described above, the image data from which the flicker component has been eliminated is transmitted to the PC at 20 fields / second, as shown in FIG. 2 (B). Also, the amount of image data transmitted becomes 1/3 of the output signal from the camera, and processing can be performed by the PC and the I / F unit.

[Second Embodiment] The second embodiment of the image input apparatus of the present invention changes the vertical scanning frequency of the camera according to the power supply frequency. Set the vertical scanning frequency. For example, in an area where the power supply frequency is 60 Hz, the power supply frequency is 50 Hz at 30 Hz.
In the z area, the camera is driven at 25 Hz. Further, even if the vertical frequency of the camera changes, the transmission speed to the external device is made constant by converting the vertical frequency in the image memory.

FIG. 4 is a block diagram of an image input apparatus according to the second embodiment of the present invention. In FIG. 4, the image input device includes a CCD 10, a preprocessing circuit 12, an ADC 13,
Signal processing circuit 14, image memory 1 for storing image data
6, an external I / F 17 that outputs video data to a PC, and these operations are the same as those in the first embodiment.

Here, the vertical scanning frequency of the camera is 30
Hz or 25 Hz. The operations of the drive circuit 19 and the memory control circuit 21 are switched by the vertical scanning frequency switching signal SEL from the control means 20. The basic clock CLK of the drive circuit 19 is 12M.
Hz, one horizontal scanning scanning period fH is 12 kHz (= 10
(00 clock), one vertical scanning period is composed of 400 horizontal lines when driven at 60 Hz, and 4 when driven at 50 Hz.
It shall consist of 80 horizontal lines. Also, CCD
From here, it is assumed that a signal of horizontal 352 pixels × vertical 288 lines, which is the number of pixels corresponding to CIF (Common Intermediate Format), is output.

First, the camera is operating at 30 Hz,
The timing is as shown in FIG. 5 when illuminated by a fluorescent lamp in an area where the power supply frequency is 60 Hz. In FIG. 5, (Y) is a lighting cycle of the fluorescent lamp, (i) is a pulse VD indicating a vertical scanning cycle, (j) is a charge sweep pulse,
(K) represents a charge read pulse, and (D) represents the amount of charge output from the CCD. In (D), of the 400 horizontal lines forming one vertical scanning period, the effective horizontal lines are 288 lines corresponding to the number of pixels of the CCD, and the remaining 122 lines are not transmitted to the PC. In this case, as shown in FIG. 5D, the amount of charge in each field is the same, and flicker does not pose a problem.

Next, FIG. 6 shows the timing when the camera is used in an area where the power supply frequency is 50 Hz when the camera is at 30 Hz. In FIG. 6, (X) is the lighting cycle of the fluorescent lamp,
(I) is a pulse VD indicating a vertical scanning period, (j) is a charge sweep pulse, (k) is a charge read pulse, (E)
Represents the amount of charge output from the CCD. As shown in (E), flicker occurs in a 3-field cycle.

The generated flicker is detected by the control means 20 in the same manner as in the first embodiment, and the vertical scanning frequency switching signal SEL is output. Upon receiving the SEL signal, the drive circuit 19 sets the vertical scanning frequency to 25.
Change to Hz. The timing at this time is also shown in FIG. (M) is a pulse VD indicating a vertical scanning period, (n) is a charge sweep pulse, and (p) is a charge read pulse. In this case, since the illuminance of the fluorescent lamp is constant during charge accumulation, flicker does not occur as shown in FIG. 6 (F).

FIG. 7 is a diagram for explaining the operation of the memory control circuit 21, in which (i), (D), (q), and (r) show the write operation at 30 Hz drive, and (m), (F), and (s). (T) shows the write operation at 25 Hz, and (u) (v) (G)
Indicates a read operation. Read operation is 30Hz and 2
It is common during 5 Hz operation. In FIG. 7, (i),
(M) is the vertical synchronizing pulse VD, (D) and (F) are the effective video signals output from the signal processing circuit 14,
(Q) and (s) show the reset pulse WRST of the write address counter, (r) and (t) show the write enable signal WE for controlling the write operation, and (u) shows the reset pulse RRST of the read address counter. v) is a read enable signal RE for controlling the read operation, (G)
Indicates a video signal read from the image memory.

When driven at 30 Hz, the video signal from the camera is written every 3 fields from (i) (D) (q) (r). That is, the video signal of 30 frames per second from the camera is thinned out to 10 frames per second in order to match the processing speed of an external device such as a PC. When driving at 25Hz,
As shown in (m), (F), (s), and (t), two images are written per five fields, and the video signal of 25 frames per second from the camera is thinned out to 10 frames per second. As shown in (u) (v) (G), reading from the image memory
It is performed at a cycle of 00ms, and 25H even when driven at 30Hz.
In the case of z drive, 10 images are output every second.

In the above embodiment, if the transfer rate of the image data with the external device can be varied, it is not necessary to match the number of images to be transferred. Further, if high-speed transfer is possible, the image memory is eliminated. , 30 or 25 images may be transmitted per second. Further, although the flicker is automatically detected, a switch or the like may be provided and the flicker may be switched depending on the area where the camera is used.

[0030]

Since the image input device of the present invention is configured as described above, according to the invention of claim 1, in the image input device for transmitting the image picked up by the image pickup means to the external device as a digital signal, A detection unit that detects the presence or absence of flicker and obtains the flicker occurrence period; and a control unit that obtains the charge amounts of a plurality of images obtained from the imaging unit within the flicker occurrence period and selects one image.
Since the storage unit that stores the image selected by the control unit and the output unit that outputs the image stored in the storage unit to the external device at each flicker occurrence cycle are provided, Since the image is updated and output, the image from which the flicker component is removed can be transmitted to an external device such as a PC.

According to the second aspect of the invention, in addition to the first aspect of the invention, the control means selects the image having the largest charge amount within the flicker generation cycle. An image with a good S / N can be transmitted.

Further, according to the invention described in claim 3, in the image input device for transmitting the image picked up by the image pickup means to the external device as a digital signal, the image pickup device is provided with the power supply frequency detecting means, and the power supply frequency is detected in accordance with the detected power supply frequency. In order to prevent the occurrence of flicker by changing the vertical scanning frequency of the image pickup means, the vertical frequency of the image pickup means is changed according to the power supply frequency, so that it is possible to obtain many images without flicker per unit time.

According to the invention described in claim 4, in addition to the invention described in claim 3, the driving device of the image pickup means capable of selecting the vertical scanning frequency, and the presence or absence of flicker is detected. Detecting means for obtaining the generation cycle of the drive, control means for changing the vertical scanning frequency of the driving device when flicker is detected by the detecting means, and storage for storing the image output by the imaging means in accordance with the vertical scanning frequency. Means and an output means for outputting the contents of the storage means to the external device in a constant cycle, the difference in vertical frequency of the image pickup means is absorbed, so that the transfer rate with the external device can be kept constant. it can.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an image input device according to a first embodiment of the present invention.

FIG. 2 is a timing diagram showing an operation of the image input device according to the first embodiment of the invention.

FIG. 3 is a flowchart showing the operation of the control means in the first exemplary embodiment of the present invention.

FIG. 4 is a configuration diagram of an image input device according to a second embodiment of the present invention.

FIG. 5 is a timing chart showing an operation of the image input device in an area having a power supply frequency of 60 Hz according to the second embodiment of the present invention.

FIG. 6 is a timing chart showing an operation of the image input device in an area having a power supply frequency of 50 Hz according to the second embodiment of the present invention.

FIG. 7 is a timing diagram showing an operation of the memory control circuit according to the second embodiment of the present invention.

[Explanation of symbols]

 10 CCD 11 CCD drive circuit 12 Pre-processing circuit 13 A / D converter 14 CCD signal processing circuit 15 Control means 16 Image memory 17 I / F circuit 18 Image memory control circuit 19 CCD drive circuit 20 Control means 21 Image memory control circuit

Claims (4)

[Claims] 1. An image input device for transmitting an image picked up by an image pickup means to an external device as a digital signal, and detecting means for detecting the presence / absence of flicker to determine the flicker occurrence period, and within the flicker occurrence period. The control means for obtaining one of the plurality of images obtained from the image pickup means to select one image, the storage means for storing the image selected by the control means, and the image stored in the storage means An image input device, comprising: an output unit that outputs to an external device at each flicker generation cycle. 2. The image input device according to claim 1, wherein the control means selects an image having the largest charge amount within the flicker generation cycle. 3. An image input device for transmitting an image picked up by an image pickup means to an external device as a digital signal, comprising a power supply frequency detection means, and changing the vertical scanning frequency of the image pickup means according to the detected power supply frequency. An image input device characterized by preventing flicker from occurring. 4. A drive device for the image pickup means capable of selecting a vertical scanning frequency, a detection means for detecting the presence or absence of flicker to obtain a flicker generation cycle, and a drive means for detecting the flicker by the detection means. Control means for changing the vertical scanning frequency of the apparatus, storage means for storing the image output by the imaging means in accordance with the vertical scanning frequency, and output means for outputting the contents of the storage means to an external device at a constant cycle. The image input device according to claim 3, further comprising: