JPH09270913A - Image signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image signal processor in which quantization error data are stored, even when number of picture elements of an image sensor is increased with a quantization error storage memory having a comparatively smaller capacity. SOLUTION: Multi-value input picture element data 5 read from an original 15, amplified by an image signal amplifier circuit 3, and converted by an A/D converter circuit 4 are given to a quantization circuit 6, and an error spread arithmetic circuit 9, in which error spread processing is conducted to calculate quantization error data caused when the data 5 are quantized into binary output picture element data 7 and the result is written and stored in a quantization error storage memory 12 for error spread processing of a succeeding line. In this case, the storage of quantization error data as to all picture elements or storage of quantization error data averaged by grouping plural picture elements into blocks is selected, based on the storage capacity of the quantization error storage memory and number of picture elements of the image sensor 2 set depending on the size of a read original.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal processing apparatus using an image sensor or the like, and relates to pixel data of a predetermined number of bits (hereinafter referred to as multi-valued pixel data) of low bit, especially 1 bit pixel data ( In the following description, variations in quantization error that occur during quantization into binary pixel data will be averaged.

[0002]

2. Description of the Related Art Generally, when quantizing multi-valued image data read by an image sensor into binary image data or the like, a quantization error occurs due to a difference between a read density of an original image and a black and white display density. . It is known that an image in which gradation and resolution are compatible to some extent can be obtained by locally diffusing this quantization error and performing a minimum approximation. This method is called the error diffusion method. First, the quantization error of the surrounding pixels is used to perform weighted averaging according to the distance from the pixel of interest,
It has been added to the pixel of interest, and the pixel of interest has been quantized with a fixed threshold.

FIG. 7 is a block diagram showing a conventional image signal processing apparatus of this type. In the figure, 1 is a lens system, 2 is a scanning position in a line direction, and an analog image signal is output pixel by pixel. The image sensor 3 is an image signal amplifier circuit that amplifies the image signal read from the image sensor 2, and 4 is the image signal from the image signal amplifier circuit 3 for each pixel 1
An analog-digital conversion circuit (hereinafter referred to as an A / D conversion circuit) 6 that converts input pixel data 5 that is byte digital data, 6 is 1-bit pixel data 7 by performing error diffusion processing on 1-pixel 1-byte input pixel data 5 Quantizing circuit outputs the quantized error data 8 by calculating the quantized error of each pixel by quantizing and outputting the quantized error Error diffusion processing data 11 based on the quantization error data 8 and the quantization error data 10 of the peripheral pixels on the previous line.
An error diffusion calculation circuit that calculates and outputs to the quantization circuit 6,
Reference numeral 12 is a quantization error storage memory in which the quantization error data 8 from the quantization circuit 6 is sequentially written, and the quantization error data 10 of the previous line is read out to the error diffusion calculation circuit 9, 13 is a control circuit, and 14 is A pixel clock signal output from the control circuit 13 that determines the timing of pixel readout, and 15 is a read original.

FIG. 8 is a diagram for explaining the error diffusion method. Each box corresponds to each pixel, and the letters Z and A to G written therein are the quantization error in that pixel, that is, Z is the present quantum. A, B, C, D of the target pixel on which the quantization processing is performed represent the quantization error of the peripheral pixels of the previous line (the line immediately above), and F, G represent the quantization error of the peripheral pixels of the current line. Indicates the weight when the error diffusion processing is performed.

FIG. 9 is a circuit diagram showing details of the quantizing circuit 6 and the error diffusion calculating circuit 9. In the figure, 61 is an A / D.
The 1-byte multi-valued input pixel data 5 from the conversion circuit 4 and the error diffusion processing data 11 from the error diffusion calculation circuit 9 are added, and the added value MSB (the binary value of the most significant bit) is output in binary. An addition circuit that outputs as pixel data 7, 62 is multi-valued addition data from the addition circuit 61, and multi-valued data of all bits 0 that is switched and output by the selector 63 depending on whether the binary output pixel data 7 is 0 or 1. “0” or all bits 1
This is a subtraction circuit that outputs the difference from the multi-valued data “R” as the quantization error data 8.

91A, 91B, 91C, 91D, 91E
Is a data transfer circuit for sequentially transferring the quantized error data 10 of the peripheral pixels of the previous line read from the quantized error storage memory 12 in synchronization with the pixel clock signal 14 from the control circuit 13, and 91F and 91G are quantized. A data transfer circuit for sequentially transferring the quantized error data 8 of the pixel at the position two before and at the previous position of the current line processed by the circuit 6 in synchronization with the pixel clock signal 14, and 92A and 92E, 1/16 division circuits, 92
B, 92D and 92F are 1/8 division circuits, 92C and 92G
Is a 1/4 division circuit, and each of the data transfer circuits 91A to 91G
Can be realized by shifting the multi-valued output data of 2 bits, 3 bits, and 4 bits. 93 is each division circuit 92A
It is an adder circuit that adds the output data of ~ 92G.

Next, the operation will be described. First, the document 15 to be read is set, the image sensor 2 is activated, and scanning of the document is started. The image signal for each pixel read from the original 15 is amplified by the image signal amplification circuit 3, converted into digital 1-pixel 1-byte input pixel data 5 by the A / D conversion circuit 4, and added by the quantization circuit 6. Circuit 6
Error diffusion processing data 1 from the error diffusion calculation circuit 9 applied to one terminal of the
1 is added. Since the error diffusion processing data 11 is multi-valued data “0” at the start of reading from the original 15, the MSB of the multi-valued input pixel data 5 is output from the addition circuit 61 as the binary output pixel data 7. On the other hand, the multivalued output data of the adder circuit 61 is applied to one input terminal of the subtractor circuit 62 and is output from the selector 63 depending on whether the binary output pixel data 7 applied to the other terminal is 0 or 1. Quantization error data 8 is output by performing subtraction with either multi-valued data "0" of all bits 0 or multi-valued data "R" of all bits 1. That is, the difference between the white or black multi-valued data output as binary data and the actually read multi-valued input pixel data 5 having gradation is calculated and output as the quantization error data 8. It is registered in the data transfer circuit 91G of the error diffusion calculation circuit 9.

By the application of the next pixel clock signal 14, the read input pixel data 5 of the next pixel is input to the adder circuit 61, and the quantization error data 8 of the previous pixel registered in the data transfer circuit 91G. Is the next data transfer circuit 9
At the same time when it is transferred to 1F, 1/4 in 1/4 division circuit 92G
The error diffusion processing data 11 is divided by 4 and added by the adder circuit 93 (other added values are 0 at this point). That is, the pixel data subjected to the error diffusion processing is obtained in the adder circuit 61, and the above quantization and the calculation of the quantization error data are performed on this data. In this way, for each pixel on the top line, image reading, error diffusion processing,
Quantization and calculation of quantization error data are performed, and the calculated quantization error data is sequentially written in the quantization error storage memory 12 via the data transfer circuits 91G and 91F.

When the next line is read out, error diffusion processing is performed by the peripheral pixels of the previous line stored in the quantization error storage memory 12. The processing of the target pixel Z of FIG. 8 on the third and subsequent pixels on the second line and below will be described below. At the time when the input pixel data of this pixel is input to the adder circuit 61, the data transfer circuits 91A, 91B, 91
Quantization error data A, B, C, D, E of the peripheral pixels on the preceding line of the pixel of interest read from the quantization error storage memory 12 are stored in C, 91D, 91E, and the data transfer circuit 91F and 91G include the quantization error data F, which is calculated before reading the current line, of the peripheral pixels of the current line.
G is registered. These quantized error data are divided by a value corresponding to the weight of each peripheral pixel by the division circuits 92A to 92G, added by the addition circuit 93, and input to the addition circuit 62 as error diffusion processing data 11.
This error diffusion processing data 11 is added to the input pixel data 5 of the pixel of interest, and the value subjected to the error diffusion processing is quantized to output binary output pixel data 7, which is output from the subtraction circuit 62. Quantized data is control circuit 1
The next pixel clock signal 14 from 3 is input to the data transfer circuit 91G.

The quantization, quantization error calculation, and error diffusion processing will be described more generally below. Here, assuming that the multi-valued pixel data 5 in a certain pixel is I (0 ≦ I ≦ R) and the quantization error is Err, when I> R / 2 (MSB = 1), Err = I−R (1 ) When I≤R / 2 (MSB = 0), Err = I-0 = I (2)

Further, the pixel data value of the pixel of interest is Iz, the corrected pixel data correction value of the error diffusion processing thereof is Iz ',
A, B, C, D, E, quantizing error data of peripheral pixels
F, G, and Fz, the weighted cumulative error for the pixel of interest, Fz = (A + B × 2 + C × 4 + D × 2 + E + F × 2 + G × 4) / 16 (3) Iz ′ = Iz + Fz (4) If the corrected pixel data value Iz 'that has been subjected to error diffusion processing is obtained by the equation (4) and this value is substituted into the equations (1) and (2) to obtain the quantized error data Z of the pixel of interest, then Iz'>
When R / 2, Z = Iz'-R (5) When Iz'≤R / 2, Z = Iz'-0 = Iz '(6)

The operation of the equation (3) is performed by the error diffusion operation circuit 9, and the operation of the equation (4) is performed by the adder circuit 61.
The subtraction circuit 62 performs the calculation of the equation (6). In this way, the MSB of the corrected pixel data value Iz 'of each pixel is output as the binary output pixel data 7, and the quantized error data F, G, and Z being processed are quantized error stored for the error diffusion calculation of the next line. It is stored in the memory 12.

[0013]

Since the conventional image signal processing device having the error diffusion function is configured as described above, one byte of quantized error data is stored for each pixel of the image sensor. Therefore, a quantization error storage memory having a storage capacity of bytes equivalent to the number of pixels of the image sensor is required. Therefore, when the number of pixels of the image sensor can be changed according to the size of the original, a quantization error storage memory having a large redundant storage capacity is required so as to correspond to the maximum number of pixels of the image sensor. ,
In the small-capacity quantization error storage memory, there is a problem that the error diffusion process cannot be performed even if a large-screen original is read by the image sensor.

The present invention has been made in order to solve the above problems, and is a quantization error storage memory having a relatively small capacity, and can cope with a change in the number of pixels of an image sensor depending on the size of an original. The purpose is to obtain an image signal processing device.

[0015]

An image signal processing apparatus according to the present invention includes an image sensor, an image signal amplifier circuit, and an analog-digital converter for converting each pixel signal from the image signal amplifier circuit into pixel data having a predetermined number of bits. Circuit, the pixel data of a predetermined number of bits from this analog-digital conversion circuit is subjected to error diffusion processing, quantized into low-bit number pixel data and output, and the quantization error of each pixel due to this quantization is calculated and quantized. A quantization circuit that outputs error data, a quantization error storage memory that stores the quantization error data output from this quantization circuit, and a quantization error of a predetermined pixel of the previous line read from this quantization error storage memory. Calculate data for error diffusion processing by using the data and the quantized error data of the predetermined pixel of the current line previously processed by the quantization circuit. In the image signal processing device including an error diffusion calculation circuit for outputting to the quantization circuit, the quantization error data written in the quantization error storage memory is divided into blocks for a plurality of pixels and averaged, and Block quantization error storage means for storing quantization error data in the quantization error storage memory, storage of quantization error data for all pixels in one line in the quantization error storage memory, and block quantization error Quantization error storage switching means for switching between storage by the storage means is provided.

Further, the block quantization error storage means is a plurality of block correction data storage means for forming blocks with different numbers of pixels. Further, the quantization error storage switching means is switched between storage of the quantization error for all pixels and storage by the block quantization error storage means according to the number of pixels of the image sensor and the storage capacity of the quantization error storage memory. It is the one.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an image signal processing apparatus according to this embodiment. In the figure, 1 is a lens system, 2 is an image sensor, 3 is an image signal amplifier circuit, 4 is an A / D conversion circuit, and 5 is many. Input pixel data of values, 6 is a quantization circuit, 7 is binary output pixel data, 8 is quantization error data of the current line, 9 is an error diffusion calculation circuit, 10 is quantization error data of the previous line, and 11 is Data for error diffusion processing,
Reference numeral 12 is a quantization error storage memory, 13 is a control circuit, 14 is a pixel clock signal, and 15 is an original to be read.
This is the same as the conventional example shown by. The image sensor 2 is configured so that pixel number data indicating the pixel number X set according to the size of the document is input to the control circuit 7.

Numeral 16 designates the quantized error data 8 of the current line from the error diffusion calculation circuit 9 as one quantized error data for each pixel, or blocks for every two pixels or every four pixels and averaged to form one block. An averaging circuit for switching and outputting to the quantization error storage memory 12 one quantization error data each,
An error data writing / reading circuit 17 creates an address for each pixel, for every two pixels or for every four pixels, and switches and sets it to the quantization error storage memory 12 to write and read the quantization error data. , 18 are created by the control circuit 13 in accordance with the pixel number data X from the image sensor 2 and store the quantization error data for each pixel, or store the quantization error data for every 2 pixels or every 4 pixels. A storage selection signal for selecting whether to store, 19 is a write / read clock signal that determines the timing of writing / reading the quantization error data to / from the quantization error storage memory 12, and 20 is a quantization error from the error data write / read circuit 17 during writing. Storage memory 1
2 is a write address signal, 21 is a read address signal output from the error data write / read circuit 17 to the quantization error storage memory 12 at the time of reading, and 22 is write quantization that is written and stored in the quantization error storage memory 12. This is error data. The averaging circuit 16 and the error data writing / reading circuit 17 form a block quantization error storage means.

FIG. 2 is a circuit diagram showing an example of the error data writing / reading circuit 17. In the drawing, 23 and 24 are, for example, T-type flip-flops, and the pixel clock signal 14 from the control circuit 13 is 1/2, and further. A 1/2 pulse frequency dividing circuit for dividing the frequency into 1/4, 25 is a pixel clock signal 14 from the control circuit 13 in response to a memory selection signal 18 from the control circuit 13, and 1/2 the pixel clock signal 14 A selector that selects either the divided pulse signal or the 1/4 divided pulse signal and outputs it as the storage clock signal 19, and 26 is the storage clock signal 19 from the selector 25.
Quantization error storage memory 1 incremented by
2 is a write address counter that outputs a write address signal 20 to 2, and 27 is a read address counter that is incremented by the storage clock signal 19 from the selector 25 and outputs to the quantization error storage memory 12 as a read address signal 21. The selector 25
Constitutes a quantization error memory switching means.

FIG. 3 is a circuit diagram showing an example of the averaging circuit 16. In the figure, 31, 32, 33 and 34 are 1-byte current line quantized error data input in parallel from the error diffusion calculation circuit 9. 8 is transferred to the next stage each time the pixel clock signal 14 is applied from the control circuit 13, and the data transfer circuits 35, 36, 37 and 38 are output from these data transfer circuits 31, 32, 33 and 34. Data, 39 is 2 output data 3 of the data transfer circuits 32 and 33
An adder circuit for adding 6, 37, 40 is an adder circuit 39
Output data, 41 is data transfer circuits 31, 32, 3
Adder circuit for adding 4 output data 35, 36, 37, 38 of 3, 34, 42 is output data of the adder circuit 41, 43
Is 1 which divides the output data 40 of the adder circuit 39 into 1/2
/ 2 division circuit, 44 is the output data of the 1/2 division circuit 43, 45 is a 1/4 division circuit that divides the output data 42 of the addition circuit 41 into 1/4, and 46 is the output data of the 1/4 division circuit 45 , 47 are memory selection signals 1 from the control circuit 13.
8 of the output data 38 of the data transfer circuit 34,
A selector that selects either the output data 44 of the / 2 division circuit 43 or the output data 46 of the 1/4 division circuit 45 and outputs it as output data 48. 49 is an error data write / read circuit for the output data 48 of the selector 47. The data transfer circuit outputs write quantization error data 22 to the quantization error storage memory 12 every time the write / read clock signal 19 is applied from 17. The selector 47 constitutes a quantization error memory switching means.

FIG. 4 is a time chart for explaining the operation when storing the quantization error data for all pixels, and FIG.
6 is a time chart for explaining the operation when storing the quantized error data by blocking every 2 pixels, and FIG. 6 is a time chart for explaining the operation when storing the quantized error data by blocking every 4 pixels. is there. In the figure, D
1 to D9 are D1, D2, ..., From the error diffusion calculation circuit 9.
The 1-byte quantized error data 8 is sequentially output to D9. 8 and 9 are also applied to this embodiment.

The operation of this embodiment will be described below. First, the document 15 to be read is set, and when the pixel number X of the image sensor 2 is set according to the size of the document to be read, pixel number data indicating the pixel number X is input to the control circuit 13. It The number X of pixels is compared with the storage capacity (Y byte) of the memory 12 in the control circuit 13, and when X ≦ Y, all pixel storage, when 1 / 2X ≦ Y <X, block storage in units of 2 pixels, 1 When / 4X ≦ Y <1 / 2X, the data for selecting the block storage in units of 4 pixels is written in the register or the like in the control circuit 13, and the storage selection signal 18 corresponding thereto is output to the averaging circuit 16 and the error data. It is output to the write / read circuit 17.

Next, the scanning of the document by the image sensor 2 is started. The image signal for each pixel read out from the original 15 is amplified by the image signal amplification circuit 3, converted into digital input pixel data 1 byte of 1 pixel by the A / D conversion circuit 4, and applied to the quantization circuit 6. To be done. This quantization circuit 6
Then, after the input pixel data 5 and the error diffusion processing data 11 from the error diffusion calculation circuit 9 are added and subjected to error diffusion processing, the pixel data after the error diffusion processing is quantized and the quantization error is calculated. The error diffusion processing data 11 is calculated by the calculated quantization error 8 of the current line and the quantization error 10 of the previous line read from the quantization error storage memory 12, and is processed next. Pixel data 5
Is applied to the quantizer circuit 6 for. The above error diffusion processing,
Since the quantizing and quantizing error calculating operations are the same as those described with reference to FIGS. 8 and 9, detailed description thereof will be omitted.

The quantizing error 8 of the current line calculated by the quantizing circuit 6 and used for calculating the error diffusion processing data by the error diffusion calculating circuit 9 is input to the averaging circuit 16 and selected by the control circuit 13 for storage selection. Depending on the storage method determined by the signal 18, one pixel, two pixels, or four pixels are set as one block, digital data values in the block are averaged, and the result is set as one quantization error data for one block. The quantization error data written in the quantization error storage memory 12 sequentially, while the quantization error data written in the quantization processing of the previous line pixel from the quantization error storage memory 12, is stored in the storage selection signal 18
Depending on the storage method determined by, 1 quantization error data for each pixel, 1 quantization error data for every 2 pixels, or 1 quantization error data for every 4 pixels are sequentially read out for error diffusion processing. To be done.

Next, the operation of the error data write / read circuit 17 will be described with reference to FIG. First, when the storage selection signal 18 from the control circuit 13 indicates the total quantization error storage operation, the pixel clock signal 14 from the control circuit 13 is directly applied to the write address counter 26 and the read address counter 27 by the selector 25. The counters 26 and 27 are incremented at the rising edge of the signal, and the write address signal 2 is written in the quantization error storage memory 12.
It is output as 0 and the read address signal 21. That is, the quantization error data output from the averaging circuit 16 for each pixel is written in the address incremented for each pixel in the quantization error storage memory 12, and stored in the quantization error storage memory 12. The quantized error data of the preceding line is read from the address incremented for each pixel. At this time, the timing pulse having the same cycle as the pixel clock signal 14 selected by the selector 25 is output to the averaging circuit 16 as the write / read clock signal 19.

During the block quantization error storage operation in units of two pixels, the pixel clock signal 14 from the control circuit 13 is 1 /
The pulse divided by 1/2 by the 2-pulse frequency dividing circuit 23 is selected by the selector 25 and applied to the counters 26 and 27, incremented at the rising edge of the pulse, and the address signal 16 is supplied to the quantization error storage memory 12. Is output as. That is, the quantization error data output from the averaging circuit 16 for every two pixels is written to the address of the quantization error storage memory 12 that is incremented for every two pixels, and stored in the quantization error storage memory 12. The quantized error data of the preceding line being read is read from the address incremented for every two pixels. At this time, the timing pulse of the double cycle of the pixel clock signal 14 selected by the selector 25 is output to the averaging circuit 16 as the write / read clock signal 19.

During a block quantization error storage operation in units of 4 pixels, the pixel clock signal 14 from the control circuit 13 is 1 /
By the 2-pulse frequency dividing circuit 23, it is further halved to 1/2
The pulse divided by the pulse frequency dividing circuit 24 into 1/2, and as a result, the pulse divided into 1/4 is selected by the selector 25 and applied to the counters 26 and 27, which is incremented at the rising edge of the pulse and The address signal 16 is output to the digitization error storage memory 12. That is, the quantization error data output from the averaging circuit 16 every 4 pixels is written to the address of the quantization error storage memory 12 that is incremented every 4 pixels, and then stored in the quantization error storage memory 12. The quantized error data of the preceding line is read from the address incremented every 4 pixels. At this time, the timing pulse of the quadruple cycle of the pixel clock signal 14 selected by the selector 25 is output to the averaging circuit 16 as the write / read clock signal 19.

Next, the averaging circuit 16 will be described with reference to FIGS.
The detailed operation of will be described. First, when the full quantization error storage operation is selected by the storage selection signal 18 from the control circuit 13, as shown in FIG. 4, the 1-byte quantization error data 8 (D1, …, D9)
Each time the pixel clock signal 14 from the control circuit 13 falls, it is set in the data transfer circuit 31, its content is output as output data 35 at the next rising edge of the pixel clock signal 14, and at the falling edge of the next stage. Data transfer circuit 32
Is set to In this way, the pixel clock signal 14
The quantization error data 8 is transferred to the data transfer circuit 32,
33, 34 and the fourth pixel clock signal 14
At the rising edge of, the output data 38 is set in the data transfer circuit 49 through the selector 47 which selects the all-pixel correction operation. The set data is the error data write / read circuit 17 having the same cycle as the pixel clock signal 14.
Write quantization error data 22 is output to the quantization error storage memory 12 at every rise of the write / read clock signal 19 from.

On the other hand, during the block storage operation in units of 2 pixels, as shown in FIG. 5, the data transfer circuits 31, 32, 3 are
The data transfer operations of 3 and 34 are similar to the above-described all-pixel correction operation, but the output data 36 of the second data transfer circuit 32 and the output data 37 of the third data transfer circuit 33 are added by the adder circuit 39. And the added data 40 is 1 /
The data 44 divided by 1/2 in the 2 division circuit 43 and averaged is set in the data transfer circuit 49 through the selector 47 that selects the block storage operation in units of 2 pixels. This set data is the pixel clock signal 1
Error data write / read circuit 17 having a cycle twice that of 4
Write quantization error data 22 is output to the quantization error storage memory 12 at every rise of the write / read clock signal 19 from.

On the other hand, during the block storing operation in units of 4 pixels, as shown in FIG. 6, the data transfer circuits 31, 32, 3
The data transfer operations of 3, 34 are the same as the all-pixel correction operation described above, but all the data transfer circuits 31, 32, 33, 34
Output data 35, 36, 37, and 38 are added by an adder circuit 41, and the added data 42 is divided by 1/4 by a 1/4 divider circuit 45 to be averaged. It is set in the data transfer circuit 49 through the selector 47 which selects the storage operation. The set data is output to the quantization error storage memory 12 as the write quantization error data 22 at every rise of the write / read clock signal 19 from the error data write / read circuit 17 whose cycle is four times as long as the pixel clock signal 14. To be done.

As described above, the quantization error storage memory 1
The quantized error data written in 2 is read at the time of the error diffusion processing of the pixel of the next line. At this time, the same quantized error data is used for a plurality of pixels in the same block. That is, in the block storage operation in units of 2 pixels, the quantization error data A to E in the previous line in FIG. 8 are, for example, A = B = (A + B) / 2, C = D = (C + D) / 2, E =
It is replaced with (E + E ') / 2, and in the block storage operation of 4 pixel unit,
For example, A = B = C = D = (A + B + C + D) / 4, E = (E + E '
+ E '' + E ''') / 4 can be replaced. Here, E ′, E ″, and E ′ ″ are the quantization error data of the pixels sequentially arranged next to the E corresponding pixel.

In this embodiment, the case where 1-byte multi-valued pixel data is quantized into 2-bit binary pixel data has been described. However, the number of bits of quantized multi-valued pixel data is limited to 1 byte. Of course, it is not limited to binary pixel data, and is applicable not only to binary pixel data, but also to quantization into low-bit-number multivalued pixel data.

[0033]

As described above, according to the present invention, the quantization error data generated by the quantization of the pixel data is blocked and averaged for each plurality of pixels, and the quantization error data for each block is stored in the quantization error storage memory. Since it is possible to store the quantization error data for all pixels and to switch between the storage of the quantization error storage memory of the quantization error data for all pixels and the storage of the blocked and averaged quantization error data, the quantization error of a small capacity can be stored. Even if the storage memory is used, there is an effect that an image signal processing device that can sufficiently cope with the change in the number of pixels of the image sensor can be obtained by a simple change in the configuration.

Further, in the above-mentioned one, since a plurality of block quantizing error data blocked by different numbers of pixels can be switched and stored in the quantizing error storing memory, the image sensor of a wider range can be used. This has an effect of being able to cope with a change in the number of pixels.

Further, depending on the number of pixels of the image sensor and the storage capacity of the quantization error storage memory, the storage of the quantization error data for all the pixels and the storage of the blocked and averaged quantization error data are switched. Therefore, the optimum quantization error data storage method can be automatically selected by setting the number of pixels of the image sensor.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of an error data write / read circuit of this embodiment.

FIG. 3 is a circuit diagram showing an example of an averaging circuit of this embodiment.

FIG. 4 is a time chart for explaining an all-pixel quantization error storage operation in this embodiment.

FIG. 5 is a time chart explaining a block quantization error storage operation in units of two pixels in this embodiment.

FIG. 6 is a time chart explaining a block quantization error storing operation in units of 4 pixels according to the present embodiment.

FIG. 7 is a block diagram showing a conventional image signal processing device.

FIG. 8 is a diagram illustrating an error diffusion method.

FIG. 9 is a circuit diagram showing details of a quantization circuit and an error diffusion calculation circuit.

[Explanation of symbols]

2 image sensor, 3 image signal amplification circuit, 4 A /
D conversion circuit, 5 input image data, 6 quantization circuit, 7
Binary pixel data, 8 current line quantization error data, 9 error diffusion calculation circuit, 10 previous line quantization error data, 11 error diffusion processing data, 12 quantization error storage memory, 13 control circuit, 14 pixels Clock signal, 16 averaging circuit (block quantization error storage means), 17 error data write / read circuit (block quantization error storage means), 18 storage selection signal, 19 write / read clock signal, 20 write address signal, 21
Read address signal, 22 write quantization error data, 25, 47 selector (quantization error storage switching means).

Claims (3)

[Claims] 1. An image sensor, an image signal amplification circuit, an analog-digital conversion circuit for converting each pixel signal from the image signal amplification circuit into pixel data having a predetermined number of bits, and a pixel having a predetermined number of bits from the analog-digital conversion circuit. Quantization circuit that performs error diffusion processing on data and quantizes and outputs it to pixel data with a low number of bits, and calculates the quantization error of each pixel by this quantization and outputs quantized error data. A quantization error storage memory that stores the output quantization error data, the quantization error data of a predetermined pixel on the previous line read from this quantization error storage memory, and the current value that was previously processed in the quantization circuit. An error diffusion calculation circuit for calculating error diffusion processing data based on the quantized error data of a predetermined pixel on the line and outputting the data to the quantization circuit. In the image signal processing device, the quantization error data written in the quantization error storage memory is divided into blocks for each plurality of pixels and averaged, and the quantization error data for each block is stored in the quantization error storage memory. Quantization error storage means, quantization error storage switching means for switching between storage of the quantization error data for all pixels in one line in the quantization error storage memory, and storage by the block quantization error storage means. An image signal processing device provided. 2. The image signal processing apparatus according to claim 1, wherein the block quantization error storage means is composed of a plurality of block quantization error storage means for dividing into blocks for different numbers of pixels. 3. The quantizing error memory switching means comprises means for storing the quantizing error data for all pixels and a block quantizing error memory means according to the number of pixels of the image sensor and the memory capacity of the quantizing error memory memory. 3. The image signal processing device according to claim 1, wherein the image signal processing device is switched between storage and storage.