JPH09252403A - Image signal processing unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an image signal processing unit in which a correction data storage memory with a comparatively smaller capacity stores correction data even when the number of picture element is increased. SOLUTION: All image data 5 obtained by reading a while reference density board 11 with an image sensor 2 are averaged for each block consisting of plural pixels by an averaging circuit 12 and correction data 17 for each block are stored in a correction data storage memory 6. Then storage of correction data of all pixels of all the image data 5 or storage of correction data obtained by applying block and averaging processing to plural pixels is switched depending on the number of pixels of the image sensor 2 set depending on a size of an original to be read and on a storage capacity of a correction data storage memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal processing device using an image sensor or the like, and more particularly to correcting variations in photoelectric conversion characteristics due to nonuniformity of light amount distribution of a light source. .

[0002]

2. Description of the Related Art Generally, image data read by an image sensor is affected by non-uniformity of light amount distribution of a light source and variations in sensitivity of each pixel, and therefore it is necessary to correct variations in photoelectric conversion characteristics. Becomes This correction is called non-uniformity correction.As a correction method, the correction data obtained by photoelectrically converting the white reference surface before image data reading is stored in the memory, and the correction amount is read from the memory when reading the image data. A method of calculating and correcting using an arithmetic circuit has been adopted.

FIG. 7 is a block diagram showing a non-uniformity correction circuit of a conventional image signal processing apparatus of this kind. In the figure, 1 is a lens system in which focus, magnification and reading position are adjusted in advance,
2 is an image sensor which scans the reading position in the horizontal direction and outputs an analog image signal from a plurality of pixels in pixel units,
Reference numeral 3 is an image signal amplification circuit for amplifying the image signal read from the image sensor 2, and 4 is an analog-digital conversion circuit (hereinafter A) for converting the image signal amplified by the image signal amplification circuit 3 into digital data of 1 byte per pixel. / D conversion circuit), 5 is input image data output from the A / D conversion circuit 4, 6 is a correction data storage memory for storing nonuniformity correction data (hereinafter referred to as correction data), 7 is a control circuit, Reference numeral 8 is a correction calculation circuit for performing nonuniformity correction of the input image data 5 based on the correction data read from the correction data storage memory 6, 9 is a pixel clock signal output from the control circuit 7 for determining the pixel read timing, and 10 is not. The uniformly corrected output image data 11 is a white level image read by the image sensor 2 when the correction data is stored in the correction data storage memory 6. Which is the reference density plate of Sutame.

Next, the operation will be described. First, the white reference density plate 11 serving as a reference for nonuniformity correction is set, the image sensor 2 is activated, and the scanning of the reference density plate 11 is started. An analog image signal output from the image sensor 2 on a pixel-by-pixel basis is amplified by an image signal amplification circuit 3 and adjusted to a white level, converted by an A / D conversion circuit 4 into digital data of 1 pixel 1 byte, and 1 pixel. The correction data is sequentially stored as correction data in the correction data storage memory 6. When the correction data for all the pixels of the image sensor 2 is stored in the correction data storage memory 6 in this way, the control circuit 7 is ready to read the image sensor 2.
Enters the document scanning waiting state.

Next, the document to be read is set, the image sensor 2 is activated, and the scanning of the document is started. The image signal for each pixel read from the original is amplified by the image signal amplification circuit 3, converted into digital input image data 5 of 1 pixel per pixel by the A / D conversion circuit 4, and input to the correction calculation circuit 8. It At the same time, the correction data corresponding to the pixel position of the input image data 5 is read from the correction data storage memory 6 in synchronization with the pixel clock 9 from the control circuit 7 and input to the correction arithmetic circuit 8. The correction calculation circuit 8 calculates output image data 10 = input image data 5 × white level reference value / correction data.

[0006]

Since the conventional image signal processing apparatus having the nonuniformity correction function is configured as described above, one byte of correction data is stored for each pixel of the image sensor. In addition, a correction data storage memory having a storage capacity of bytes equivalent to the number of pixels of the image sensor was required. Therefore, when the number of pixels of the image sensor can be changed according to the size of the original, a correction data storage memory having a large redundant storage capacity is required so as to correspond to the maximum number of pixels of the image sensor, In the small-capacity correction data storage memory, there is a problem that nonuniformity correction cannot be performed even if a large-screen original is read by the image sensor.

The present invention has been made in order to solve the above-mentioned problems, and it is an image capable of accommodating a change in the number of pixels of an image sensor in accordance with the size of a document with a correction data storage memory having a relatively small capacity. The purpose is to obtain a signal processing device.

[0008]

An image signal processing apparatus according to the present invention is obtained by reading an image input unit having an image sensor, an image signal amplification circuit and an analog-digital conversion circuit, and a reference density plate by the image input unit. An image signal processing apparatus comprising: a correction data storage memory for storing the correction data thus obtained; and a correction arithmetic circuit for correcting the read data from the image input means with the correction data from the correction data storage memory and outputting the correction data. Block correction data storage means for storing all the image data read out from the reference density plate by the image input means into a plurality of pixels into blocks and averaging, and storing correction data for each block in the correction data storage memory; and the reference density plate. To the correction data storage memory of the correction data for all pixels of the image data read from And storage, is provided with a correction data switching means for switching the memory by the block compensation data storage means.

Further, the block correction data storage means is a plurality of block correction data storage means for forming blocks with different numbers of pixels. Further, the correction data switching means is configured to switch between storage of correction data for all pixels and storage by the block correction data storage means according to the number of pixels of the image sensor and the storage capacity of the correction data storage memory. .

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a nonuniformity correction circuit of this embodiment. In the figure, 1 is a lens system, 2 is an image sensor, 3 is an image signal amplification circuit, 4 is an A / D conversion circuit, and 5 is an input. Image data, 6 is a correction data storage memory, 7 is a control circuit, 8 is a correction calculation circuit, 9 is a pixel clock signal, 10 is output image data, 11 is a reference density plate, and the above is the same as the conventional example shown in FIG. Lens system 1, image sensor 2, image signal amplification circuit 4 and A
The / D conversion circuit 4 constitutes an image input means. The image sensor 2 is configured so that pixel number data indicating the pixel number X set according to the size of the document is input to the control circuit 7.

Reference numeral 12 is a block of the entire input image data 5 read from the reference density plate 11 as one correction data for each pixel, or is divided into blocks for every two pixels or every four pixels and averaged to make one correction for each block. An averaging circuit 13 for switching and outputting to the correction data storage memory 6 as data,
An address creating circuit that creates an address for every 2 pixels or every 4 pixels and switches and sets it to the correction data storage memory 6.
Reference numeral 14 is created by the control circuit 7 according to the pixel number data X from the image sensor 2 and determines whether to create correction data for each pixel or for every two pixels or every four pixels. A correction selection signal to be selected, 15 is a correction clock signal that determines the timing for outputting correction data, 16
Is an address signal output from the address creating circuit 13 to the correction data storage memory 6, and 17 is correction data stored in the correction data storage memory 6. The averaging circuit 1
2 and the address creation circuit 13 constitute a block correction data storage means.

FIG. 2 is a circuit diagram showing an example of the address generating circuit 13. In the figure, 18 and 19 are, for example, T-type flip-flops, and the pixel clock signal 9 from the control circuit 7 is 1/2 and 1 /. A 1/2 pulse frequency dividing circuit for dividing the frequency into 4 is a pixel clock signal 9 from the control circuit 7 according to the correction selection signal 14 from the control circuit 7, and the pixel clock signal 9 is frequency divided into 1/2. Pulse signal and 1 /
A selector that selects any one of the pulse signals divided by 4 and outputs it as the correction clock signal 15, and 21 is a selector 2
It is a counter that is incremented by a correction clock signal 15 from 0 and outputs as an address signal 16 to the correction data storage memory 6. The selector 20 constitutes correction data switching means.

FIG. 3 is a circuit diagram showing an example of the averaging circuit 12. In the figure, reference numerals 22, 23, 24 and 25 denote 1-byte input image data 5 input in parallel from the A / D conversion circuit 4. , A data transfer circuit composed of flip-flops, which is transferred to the next stage every time the pixel clock signal 9 is applied from the control circuit 7, 26, 27, 28 and 29 are output data of these data transfer circuits 22, 23, 24 and 25, 30 is an adder circuit for adding the two output data 27, 28 of the data transfer circuits 23, 24, 31 is the output data of the adder circuit 30, 32
Is an adder circuit for adding the four output data 26, 27, 28, 29 of the data transfer circuits 22, 23, 24, 25, 33 is the output data of the adder circuit 32, and 34 is 1/2 the output data 31 of the adder circuit 30. ½ division circuit for dividing by, 35 is output data of ½ division circuit 34, and 36 is addition circuit 32
1/4 division circuit that divides the output data 33 of
37 is the output data of the 1/4 divider circuit 36, 38 is the output data 29 of the data transfer circuit 25, the output data 35 of the 1/2 divider circuit 34 and 1/38 according to the correction selection signal 14 from the control circuit 7. A selector that selects any one of the output data 37 of the divide-by-four circuit 36 and outputs it as output data 39. Reference numeral 40 denotes the output data 39 of the selector 38 each time the correction clock signal 15 is applied from the address creating circuit 13 to the correction data storage memory. 6 is a data transfer circuit that outputs the stored data to the storage device 6. The selector 38 constitutes correction data switching means.

FIG. 4 is a time chart for explaining the all-pixel correction operation when storing the correction data for all pixels.
FIG. 5 is a time chart for explaining a block correction operation in units of 2 pixels in which correction data is divided into blocks for every 2 pixels, and FIG. 6 is a block correction operation in units of 4 pixels in which correction data is divided into blocks for every 4 pixels and stored. 3 is a time chart for explaining. In the figure, D1 to D9 are 1-byte input image data 5 sequentially output from the A / D conversion circuit 4 to D1, D2, ..., D9.

The operation of this embodiment will be described below. First, the pixel number X of the image sensor 2 is set according to the size of the document to be read, and the pixel number data indicating the pixel number X is input to the control circuit 7. In the control circuit 7, the number X of pixels is compared with the storage capacity (Y byte) of the memory 6, and when X ≦ Y, all pixel correction, 1 / 2X ≦ Y <X.
In case of, block correction in units of 2 pixels, 1 / 4X ≦ Y <1 /
In the case of 2 ×, the data for selecting the block correction in units of 4 pixels is written in the register or the like in the control circuit 7, and the correction selection signal 14 corresponding thereto is output to the averaging circuit 12 and the address creating circuit 13.

Next, the white reference density plate 11 as a reference for nonuniformity correction is set, the image sensor 2 is activated, and the scanning of the reference density plate 11 is started. An analog image signal output from the image sensor 2 in pixel units is
The image signal amplifier circuit 3 amplifies and adjusts to a white level, and the A / D converter circuit 4 converts it into digital data of 1 byte per pixel. That is, the input image data 5 of the white reference density plate 11 is applied to the averaging circuit 12 pixel by pixel. In the averaging circuit 5, the digital input image data 5 for correction is divided into one block of one pixel, two pixels, or four pixels according to the correction method determined by the correction selection signal 14 from the control circuit 7, Are averaged, and the result is sequentially stored in the correction data memory 6 as one correction data for one block. When the correction data for all the pixels of the image sensor 2 is stored in the correction data storage memory 6 in this way, the control circuit 7 is ready to read the image sensor 2.
Enters the document scanning waiting state.

Next, the operation of the address creating circuit 13 will be described with reference to FIG. First, when the correction selection signal 14 from the control circuit 7 indicates the all-pixel correction operation, the pixel clock signal 9 from the control circuit 7 is directly applied to the counter 21 by the selector 20, and the counter 21 receives the rising edge of the signal. It is incremented and output as the address signal 16 to the correction data storage memory 6. That is, the correction data output from the averaging circuit 12 for each pixel is stored in the corrected data storage memory 6 at the address incremented for each pixel.

During the block correction operation in units of 2 pixels, the pixel clock 9 from the control circuit 7 is divided into 1/2 pulse frequency dividing circuit 1.
The pulse divided by ½ by 8 is selected by the selector 20, applied to the counter 21, incremented at the rising edge of the pulse, and output to the correction data storage memory 6 as the address signal 16. That is,
The correction data output from the averaging circuit 12 for every two pixels is stored in the correction data storage memory 6 at the address incremented for every two pixels.

During the block correction operation in units of 4 pixels, the pixel clock 9 from the control circuit 7 is divided into ½ pulse frequency dividing circuits 1.
8 by 1/2, and further by 1/2 pulse divider circuit 19
The pulse divided by ½ by 1 and divided by 1 as a result is selected by the selector 20 and applied to the counter 21, incremented at the rising edge of the pulse, and addressed to the correction data storage memory 6. The signal 16 is output. That is, the correction data output from the averaging circuit 12 every 4 pixels is stored in the address of the storage memory 6 that is incremented every 4 pixels. The timing pulse selected by the selector 20 is output to the averaging circuit 12 as the correction clock signal 15.

Next, the averaging circuit 12 will be described with reference to FIGS.
The detailed operation of will be described. First, when the all-pixel correction operation is selected by the correction selection signal 14 from the control circuit 7,
As shown in FIG. 4, the input image data 5 (D
, ..., D9) are set in the data transfer circuit 22 at every fall of the pixel clock signal 9 from the control circuit 7, and the contents thereof are output as output data 26 at the next rise of the pixel clock signal 9. At the time of its fall, it is set in the data transfer circuit 23 of the next stage. In this way, every time the pixel clock signal 9 is applied, the input image data 5 is transferred to the data transfer circuits 23, 24 and 25, and when the fourth pixel clock signal 9 rises, the output data 29 selects the all pixel correction operation. It is set in the data transfer circuit 40 through the selector 38 that is operating. The set data is output to the correction data storage memory 6 as the correction data 17 every time the correction clock signal 15 from the address creating circuit 13 having the same cycle as the pixel clock signal 9 rises.

On the other hand, during the block correction operation in units of 2 pixels, as shown in FIG. 5, the data transfer circuits 22, 23, 2
The data transfer operations of Nos. 4 and 25 are similar to the above-described all-pixel correction operation, but the output data 27 of the second data transfer circuit 23 and the output data 28 of the third data transfer circuit 24 are added by the adder circuit 30. And the added data 31 is 1 /
The data 35 divided by 1/2 in the 2 division circuit 34 and averaged is set in the data transfer circuit 40 through the selector 38 that selects the block correction operation in units of 2 pixels. This set data is the pixel clock signal 9
Is output to the correction data storage memory 6 as the correction data 17 at every rising edge of the correction clock signal 15 from the address creating circuit 13, which has a cycle twice as long as.

On the other hand, during the block correction operation in units of 4 pixels, as shown in FIG. 6, the data transfer circuits 22, 23, 2 are
The data transfer operation of Nos. 4, 25 is the same as the all-pixel correction operation described above, but all the data transfer circuits 22, 23, 24, 25
Output data 26, 27, 27, 28, 29 are added by the adder circuit 32, and the added data 33 is divided by 1/4 by the 1/4 divider circuit 36 to be averaged to obtain data 37.
It is set in the data transfer circuit 40 through the selector 38 that selects the block correction operation in units of 4 pixels. The set data is output to the correction data storage memory 6 as the correction data 17 every time the correction clock signal 15 from the address creating circuit 13 has a cycle four times as long as the pixel clock signal 9.

When the storage of the correction data in the correction data storage memory 6 as described above is completed, the image sensor 2 is ready for reading and a new document to be read is set and the image sensor 2 is started up. Scanning is started. The image signal for each pixel read from the original is amplified by the image signal amplification circuit 3, converted into digital input image data 5 of 1 pixel per pixel by the A / D conversion circuit 4, and input to the correction calculation circuit 8. It At the same time, the correction data corresponding to the block to which each pixel position of the input image data 5 belongs is incremented every time the correction clock signal 15 of the correction data storage memory 6 rises in synchronization with the pixel clock 9 from the control circuit 7. The data is read from the address and input to the correction calculation circuit 8. That is, the same correction data is used for a plurality of pixels in the same block. Then, the correction calculation circuit 8 calculates output image data 10 = input image data 5 × white level reference value / correction data. In this way, by using the small-capacity memory 6, it is possible to perform nonuniformity correction in response to changes in the number of pixels of the image sensor 2.

[0024]

As described above, according to the present invention, all the image data read from the reference density plate is divided into blocks for each of a plurality of pixels and averaged, and the correction data for each block can be stored in the correction data storage memory. Since the storage of the correction data for all the pixels of the image data read from the reference density plate in the correction data storage memory and the storage of the block-averaged correction data are switched, it is possible to store a small amount of correction data. Even if the memory is used, there is an effect that an image signal processing device which can sufficiently cope with a change in the number of pixels of the image sensor can be obtained by a simple configuration change.

Further, in the above-mentioned one, since a plurality of block correction data blocked by different numbers of pixels can be switched and stored in the correction data storage memory, the pixel number of the image sensor in a wider range can be changed. There is an effect that can correspond to.

Further, according to the number of pixels of the image sensor and the storage capacity of the correction data storage memory, the storage of the correction data for all the pixels and the storage of the block-averaged correction data are switched. There is an effect that the optimum correction data storage method can be automatically selected by setting the number of pixels of the sensor.

[Brief description of drawings]

FIG. 1 is a block diagram showing a nonuniformity correction circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of an address generation circuit of this embodiment.

FIG. 3 is a circuit diagram showing an example of an averaging circuit of this embodiment.

FIG. 4 is a time chart illustrating an all-pixel correction operation according to this embodiment.

FIG. 5 is a time chart explaining a block correction operation in units of 2 pixels in this embodiment.

FIG. 6 is a time chart explaining a block correction operation in units of 4 pixels in this embodiment.

FIG. 7 is a block diagram showing a nonuniformity correction circuit of a conventional image signal processing device.

[Explanation of symbols]

1 lens system (image input means), 2 image sensor (image input means), 3 image signal amplification circuit (image input means), 4 A / D conversion circuit (image input means), 5 input image data, 6 correction data storage Memory, 7 control circuit,
8 correction calculation circuit, 9 pixel clock signal, 10 output image data, 11 reference density plate, 12 averaging circuit (block correction data storage means), 13 address creation circuit (block correction data storage means), 14 correction selection signal, 15 Correction clock signal, 16 address signal, 17
Correction data, 20, 38 selector (correction data switching means).

Claims (3)

[Claims] 1. An image input means having an image sensor, an image signal amplification circuit and an analog-digital conversion circuit, a correction data storage memory for storing correction data obtained by reading a reference density plate by the image input means, and In an image signal processing device having a correction arithmetic circuit for correcting read data from the image input means with the correction data from the correction data storage memory and outputting the same, all image data read from the reference density plate by the image input means. Block correction data storage means for storing the correction data for each block in the correction data storage memory, and correcting the correction data for all the pixels of the image data read from the reference density plate. Storage in correction data storage memory and storage by the block correction data storage means An image signal processing device, comprising: a correction data switching means for switching between and. 2. The image signal processing apparatus according to claim 1, wherein the block correction data storage means comprises a plurality of block correction data storage means for forming blocks with different numbers of pixels. 3. The correction data switching means switches between storage of correction data for all pixels and storage by the block correction data storage means according to the number of pixels of the image sensor and the storage capacity of the correction data storage memory. The image signal processing device according to claim 1 or 2, characterized in that.