JPH09270774A - Synchronism pull-in circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit capable of performing synchronism pull-in at a high speed. SOLUTION: At the time of a synchronism pull-in mode, the reference data 41 of a storage circuit 4 are read by an added address 11 for which an address specifying signal 31 and a phase difference setting value are added and simultaneously, reception data are held in a latch circuit 6 by a holding pulse 42 and also an error counter circuit 10 starts counting. When the reference data 41 and the reception data match, the counting of the error counter circuit 10 is stopped and the error counted value 105A of the phase difference of the reference data 41 and the reception data is obtained. At the time of an error measurement mode, by the compared result of the reception data 102A and the reference data 41 read from the storage circuit 4 by the added address 11 of a value for which '1' is added to the error counted value 105A of the phase difference and the address specifying signal 31, the error counter circuit 10 performs up- counting to the error counted value 105A of the phase difference and the error counted value is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sync pull-in circuit, and more particularly to a receive data sync pull-in circuit in a circuit for measuring a code error in a data string of received data.

[0002]

2. Description of the Related Art In a sync pull-in circuit for measuring a code error for measuring an error in a received data string,
An error is measured by comparing the received data string with the internally generated reference data. In order to measure the error, this referenced data needs to be synchronized with the received data.

Conventionally, in order to pull in this synchronization, the reference data is delayed by one clock to pull in the synchronization. FIG. 3 is a block diagram showing the configuration of a conventional sync pull-in circuit. In the conventional synchronous pull-in circuit shown in FIG. 3, the clock signal 101A input to the clock input terminal 101 is input to the gate circuit 2.

A clock control signal 200A from a clock control terminal 200 is inputted to the other input end of the gate circuit 7, and this clock control signal 20 is supplied.
Assuming that 0A is not gated by the gate circuit 2, the gate circuit 2 outputs the clock signal 10
The clock signal 21 is input to the counter circuit circuit 3 as an output signal of the gate circuit 2 through 1A.

The counter circuit circuit 3 generates an address designation signal 31 by the input clock signal 21 and outputs it to the storage circuit 4. The memory circuit 4 uses this addressing signal 3
The reference data 41 is sequentially read from the address designated by 1.

The reference data 41 is input to the comparison circuit 7,
It is compared with the received data 102 from the received data input terminal 102. The comparison result 71 of the comparison circuit 7 is counted by the error counter circuit 10, and the count value 105A is output from the error number output terminal 105.

When the count value 105A of the error counter circuit 10 is equal to or larger than a certain error, it is determined that the synchronization is not established, and the clock control signal 200A for stopping the clock is input to the gate circuit 2 for controlling the clock signal 21. .

The clock control signal 200A is applied to the gate circuit 2
, The clock signal 21 is stopped, which delays the generation of the reference data 41 with respect to the received data 102A. By repeating this operation until the received data 102A and the reference data 41 match, synchronization is pulled in.

[0009]

In the conventional synchronization pull-in circuit, since the reference data is delayed by one clock to match the received data 102A, the longer the data length, the longer the synchronization takes.

[0010]

In order to solve the above problems, a synchronous pull-in circuit according to the present invention comprises a memory circuit 4 for storing reference data and generating a holding pulse of a periodic pattern, and an address designation in the synchronous pull-in mode. The reference data and the holding pulse are output from the memory circuit 4 at the addition address of the signal and the phase difference set value, and the phase difference difference between the reference data and the reception data measured in the synchronous pull-in mode is output in the error measurement mode. An adder circuit 1 for sequentially reading reference data from a memory circuit 4 at an addition address with the address designation signal, and a holding means 6 for holding the received data by the holding pulse in the synchronous pull-in mode.
A comparator circuit 7 for comparing the reference data with the received data in the synchronous pull-in mode and the error measurement mode; and a comparator circuit 7 for starting counting by the holding pulse in the synchronous pull-in mode to make the reference When the coincidence between the data and the received data is detected, the counting is stopped to count the deviation of the phase difference between the reference data and the received data, and in the error measurement mode, the reference data and the reception by the comparison circuit 7 are received. An error counter circuit 10 that counts the result of comparison with the data as an error in the code of the data string of the received data, and the holding pulse causes the error counter circuit 10 to start counting in the synchronous pull-in mode, and the comparison circuit 7 compares As a result, the counting of the error counter circuit 10 is stopped, Comprising a reset start means for causing the counting of the error of the code to the error counter circuit 10 by comparison with the reference data by the circuit 7 and the reception data.

[0011]

According to the present invention, in the synchronous pull-in mode, the reference data of the memory circuit 4 is read at the same time as the holding data by the addition address obtained by adding the address designation signal and the phase difference setting value by the addition circuit 1. The received data is latched by the latch circuit 6, the error counter circuit 10 starts counting, and when the reference data and the received data match, the count of the error counter circuit 10 is stopped and the phase difference between the reference data and the received data is reached. Error is counted, and in the error measurement mode, the count value of the phase difference error and the address designation signal are added by the adder circuit 1 to calculate the added address, and the reference data is read from the memory circuit 4 at the added address and referred to. The comparison circuit 7 compares the data with the received data, and the error counter circuit 10 counts up the error of the phase difference according to the comparison result. And, we obtain an error count.

Next, an embodiment of a sync pull-in circuit of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of this embodiment. In FIG. 1, the adder circuit 1 is configured so that the phase difference set value 103A and the address designation signal 31 from the counter circuit circuit 3 are input from the phase difference set value input terminal 103.

The adder circuit 3 adds the phase difference set value 103A and the address designation signal 31 and outputs the added address 11 to the storage circuit 4. The storage circuit 4 outputs the reference data 41 to the comparison circuit 7 according to the addition address 11, outputs the holding pulse 42 at the pattern cycle, and outputs the holding pulse 42 to the gate circuit 5. The memory circuit 4 has one more data bit in order to output the hold pulse 42.

The mode switching control input terminal 104 receives a mode switching control signal 104A for switching between synchronous pull-in and error measurement modes, and the mode switching control signal 104A is input to the gate circuit 5 and the 2-to-1 selector 9. It is supposed to be done.

The mode switching control signal 104A is a signal for switching between the synchronous pull-in mode and the error measurement mode, and the mode switching control signal 104 in the error measurement mode.
When A is input to the gate circuit 5, the gate of the gate circuit 5 is closed so that the holding pulse 42 is not input to the latch circuit 6, and in the error measurement mode, the holding pulse 51 output from the gate circuit 5 is SR flipped.・ Flop 8
Is sent to the S terminal and the error counter circuit 10.

When the holding pulse 51 is input from the gate circuit 5 to the latch circuit 6 as a holding means, the latch circuit 6
Holds the reception data 102A, and the output signal 61 (reception data) of the latch circuit 6 is input to the comparison circuit 7.

The comparison circuit 7 compares the reference data 41 and the output signal 61, and when they match, outputs a match signal 71 to the R terminal of the SR flip-flop 8 and the 2-to-1 selector 9. I am trying.

In the error measurement mode, the 2-to-1 selector 9 receives the comparison signal from the comparison circuit 7 by the mode switching control signal 104A.
Output signal, that is, the coincidence signal 71 is selected and the enable signal 91 is output to the error counter circuit 10. The SR flip-flop 8 and the 2: 1 selector 9 serve as reset / start means of the error counter circuit 10.

A clock signal 101A from a clock input terminal 101 is input to the counter circuits 1 and 10. Of these, the counter circuit 1 counts the clock signal 101A and outputs the address designation signal 31, and the error counter circuit 10 is reset when the holding pulse 51 output from the gate circuit 5 is input and is set to 2: 1 in the pull-in mode. The counting of the clock signal 101A is started by the enable signal 91 from the selector 9,
When the comparison circuit 7 detects that the reference data 41 and the output signal 61 of the latch circuit 6 match, the 2-to-1 selector 9
As a result, the error counter circuit 10 outputs from the error count value output terminal 105 as the clock count value 105A corresponding to the phase difference between the received data 102A and the reference data 41.

Next, the operation of this embodiment configured as described above will be described first with reference to the time chart in FIG. 2 from the operation in the synchronous pull-in mode. In the synchronous pull-in mode, the gate circuit 5 is not gated, the 2-to-1 selector 9 is the SR flip-flop 8
The output signal 81 is selected.

At time T1, the phase difference set value 103A shown in FIG. 2 (c) of the phase difference set value input terminal 103 sets the phase difference 0. FIG. 2 output from the counter circuit 3
The addressing signal 31 shown in (b) is "0", and FIG.
The received data 102A shown in (g) is “D4”.

The counter circuit 3 has a clock signal 101A input from the clock input terminal 101 shown in FIG.
Generates an addressing signal 31. The address designation signal 31 is input to the adder circuit 1.

The adder circuit 1 has an addressing signal 31.
"0" and "0" of the phase difference setting value 103A from the phase difference setting value input terminal 103 are added, and the addition address 11 of "0" of the adding circuit 1 is output as shown in FIG. To do. The addition address 11 is input to the memory circuit 4, and the memory circuit 4 changes the data “D0” when the address value is “0” from the memory circuit 4 to the reference data 4 as shown in FIG.
1 is sequentially read. At the same time, the memory circuit 4 generates the holding pulse 42 at the pattern cycle.

At this time, the gate of the gate circuit 5 is opened by the mode switching control signal 104A shown in FIG. 2 (h) from the mode switching control terminal 104, and the holding pulse 42 shown in FIG. 2 (f) passes through the gate 5. Then, the holding pulse 51 shown in FIG. 2I is input to the latch circuit 6, the SR flip-flop 8 and the error counter circuit 10.

With this holding pulse 51, the latch circuit 6 latches and holds the output signal 61 shown in FIG. 2 (j) with "D4" of the received data 102A shown in FIG. 2 (g) as holding data.

Further, the SR flip-flop 8 outputs an output signal 81 in a state in which the error counter circuit 10 is enabled by the holding pulse 51, as shown in FIG. This output signal 81 is the mode switching control signal 104A.
2 through the 2-to-1 selector 9,
It is input to the error counter circuit 10 as an enable signal 91 shown in (m).

After time T1, the error counter circuit 10 counts up the error count value 105A by the clock signal 101A as shown in FIG. 2 (n), and outputs it to the count value output terminal 105.

Next, the operation at time T2 will be described. At this time T2, the reference data 41 shown in FIG. 2 (e) and the output signal 61 of the latch circuit 6 shown in FIG. 2 (J) are compared by the comparison circuit 7, and the output signal 61 becomes the received data 102A.
When the coincidence is detected in “D4” of, the comparison circuit 7
To output a coincidence signal 71 as shown in FIG.

The coincidence signal 71 from the comparison circuit 7 is SR
The SR flip-flop 8 is reset by being applied to the R terminal of the flip-flop 8. This SR flip
The output signal 81 of the flop 8 is the mode switching control signal 1
It is selected by the 2-to-1 selector 9 by 04A and is output to the error counter circuit 10 as the enable signal 91.

The error counter circuit 10 receives the enable signal 9
When 1, the count is stopped. As the phase difference between the received data 102A and the reference data 41 at this time, the number of clocks corresponding to the deviation is the error count value 10 of the error counter circuit 10.
5 A is output to the count value output terminal 105. FIG.
In the case of (n), the error count value 105A is "3".

Next, the operation in the error measurement mode after time T3 will be described. At time T3, the mode switching control signal 104A is switched to the error measurement mode. In this error measurement mode, the gate circuit 5 is in a gate state in which a signal is stopped, the latch circuit 6 is in a state in which the received data 102A passes, and the 2-to-1 selector 9 is in a state in which the coincidence signal 71 of the comparison circuit 7 is selected.

At time T3, at the phase difference setting value input terminal 103, the phase difference setting value 103A is the number of phase difference clocks at the count value output terminal 105, that is, the error count value 1
A value obtained by adding “1” to 05A, in other words, {(error count value 105A) +1} = “4” is input as the phase difference between the reference data 41 and the reception data 102A.

At time T3, the output of the counter circuit 3, that is, "8" of the address designation signal 31 and "4" of the phase difference set value 103A are added by the adder circuit 1, and the addition address 11 of the addition result is It becomes “12” and is output to the memory circuit 4. In the memory circuit 4, the addition address 11 is "1.
The data “D12” in the case of “2” is read as reference data 41 and output to the comparison circuit 7.

Further, the mode switching control signal 104A is input to the gate circuit 5 and the 2-to-1 selector 9, and the mode switching control signal 104A is input to the gate circuit 5, whereby the holding pulse 42 from the memory circuit 4 is changed. In the non-holding state, that is, the gate of the gate circuit 5 is closed, and the holding pulse 42 is not input to the latch circuit 6.

Therefore, the latch circuit 6 receives the received data 1
It passes through “D12” of 02A and is input to the comparison circuit 7. In the comparison circuit 7, “D1 of the received data 102A is displayed.
The data "2" and the data "D12" of the reference data 41 are compared. The comparison result of the comparison circuit 7, that is, the coincidence signal 71 is output to the SR flip-flop 8 and the 2: 1 selector 9.

The mode switching control signal 104A is input to the 2-to-1 selector 9, the 2-to-1 selector 9 selects the coincidence signal 71 by the mode-switching control signal 104A, and the enable signal 91 is output from the 2-to-1 selector 9. It is output to the error counter circuit 10.

The error counter circuit 10 counts the clock signal 101A by the enable signal 91 and outputs the error count value 105A to the count value output terminal 105. Next, at time T4, it is assumed that an error occurs in the data “D17” of the reception data 102A shown in FIG. 2 (e).

The latch circuit 6 passes erroneous data "D17" of the received data 102A. The output signal 61 of the latch circuit 6, that is, the data “D17” is compared with the data “D17” of the reference data 41 by the comparison circuit 7.

The coincidence signal 71 output as the comparison result of the comparison circuit 7 is in a state in which an error is detected, and this erroneous coincidence signal 71 passes through the 2-to-1 selector 9 and the output signal ( It is input to the error counter circuit 10 as an enable signal 91).

The error counter circuit 10 receives this signal and counts. In the example of FIG. 2 (n), the error count value 105A of the error counter circuit 10 is counted up from "3" to "4" in the phase difference clock number in the synchronous pull-in mode. Since the phase difference clock number "3" is known, the error count value is 4-3 = 1.

[0041]

In the synchronous pull-in circuit according to the present invention, in the synchronous pull-in mode, the holding pulse of the reference data and the pattern period is generated from the storage circuit by the addition address obtained by adding the address designation signal and the phase difference setting value, and the holding pulse is used. The received data is held in the latch circuit and at the same time the error counter circuit starts counting, and when the reference data and the received data match, the error counter circuit stops counting and the error difference of the phase difference between the reference data and the received data is measured. Get the number. In the error measurement mode, the reference data is read according to the addition result of the phase difference clock of the error count value in the synchronous pull-in mode and the address designation signal in the error measurement mode, and is counted up from the phase difference clock in the synchronous pull-in mode. Since the error count value is obtained in this manner, the phase difference between the received data and the reference data can be delayed in a lump, and the synchronization pull-in can be performed at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a configuration of an embodiment of a synchronization pull-in circuit according to the present invention.

FIG. 2 is a time chart for explaining the operation of the embodiment of FIG.

FIG. 3 is a block diagram showing a configuration of a conventional sync pull-in circuit.

[Explanation of symbols]

 1 adder circuit 3 counter circuit 4 memory circuit 5 gate circuit 6 latch circuit 7 comparison circuit 8 SR flip-flop 9 2 to 1 selector 10 error counter circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H04L 7/00 H04L 7/00 Z

Claims (2)

[Claims] 1. A storage circuit (4) for storing reference data and generating a holding pulse of a periodic pattern, and a storage circuit (4) for adding an address specifying signal and a phase difference set value in the synchronous pull-in mode. The storage circuit (4) outputs the reference data and the holding pulse, and in the error measurement mode, the addition amount of the shift amount of the phase difference between the reference data and the reception data measured in the synchronous pull-in mode and the address designation signal. An adder circuit (1) for sequentially reading reference data from, holding means (6) for holding the received data by the holding pulse in the synchronous pull-in mode, and the reference data in the synchronous pull-in mode and the error measurement mode A comparison circuit (7) for comparing with the received data, and starts counting by the holding pulse in the synchronous pull-in mode. The comparison circuit (7) stops counting when a match between the reference data and the received data is detected, counts a shift amount of the phase difference between the reference data and the received data, and, in the error measurement mode, Comparison circuit
An error counter circuit (10) for counting the comparison result of the reference data and the received data according to (7) as an error in the code of the data string of the received data, and the error counter circuit (10) due to the holding pulse in the synchronous pull-in mode. 10) is started, and the error counter circuit (10) is determined by the comparison result of the comparison circuit (7).
Resetting that causes the error counter circuit (10) to count the error of the code according to the comparison result of the reference data and the received data by the comparison circuit (7) in the error measurement mode. A synchronization pull-in circuit comprising start means. 2. The synchronous pull-in circuit according to claim 1, wherein the reset / start means uses the holding pulse to generate the error counter circuit (10) in the synchronous pull-in mode.
And an SR flip-flop (8) for outputting an output signal for enabling the error counter circuit (10) to stop counting when the comparison circuit (7) detects a match, and the synchronous pull-in. In the mode, the output of the SR flip-flop (8) causes the error counter circuit (10) to start and stop counting, and in the error measurement mode, the comparison circuit (7) causes the error counter circuit (10) to A synchronous pull-in circuit comprising a 2-to-1 selector (9) for counting the comparison result as the number of errors.