JPH0926931A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To use one semiconductor integrated circuit as plural bus adapters by providing bus interface circuits corresponding to the plural kinds of buses and an interface circuit selection means. SOLUTION: For instance, an interface selection circuit 2 is set so as to select and connect the bus interface circuit A1a to a primary side data bus 5 and the bus interface circuit C1c to a secondary side data bus 6 at the time of assembly. An external connection circuit 11 connects the primary side data bus 5 and the buses 7a and 8a corresponding to interface selection signals 3. Also, the secondary side data bus 6 and the buses 7c and 8c are connected. An internal bus connection circuit 12 connects the bus 9a and the bus 10c and connects the bus 10a and the bus 9c corresponding to the interface selection signals 4. Thus, a bus interface on a primary side is converted to a secondary side bus interface through the internal bus connection circuit 12 and data are outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit for a bus adapter.

[0002]

2. Description of the Related Art A conventional semiconductor integrated circuit for a bus adapter is, for example, a DECchip 21050 issued by DEC.
Some are as described in the PCI-to-PCI Bridge data sheet. FIG. 13 is a block diagram of a conventional semiconductor integrated circuit. The primary side data bus control device 101 sends a request from the primary side data bus 5 when a bus operation request is issued from the primary side data bus 5. While receiving it, the bus operation to the secondary side data bus 6 is started. When there is a bus operation request from the secondary side data bus 6, the secondary side data bus control device 102 starts the bus operation to the primary side data bus 5 while receiving the request from the secondary side data bus 6. . The data path 103 to the primary side is a data bus for receiving data from the secondary side data bus 6 and driving the data to the primary side data bus 5. Data bus 1 to the primary side
03 is used when a store request comes from the secondary data bus 6 or when a fetch request comes from the primary data bus 5. The data path 104 to the secondary side receives data from the primary side data bus 5 and the secondary side data bus 6
Is a data path for driving data. The data path 104 to the secondary side is used when a store request comes from the primary side data bus 5 or when a fetch request comes from the secondary side data bus 6. Configuration register 105
Although the internal configuration of is not particularly shown, it is a control logic related thereto. The arbiter 106 arbitrates the secondary data bus 6.

When there is a data transmission request from the primary data bus 5, the primary data bus control device 101 controls the request. The primary side data bus control device 101 enables the data path 104 to the secondary side to receive the data from the primary side data bus 5 through the bus interface, and makes the primary side data path 103.
It is prohibited to send data to the primary side data bus 5.
The primary side data bus control device 101 informs the secondary side data bus control device 102 that a data transmission request has been issued from the primary side data bus 5.
Disables data reception of data sent from the secondary data bus 6 via the bus interface to the data path 103 to the primary side, and the secondary data bus 6 to the data path 104 to the secondary side. It enables data transmission via the bus interface. That is, the transfer data is sent to the secondary side data bus 6 through the data path 104 from the primary side data bus 5 to the secondary side.

As described above, the conventional semiconductor integrated circuit has two bus interface circuits of one type or two types, and the two bus interface circuits are fixedly connected by the bus interface connection circuit. Therefore, 2
When there is a request to connect the secondary data bus 6 to a different bus, it is necessary to separately prepare a bus adapter having a different bus interface.

[0005]

As described above, when the conventional semiconductor integrated circuit has a plurality of bus interface circuits, two bus interfaces used as input and output are fixedly connected to the external connection module. Was there. For this reason, if one of the multiple bus interfaces is to be connected to another bus having a different protocol or electrical condition, a separate bus adapter must be developed, and therefore adapter development and test pattern generation are required. There was a problem that the cost required for designing and manufacturing such as this would be high.

The present invention has been made to solve the above-mentioned problems, and one semiconductor integrated circuit can be used as a plurality of bus adapters, and the design cost and manufacturing cost are reduced, and the flexibility is high. It is an object of the present invention to provide a semiconductor integrated circuit.

[0007]

A semiconductor integrated circuit according to a first aspect of the present invention comprises a bus interface circuit corresponding to a plurality of types of buses, an interface circuit selecting means for selecting a plurality of types of bus interface circuits, and an interface. Bus connecting means for connecting the bus interface circuits selected by the circuit selecting means, and external connecting means for connecting the bus interface circuit selected by the interface circuit selecting means to a peripheral circuit outside the semiconductor integrated circuit. By being provided, it operates as a bus adapter between different types of bus interfaces.

A second aspect of the present invention is the semiconductor integrated circuit according to the first aspect, wherein the interface circuit selecting means is controlled by an external input signal from an external pin of the semiconductor integrated circuit.

A third aspect of the present invention is the semiconductor integrated circuit according to the first aspect, wherein the interface circuit selecting means comprises a register, and control for selecting the interface circuit is performed by an output signal of the register. .

According to a fourth aspect of the invention, in the semiconductor integrated circuit according to the third aspect, the semiconductor integrated circuit comprises a set of scan circuits consisting of a scan input pin, a scan output pin, a scan clock and a scan path, and rewriting of a register is performed by the scan circuit. It was something that I was supposed to do.

A fifth aspect of the invention is the semiconductor integrated circuit according to the third aspect of the invention, in which an input bus for controlling interface circuit selecting means control data and an address bus for designating a register into which the interface circuit selecting means control data is fetched. Also, by providing the decoder of the address bus, rewriting of the control data for the register is performed by the bus access method.

A sixth aspect of the present invention is the semiconductor integrated circuit according to the first aspect, further comprising bus interface circuit driving means whose output is controlled by the interface circuit selecting means, the bus interface circuit driving means being constituted by the interface circuit selecting means. Only the selected bus interface circuit is drive-controlled.

A seventh aspect of the present invention is the semiconductor integrated circuit according to the first aspect, wherein the external connection means includes an input buffer and an output buffer for each of the primary and secondary external interfaces of the semiconductor integrated circuit. Secondary and 2
The secondary side external interface and the bus interface circuit are connected via the input buffer and the output buffer.

An eighth aspect of the present invention is the semiconductor integrated circuit according to the first aspect, wherein the external connection means is provided with a parity check circuit for the primary side and secondary side external interfaces, and the primary check is performed via the parity check circuit. The external interface on the secondary side and the external interface on the secondary side are connected to the bus interface circuit.

A ninth aspect of the invention is the semiconductor integrated circuit of the first aspect, wherein the bus interface circuit comprises a set of scan input pins, scan output pins, scan clocks, and scan paths connected to each bus interface circuit. The bus interface circuit is connected to form a scan path under the control of the interface circuit selecting means.

[0016]

The semiconductor integrated circuit according to the present invention includes a plurality of bus interface circuits, and the interface selection circuit selects the bus interface circuits corresponding to the primary side data bus and the secondary side data bus, respectively.
The primary side bus interface is converted into a secondary side bus interface via an internal bus connection circuit and data is output.

The semiconductor integrated circuit according to the present invention is
The bus interface selection circuit is operated by a control signal input from an external pin.

The semiconductor integrated circuit according to the present invention is
The bus interface selection circuit is controlled by the output signal of the internal register.

The semiconductor integrated circuit according to the present invention is
The bus interface selection circuit is controlled based on the control information in the shift register set by the scan input from the outside of the semiconductor integrated circuit.

The semiconductor integrated circuit according to the present invention is
The bus interface selection circuit is controlled based on control information in a register set by a bus access method from the outside of the semiconductor integrated circuit.

The semiconductor integrated circuit according to the present invention is
Of the plurality of bus interface circuits in the semiconductor integrated circuit, the clock is provided only to the bus interface circuit selected by the bus interface selection circuit to execute the interface conversion process.

The semiconductor integrated circuit according to the present invention is
An external connection circuit forming a semiconductor integrated circuit is provided with an input / output buffer for buffer control, and a buffer-controlled data path is connected to a bus interface circuit controlled by an interface selection circuit for bus interface conversion.

The semiconductor integrated circuit according to the present invention is
By providing a parity check circuit in the external connection circuit that constitutes the semiconductor integrated circuit, the parity check is performed during the bus interface conversion in the semiconductor integrated circuit.

Further, in the semiconductor integrated circuit according to the present invention, a scan path is formed in the bus interface circuit, the scan path of the bus interface circuit selected by the interface selection circuit is selected, and a set of scan input pin and scan output pin is set. By connecting to, the operation of the bus interface circuit is verified.

[0025]

【Example】

Embodiment 1 FIG. A first embodiment of the present invention will be described with reference to FIG. FIG. 1 shows the configuration of a semiconductor integrated circuit having three different types of bus interface circuits 1a, 1b, and 1c. Bus interface circuit 1
a, 1b, 1c are buses 7a, 7b, 7c, 8 respectively
It is connected to the external connection circuit 11 by a, 8b, and 8c. Also, buses 9a, 9b, 9c, and 10a, 10
It is connected to the internal bus connection circuit 12 by b and 10c. The external connection circuit 11 uses the interface selection signal 3
The three bus interface circuits 1a, 1b, 1
Any one of c is connected to the primary side data bus 5 and the secondary side data bus 6. The internal bus connection circuit 12 is connected to one of the three bus interface circuits 1a, 1b, 1c by the interface selection signal 4. The interface selection circuit 2 uses a PROM (programmable read-only memory) to select which of the bus interface circuits 1a, 1b, 1c should be selected in advance when incorporated.
Alternatively, the interface selection signals 3 and 4 are created by writing them in an EPROM (erasable PROM) or the like.

Next, the operation will be described. Here, for example, the interface selection circuit 2 includes a bus interface circuit Ala on the primary side data bus 5 when installed.
It is assumed that the bus interface circuit C1c is selected and connected to the secondary data bus 6.
The external connection circuit 11 connects the primary side data bus 5 and the buses 7a and 8a in accordance with the interface selection signal 3.
Further, the secondary side data bus 6 and the buses 7c and 8c are connected. The internal bus connection circuit 12 receives the bus 9a, the bus 10c, and the bus 10a according to the interface selection signal 4.
And the bus 9c are connected.

When a data fetch request comes from the primary data bus side, the operation is as follows. The external connection circuit 11 connects the primary side data bus 5 and the bus interface circuit A1a by the interface selection signal 3. Control of data fetch on the primary side is controlled by the bus interface circuit A1a. When the bus interface circuit A1a recognizes the data fetch request, it issues the data fetch request to the internal bus connection circuit 12 via the bus 10a. In the internal bus connection circuit 12,
The interface selection signal 4 recognizes that the secondary bus interface circuit is the bus interface circuit C1c, and therefore issues a data fetch request to the bus interface circuit C1c via the bus 9c. The bus interface circuit C1c receives this and issues a data fetch request via the bus 8c. The external connection circuit 11 recognizes from the interface selection signal 3 that the bus interface circuit C1c is connected to the secondary side data bus 6, so that the fetch request from the bus 8c is transmitted to the secondary side data bus 6. To publish. When the fetch data for the fetch request is sent from the secondary side data bus 6, the fetch data is sent to the secondary side data bus 6 and the external connection circuit 1.
1, the bus 7c, the bus interface circuit C1c, and the bus 10c, the internal bus connection circuit 12, the bus 9a, the bus interface circuit A1a, the bus 8a, and the external connection circuit 11 to send the data to the primary data bus 5.

When a data store request comes from the primary data bus side, the operation is as follows. The external connection circuit 11 connects the primary side data bus 5 and the bus interface circuit A1a by the interface selection signal 3. The control of the data store on the primary side is controlled by the bus interface circuit A1a. When the bus interface circuit A1a recognizes the data store request,
A data store request is issued to the internal bus connection circuit 12 via the bus 10a. The internal bus connection circuit 12 recognizes from the interface selection signal 4 that the bus interface circuit on the secondary side is the bus interface circuit C1c. Therefore, a data store request is issued to the bus interface circuit C1c via the bus 9c. To issue. In response to this, the bus interface circuit C1c issues a data store request using the bus 8c. The external connection circuit 11 receives the interface selection signal 3
The secondary side data bus 6 has a bus interface circuit C1.
Since it recognizes that c is connected, bus 8c
Issues a request from the secondary side data bus 6.
The store data corresponding to the store request includes the request between each circuit, the primary side data bus 5, the external connection circuit 11,
Bus 7a, bus interface circuit A1a, bus 10
a, via the internal bus connection circuit 12, the bus 9c, the bus interface circuit C1c, the bus 8c, the external connection circuit 1
It is sent to the secondary side data bus 6 via 1.

When a data fetch request comes from the secondary data bus, the operation is as follows. The external connection circuit 11 connects the secondary data bus 6 and the bus interface circuit C1c by the interface selection signal 3. The control of the data fetch on the secondary side is controlled by the bus interface circuit C1c. When the bus interface circuit C1c recognizes the data fetch request, it issues the data fetch request to the internal bus connection circuit 12 via the bus 10c. In the internal bus connection circuit 12, the primary side bus interface circuit is changed to the bus interface circuit A1 by the interface selection signal 4.
Since it has been recognized as a, a data fetch request is issued to the bus interface circuit A1a using the bus 9a. The bus interface circuit A1a receives the request and issues a data fetch request via the bus 8a. The external connection circuit 11 recognizes from the interface selection signal 3 that the bus interface circuit A1a is connected to the primary-side data bus 5, so that the request from the bus 8a is transmitted to the primary-side data bus 5.
Issue to The fetch data for the fetch request is
When the fetch data is sent from the primary side data bus 5, the fetch data is sent to the primary side data bus 5, the external connection circuit 11 and the bus 7.
a, the bus interface circuit A1a, the bus 10a, and the internal bus connection circuit 12, and then to the secondary data bus 6 via the bus 9c, the bus interface circuit C1c, the bus 8c, and the external connection circuit 11.

When a data store request comes from the secondary data bus 6, the operation is as follows. The external connection circuit 11 connects the secondary data bus 6 and the bus interface circuit C1c by the interface selection signal 3. The control of the data store on the secondary side is controlled by the bus interface circuit C1c. When the bus interface circuit C1c recognizes the data store request,
A data store request is issued to the internal bus connection circuit 12 by the bus 10c. The internal bus connection circuit 12 recognizes from the interface selection signal 4 that the primary-side bus interface circuit is the bus interface circuit A1a. Therefore, a data store request is issued to the bus interface circuit A1a via the bus 9a. To issue. The bus interface circuit A1a receives this and issues a data store request using the bus 8a. The external connection circuit 11 receives the interface selection signal 3
The primary side data bus 5 has a bus interface circuit A1
Since it recognizes that a is connected, the bus 8a
Issues a request from the primary side data bus 5.
The store data for the store request includes the request between the circuits, the secondary side data bus 6, the external connection circuit 11,
Bus 7c, bus interface circuit C1c, bus 10
c, the internal bus connection circuit 12, the bus 9a, the bus interface circuit A1a, the bus 8a, and the external connection circuit 11 to the primary data bus 5.

According to the semiconductor integrated circuit of this embodiment, the bus adapter circuit can be appropriately selected according to the external bus interface, so that it is possible to flexibly cope with different types of interfaces.

Embodiment 2 FIG. A second embodiment of the present invention will be described with reference to FIGS. 2, 3 and 4. FIG. 2 is a configuration diagram of a semiconductor integrated circuit according to the second embodiment of the present invention, which is almost the same as the configuration of the semiconductor integrated circuit of the first embodiment. However, the present embodiment is different in that a level input signal 201 is provided to the interface selection circuit 2 via an external pin in order to control which of the bus interface circuits 1a, 1b, 1c is selected from the outside. There is. Here, the external input signal 201 is a level signal pulled up to 0V or 5V. In addition, an external input signal 20 is provided inside the interface selection circuit 2.
An interface selection signal control circuit 202 for controlling the interface selection signals 3 and 4 by 1 is provided. Here, the external input signal 201 is a 4-bit signal line and controls the interface selection signals 3 and 4.

FIG. 3 is an internal block diagram of the interface selection circuit 2 in this embodiment. 3 and 4 are the interface selection signals already shown in FIG. 2, 202 is the interface selection signal control circuit, and the external input signal 201
To generate interface selection signals 3 and 4. FIG. 4 shows which bus interface circuit the interface selection signal control circuit 202 selects with respect to the set value of the external input signal 201.

Here, the bus interface circuit A1a is provided for the primary side bus interface, and the bus interface circuit B1 is provided for the secondary side bus interface.
A case will be described in which b is selected from outside the semiconductor integrated circuit, respectively. External input signal 201
Is given a 4-bit signal value 0001. External input signal 2
When the 4-bit signal value of 01 is 0001, the interface selection signal control circuit 202 outputs the interface selection signals 3 and 4 respectively to the bus interface circuit A1.
Control is performed so as to select a and B1b. Therefore, the external connection circuit 11 connects the primary side data bus 5 to the buses 7a and 8a, and connects the secondary side data bus 6 to the buses 7b and 8b. The internal connection circuit 12 connects the bus 9a and the bus 10b to each other.
The bus 10a and the bus 9b are connected. Next, the bus interface on the primary side has a bus interface circuit A1a.
However, a case where the bus interface circuit C1c is selected from the outside of the semiconductor integrated circuit as the bus interface on the secondary side will be described.
A 4-bit signal value 0010 is given to the external input signal 201. The 4-bit signal value of the external input signal 201 is 0010.
At this time, the interface selection signal control circuit 202 controls so that the interface selection signals 3 and 4 select the bus interface circuits A1a and C1c. Therefore, the external connection circuit 11 includes the primary side data bus 5 and the bus 7
a and 8a are connected, and the secondary side data bus 6 and buses 7c and 8 are connected.
Connect c. The internal connection circuit 12 connects the buses 9a and 10c and the buses 10a and 9c. Then, 1
The bus interface circuit B1b is selected for the secondary side bus interface, and the bus interface circuit C1c is selected for the secondary side bus interface.
Described below is the case of setting each from outside the semiconductor integrated circuit. 4-bit signal value 01 for external input signal 201
Give 10 When the 4-bit signal value of the external input signal 201 is 0110, the interface selection signal control circuit 202 controls the interface selection signals 3 and 4 to select the bus interface circuits B1b and C1c. Therefore, the external connection circuit 11 is connected to the primary side data bus 5
And the buses 7b and 8b are connected, and the secondary data bus 6 is connected to the buses 7c and 8c. Further, the internal connection circuit 12 is the bus 9
b and the bus 10c, and the bus 10b and the bus 9c are connected.

According to this embodiment, since the interface selection circuit is controlled by the external input signal via the external pin of the semiconductor integrated circuit, the interface circuit switching process can be easily performed.

Embodiment 3 FIG. A third embodiment of the present invention will be described based on FIG. FIG. 5 is a configuration diagram of the semiconductor integrated circuit in the third embodiment, which is almost the same as the configuration diagrams shown in the first and second embodiments. However, in this embodiment, the control of the bus interface selection circuit 2 is controlled by the output signal 302 of the register 301 separately provided as shown in FIG.
The difference is that it is done by. For example, as shown in FIG.
The bus interface circuit corresponding to the input value is selected when the value as shown by is set. The output signal 302 of the register 301 is connected to the input of the interface selection circuit 2,
The primary-side and secondary-side bus interface circuits are designated by setting a value corresponding to the bus interface circuit to be selected. In this way, the register 30
The output signal 302 of 1 controls the interface selection circuit 2.

According to the present embodiment, the semiconductor integrated circuit controls the bus interface corresponding to the register set value based on the register set value, so that the interface can be flexibly selected.

Embodiment 4 FIG. A fourth embodiment of the present invention will be described based on FIG. FIG. 6 is a diagram showing a configuration of a semiconductor integrated circuit in the case where a register is rewritten by scanning in the fourth embodiment. Shift register 40
Reference numeral 1 is a shift register that shifts the 1-bit input signal 403 to the 1-bit output signal 404 side by the scan clock input signal 402. By setting a value corresponding to the bus interface circuit to be selected in this register 401, the interface selection circuit 2
Control. Next, when a shift register is used to control the interface selection circuit 2, the operation in the case of rewriting the register by scanning will be described. For example, the shift register is a 4-bit shift register, and the primary side data bus 5 is the bus interface circuit A1a and the secondary side data bus 6 is the bus interface circuit C1c according to the correspondence between the input value and the bus interface circuit selection in FIG. Suppose you want to connect to. In this case, according to the scan clock input 402, 2
The bus interface circuit A1a and the bus interface circuit C1c are connected to the primary side data bus 5 and the secondary side data bus 6 by serially inputting the binary data "0010" to the input signal 403 and setting the value in the shift register.

According to the present embodiment, since the control register of the interface selection circuit is rewritten by bit serial input, even if the bus adapter circuit becomes complicated due to the increase in the types of bus interfaces, the number of external pins is relatively increased without increasing. It can be handled with a simple circuit. Further, the interface selection circuit can be operated by the cold start method.

Embodiment 5 FIG. A fifth embodiment of the present invention will be described with reference to FIGS. 7 and 8. FIG. 7 shows Example 5.
FIG. 9 is a diagram showing a configuration in the case where the rewriting of the register in FIG. In the figure, 504 is an address decoder for performing address decoding based on address data on the address bus 503, and 502 is a register for fetching data on the data bus 505 based on the decoding result of the address decoder 504. Next, the operation will be described. The address decoder 504 controls the input control signal 501 of the register 502 according to the value of the address bus 503, and controls the fetching of data on the data bus 505. This address decoder 504
Determines a part of the space accessible to the system, and sets the value indicated by the register 502 therein.
That is, the address of the system space assigned to the register 502 is loaded on the address bus 503, and the value for the bus interface circuit to be selected is loaded on the data bus 505. When an address corresponding to the system space assigned to this register appears on the address bus 503, the address decoder 504 enables the data on the input data bus 505 to be written to the register 502.

Here, for example, according to the correspondence between the input value and the bus interface circuit selection in FIG. 4, the primary side data bus 5
Is connected to the bus interface circuit A1a, and the secondary data bus 6 is connected to the bus interface circuit C1c. The address of the system space of the register 502 is hexadecimal x'2000 ', and 4 bits of the register 502 are connected to 4 bits of the LSB side of the data bus 505. Both the address bus and the data bus are 16-bit wide buses. Suppose FIG. 8 is a timing chart showing bus access by rewriting the register in this embodiment. When x'2000 'is output to the address bus 503 (T2), hexadecimal x'to the data bus 505.
^{*** Put} 2 '( ^* : don't care). T1
When the address is other than x'2000 'as in the case, the input of the register 502 is invalid and the register 502 is not rewritten. In this way, the address decoder 5
The input of the register 502 is controlled by 04, and the data bus 50
The set value is placed in 5, and the register 502 is rewritten. However, in FIG. 8, the initial value of the register 502 is assumed to be hexadecimal data x'F '.

According to this embodiment, the control register of the interface selection circuit is controlled by the bus access method, and a part of the system space address is allocated to the control register of the interface selection circuit. The effect is that the installed system resources can be shared.

Embodiment 6 FIG. FIG. 9 shows the sixth embodiment of the present invention.
It will be described based on. This embodiment is almost the same as the configuration diagram of the semiconductor integrated circuit shown in the first embodiment, but as shown in FIG. 9, a clock input signal 601 from a clock pin is input.
And the clock driver 6 controlled by the interface selection signal 606 from the interface selection circuit 2.
02 is provided, and the bus interface circuits 1a, 1b, and 1c are connected to the dedicated clock signals 603, 604, and 605 output from the clock driver 602, respectively. The clock driver 602 connects the clock input signal 601 to only the clock signal of the bus interface circuit selected by the signal 606 of the interface selection circuit 2 and supplies the clock signal.

Here, the interface selection circuit 2 is set to 1
A case will be described in which the bus interface circuit A1a is set as the secondary bus interface and the bus interface circuit B1b is selected as the secondary bus interface. The clock driver 602 receives the clock signal 603 according to the interface selection signal 606.
And 604 are respectively connected to the clock input signal 601 from the clock pin, and are not connected to the clock signal 605. As a result, the bus interface circuits A1a and B1
Although the clock is supplied to b to start the operation, the bus interface circuit C1c does not operate because the clock is not supplied.

Next, the interface selection circuit 2 switches the bus interface circuit A to the primary side bus interface.
1a will be described when the secondary side bus interface is set to select the bus interface circuit C1c. The clock driver 602 receives the clock signal 603 according to the interface selection signal 606.
And 605 are respectively connected to the clock input signal 601 from the clock pin and are not connected to the clock signal 604. As a result, the bus interface circuits A1a and C1
Although the clock is supplied to c to start the operation, the bus interface circuit B1b does not operate because the clock is not supplied.

Next, the interface selection circuit 2 changes the bus interface circuit B to the primary side bus interface.
1b will be described when the secondary side bus interface is set to select the bus interface circuit C1c. The clock driver 602 follows the interface selection signal 606 to generate a clock signal 604,
Each of 605 is connected to the clock input signal 601 from the clock pin and is not connected to the clock signal 603.
As a result, a clock is supplied to the bus interface circuits B1b and C1c to start operation, but the bus interface circuit A1a does not operate because a clock is not supplied.

According to this embodiment, the clock is supplied only to the selected bus interface circuit to operate it, while the clock is not supplied to the unused bus interface circuit. There is an effect that wasteful power consumption can be prevented.

Embodiment 7 FIG. FIG. 10 shows a seventh embodiment of the present invention.
It will be described based on. FIG. 10 shows the configuration of the external connection circuit 11 in the present embodiment. The external connection circuit 11 has a primary side input buffer 711, a primary side output buffer 712, a secondary side input buffer 721 and a secondary side. Four side output buffers 722 are provided. Also,
Buses 7a, 7b, 7c are provided in the primary side input signal selection circuit 713.
To connect the primary side output signal selection circuit 714 to the bus 8a,
8b and 8c are connected. On the other hand, the buses 7a, 7b and 7c are connected to the secondary side input signal selection circuit 723, and the buses 8a, 8b and 8c are connected to the secondary side output signal selection circuit 724.
Primary-side input buffer 711 and primary-side input signal selection circuit 7
13 is connected by the primary side input signal 715,
Primary-side output buffer 712 and primary-side output signal selection circuit 7
14 are connected by the primary side output signal 716. The secondary input buffer 721 and the secondary input signal selection circuit 723 are connected by the secondary input signal 725, and the secondary output buffer 722 and the secondary output signal selection circuit 724 are connected.
Are connected by a secondary output signal 726.

In the primary side input signal selection circuit 713,
Any one of the input signals 7a, 7b, 7c of the three types of bus interface circuits 1a, 1b, 1c is selected according to the interface selection signal 3 and connected to the primary side input buffer 711. In the primary side output signal selection circuit 714, one of the output signals 8a, 8b, 8c of the three types of bus interface circuits 1a, 1b, 1c is selected in accordance with the interface selection signal 3, and the primary It is connected to the side output buffer 712. In the secondary side input signal selection circuit 723, any one of the input signals 7a, 7b, 7c of the three types of bus interface circuits 1a, 1b, 1c is selected in accordance with the interface selection signal 3, and the secondary side input signal is selected. Connect to the buffer 721. In the secondary side output signal selection circuit 724, 3
Any one of the output signals 8a, 8b, 8c of the bus interface circuits 1a, 1b, 1c of the type is selected according to the interface selection signal 3 and connected to the secondary side output buffer 722.

Next, the operation will be described. Since the outline of the entire operation is as described in the first embodiment, the operation of the external connection circuit 11 will be described here. However,
It is assumed that the bus interface circuit A1a is selected as the primary side bus interface and the bus interface circuit C1c is selected as the secondary side bus interface.

First, a case where a data fetch request is generated from the primary side and the primary side output buffer 712 is used but the secondary side input buffer 721 is not used will be described. The fetch request from the primary side data bus 5 is transmitted to the selected bus interface circuit A1a via the primary side input signal selection circuit 713. Then, from the bus interface circuit C1c selected as the secondary side bus interface circuit, the secondary side output signal selection circuit 7
After 24, a fetch request is issued to the secondary side data bus 6. Then, the fetch data is transferred from the secondary data bus 6 to the bus interface circuit C1c via the secondary input signal selection circuit 723 without being buffered in the secondary input buffer 721. Then, it is transferred to the bus interface circuit A1a which is the primary side bus interface circuit and is transferred to the primary side output signal selection circuit 7
It is buffered in the primary side output buffer 712 via 14. Then, when the primary side data bus 5 is ready for data transfer, fetch data is driven from the primary side output buffer 712 to the primary side data bus 5.

Next, a case where a data fetch request is generated from the primary side data bus 5 and the primary side output buffer 712 and the secondary side input buffer 721 are used will be described. 1
The fetch request from the secondary data bus 5 is transmitted to the selected bus interface circuit A1a via the primary input signal selection circuit 713. Then, the fetch request is output from the bus interface circuit C1c selected as the secondary bus interface circuit to the secondary data bus 6 via the secondary output signal selection circuit 724. Then, the fetched data is buffered from the secondary side data bus 6 to the secondary side input buffer 721 and transferred to the bus interface circuit C1c via the secondary side input signal selection circuit 723. Then, the data is transferred to the bus interface circuit A1a, which is the primary side bus interface circuit, and the primary side output signal selection circuit 714 is supplied.
And is buffered in the primary side output buffer 712. Then, when the primary side data bus 5 is ready for data transfer, fetch data is driven from the primary side output buffer 712 to the primary side data bus 5.

Next, a case where two fetch requests are successively generated from the primary side data bus 5 and the primary side output buffer 712 and the secondary side input buffer 721 are used will be described. The fetch request from the primary side data bus 5 is transmitted to the selected bus interface circuit A1a via the primary side input signal selection circuit 713. Then, the fetch request is output from the bus interface circuit C1c selected as the secondary bus interface circuit to the secondary data bus 6 via the secondary output signal selection circuit 724. At this time, the second fetch request is transmitted from the primary side data bus 5 to the bus interface circuit A1a via the primary side input signal selection circuit 713. Then, the fetch data for the first fetch request is buffered from the secondary data bus 6 to the secondary input buffer 721. After that, it is transferred to the bus interface circuit C1c via the secondary side input signal selection circuit 723. Then, it is transferred to the bus interface circuit A1a and is buffered in the primary output buffer 712 via the primary output signal selection circuit 714. This time,
The second fetch request is output to the secondary data bus 6 through the same bus as the first fetch request. The fetch data for the second fetch request is buffered in the secondary side input buffer 721. When the primary side data bus 5 is ready for data transfer,
The fetch data corresponding to the first fetch request from the primary output buffer 712 is driven to the primary data bus 5. After that, the fetch data for the second fetch request buffered in the secondary input buffer 721 is transferred to the primary output buffer 712 in the same manner as the fetch data for the first fetch request, and the primary data is transferred. 1 when the bus 5 is ready for data transfer
The fetch data corresponding to the second fetch request from the secondary output buffer 712 is driven to the primary data bus 5.

Next, a fetch request and a store request are successively generated from the primary side data bus 5, and the primary side input buffer 711, the primary side output buffer 712, the secondary side input buffer 721, and the secondary side. A case where four buffers of the side output buffer 722 are used will be described. The fetch request from the primary side data bus 5 is transmitted to the selected bus interface circuit A1a via the primary side input signal selection circuit 713. Then, the fetch request is output from the bus interface circuit C1c selected as the secondary bus interface circuit to the secondary data bus 6 via the secondary output signal selection circuit 724.
At this time, when a new store request is generated from the primary side data bus 5, the request is the primary side input signal selection circuit 713.
And is transmitted to the bus interface circuit A1a. Then, the store data is the primary side input buffer 711.
Buffered. The fetch data for the fetch request is buffered from the secondary data bus 6 to the secondary input buffer 721. Then, through the secondary side input signal selection circuit 723, the bus interface circuit C
1c is transferred. Then, it is transferred to the bus interface circuit A1a and is buffered in the primary output buffer 712 via the primary output signal selection circuit 714. After the fetched data of the store data is buffered in the primary side output buffer 712, it passes through the primary side input signal selection circuit 713 and then the bus interface circuit A1.
a. Then, it is transferred to the secondary side bus interface circuit C1c and is transferred to the secondary side output signal selection circuit 72.
4 and transferred to the secondary output buffer 722. 1
The fetch data buffered in the secondary output buffer 712 is fetched from the primary output buffer 712 in response to the fetch request when the primary data bus 5 becomes ready for data transfer. Drive to. The store data buffered in the secondary output buffer 722 is stored in the secondary data bus 6
Is ready to transfer data, the secondary output buffer 722 drives the secondary data bus 6.

Next, a case where a data store request is generated from the primary side and the primary side input buffer 711 is used but the secondary side output buffer 722 is not used will be described. The store request from the primary side data bus 5 is transmitted to the selected bus interface circuit A1a via the primary side input signal selection circuit 713. The store data is buffered from the primary side data bus 5 to the primary side input buffer 711. Then, the bus interface circuit C selected as the secondary side bus interface circuit
From 1c, a store request is issued to the secondary side data bus 6 via the secondary side output signal selection circuit 724. Then, the store data is transferred to the bus interface circuit A1a via the primary side input signal selection circuit 713. Further, the data is transferred to the bus interface circuit C1c, passes through the secondary-side output signal selection circuit 724, and then passes through the secondary-side output buffer 722.
Secondary data bus 6 without buffering
Driven to.

Next, a data store request is issued from the primary side, and the primary side input buffer 711 and the secondary side output buffer 7
The case of using 22 will be described. The store request from the primary side data bus 5 is sent to the primary side input signal selection circuit 71.
Bus interface circuit A selected via 3
1a is transmitted. The store data is buffered from the primary side data bus 5 to the primary side input buffer 711. Then, from the bus interface circuit C1c selected as the secondary side bus interface circuit,
A store request is issued to the secondary side data bus 6 via the secondary side output signal selection circuit 724. Then, the store data is transferred to the bus interface circuit A1a via the primary side input signal selection circuit 713. Further, the data is transferred to the bus interface circuit C1c and is buffered in the secondary output buffer 722 via the secondary output signal selection circuit 724. Then, when the secondary side data bus 6 becomes ready for data transfer, the secondary side output buffer 722
Drive the store data to the secondary side data bus 6.

Next, two store requests are continuously generated from the primary side data bus 5, and the primary side input buffer 711 is generated.
A case where the secondary output buffer 722 is used will be described. The first store request from the primary side data bus 5 is transmitted to the selected bus interface circuit A1a via the primary side input signal selection circuit 713.
The first store data is the primary data bus 5
From the primary side input buffer 711. Then, from the bus interface circuit C1c selected as the secondary side bus interface circuit,
The first store request is issued to the secondary side data bus 6 via the secondary side output signal selection circuit 724. Then, the first store data passes through the primary side input signal selection circuit 713,
It is transferred to the bus interface circuit A1a. Further, through the bus interface circuit C1c, the secondary output signal selection circuit 724, the secondary output buffer 7
Buffered to 22. At this time, the second store request is generated from the primary side data bus 5. The second store request is transmitted to the bus interface circuit A1a via the primary side input signal selection circuit 711. Then, the second store data is buffered in the primary side input buffer 711. The first store data is driven from the secondary output buffer 722 to the secondary data bus 6 when the secondary data bus 6 is ready for data transfer. After that, the second store request is issued from the bus interface circuit C1c selected as the secondary bus interface circuit to the secondary output signal selection circuit 724.
Then, it is issued as a second store request to the secondary side data bus 6. Then, the second store data is transferred to the bus interface circuit C1c, passed through the secondary output signal selection circuit 724, and buffered in the secondary output buffer 722. The second store data buffered in the secondary output buffer 722 is driven from the secondary output buffer 722 to the secondary data bus 6 when the secondary data bus 6 becomes ready for data transfer. To be done.

Finally, a store request and a fetch request are successively generated from the primary side data bus 5, and the primary side input buffer 711, the primary side output buffer 712, the secondary side input buffer 721, and the secondary side. A case where four buffers of the side output buffer 722 are used will be described. The store request from the primary side data bus 5 is transmitted to the selected bus interface circuit A1a via the primary side input signal selection circuit 713. The store data is buffered from the primary side data bus 5 to the primary side input buffer 711. Then, a store request is issued from the bus interface circuit C1c selected as the secondary side bus interface circuit to the secondary side data bus 6 via the secondary side output signal selection circuit 724. Then, the store data is transferred to the bus interface circuit A1a via the primary side input signal selection circuit 713. Further, the data is transferred to the bus interface circuit C1c and is buffered in the secondary output buffer 722 via the secondary output signal selection circuit 724. At this time, a fetch request is generated from the primary side data bus 5. The fetch request is transmitted to the bus interface circuit A1a via the primary side signal selection circuit 711. Store data is stored in the secondary output buffer 7 when the secondary data bus 6 is ready for data transfer.
Driven from 22 to the secondary data bus 6. After that, the fetch request is sent to the bus interface circuit C1c selected as the secondary side bus interface circuit.
Then, a fetch request is issued to the secondary side data bus 6 via the secondary side output signal selection circuit 724. The fetch data corresponding to the fetch request is buffered in the secondary side input buffer 721. After that, it is transferred to the bus interface circuit C1c via the secondary side input signal selection circuit 723. Then, it is transferred to the bus interface circuit A1a and is buffered in the primary output buffer 712 via the primary output signal selection circuit 714. When the primary side data bus 5 is ready for data transfer, 1
The fetch data corresponding to the fetch request from the secondary output buffer 712 is driven to the primary data bus 5.

Similar to the operation for the request from the primary side data bus 5, the operation for the request from the secondary side data bus 6 is performed.

According to the present embodiment, the input / output buffer is conventionally provided for each bus interface, but the external connection circuit is provided with the input / output buffer all at once, so that the logic circuit is compact. Therefore, the cost can be reduced.

Embodiment 8 FIG. An eighth embodiment of the present invention will be described based on FIG. FIG. 11 shows the configuration of the external connection circuit 11 in this embodiment. The external connection circuit 11 includes a primary side Paris check circuit 811 and a secondary side parity check circuit 821. The buses 7a, 7b and 7c are connected to the primary side input signal selection circuit 713, and the buses 8a, 8b and 8c are connected to the primary side output signal selection circuit 714. On the other hand, the bus 7 is connected to the secondary side input signal selection circuit 723.
a, 7b, 7c, and the secondary side output signal selection circuit 724
The buses 8a, 8b and 8c are connected to. The primary side parity check circuit 811 and the primary side input signal selection circuit 713 are set to 1
The secondary side input signal 715 is connected, and the secondary side parity check circuit 821 and the secondary side input signal selection circuit 723 are connected by the secondary side input signal 725.

In the primary side input signal selection circuit 713,
Any one of the input signals 7a, 7b, 7c of the three types of bus interface circuits 1a, 1b, 1c is selected according to the interface selection signal 3 and connected to the primary side parity check circuit 811. Further, in the primary side output signal selection circuit 714, output signals 8a, 8 which are output signals of three types of bus interface circuits 1a, 1b, 1c.
Any one of b and 8c is selected according to the interface selection signal 3. On the other hand, in the secondary side input signal selection circuit 723, three types of bus interface circuits 1
Any one of 7a, 7b and 7c which are input signals a, 1b and 1c is selected according to the interface selection signal 3 and connected to the secondary side parity check circuit 821. Further, the secondary side output signal selection circuit 724 selects any one of the output signals 8a, 8b, 8c of the three types of bus interface circuits 1a, 1b, 1c according to the interface selection signal 3.

Next, the operation will be described. Since the overall operation is as described in the first embodiment, the operation of the external connection circuit will be described here. However, the bus interface circuit A1 is used as the primary-side bus interface.
It is assumed that a is selected and the bus interface circuit C1c is selected as the secondary side bus interface.

First, the case where a fetch request is issued from the primary side data bus 5 will be described. Primary side data bus 5
From the primary side input signal selection circuit 713.
Selected bus interface circuit A1
a. Then, from the bus interface circuit C1c selected as the secondary side bus interface circuit, through the secondary side output signal selection circuit 724, 2
A fetch request is issued to the secondary data bus 6. And
Fetch data and data parity are secondary data bus 6
Is input to the secondary side parity check circuit 821.
A parity check is performed in the secondary side parity check circuit 821, and if there is no error, it is transferred to the bus interface circuit C1c via the secondary side input signal selection circuit 723. Then, the data is transferred to the bus interface circuit A1a, which is the primary-side bus interface circuit, and
Primary side data bus 5 via secondary side output signal selection circuit 714
Fetch data and data parity are driven to.

Next, a case where a store request is issued from the primary side data bus 5 will be described. Primary side data bus 5
Store request from the bus interface circuit A1a selected through the primary side input signal selection circuit 713.
Is transmitted to Store data and data parity is 1
Secondary data bus 5 to primary parity check circuit 81
1 is input. A parity check is performed by the primary side parity check circuit 811. If there is no error in the parity check, the store request is output to the secondary data bus 6 from the bus interface circuit C1c selected as the secondary bus interface circuit via the secondary output signal selection circuit 724. It Then, the store data is transferred to the bus interface circuit A1a via the primary side input signal selection circuit 713. Further, it is transferred to the bus interface circuit C1c and is driven to the secondary side data bus 6 via the secondary side output signal selection circuit 724.

The operation of the external connection circuit 11 in response to the request from the secondary side data bus 6 is the same as the operation of the external connection circuit 11 in response to the request from the primary side. Further, in the above description, the example in which the parity check is performed when the data is input from the semiconductor integrated circuit has been described, but the parity check may be performed when the data is output.

According to this embodiment, the parity check circuit conventionally provided for each bus interface is now collectively provided in the external connection circuit.
The logic circuit can be configured compactly and the cost can be reduced.

Example 9. FIG. 12 shows the ninth embodiment of the present invention.
It will be described based on. In the figure, 1a, 1b and 1c are bus interface circuits, 2 is an interface selection circuit, 901 is a scan input terminal, 902 is a scan output terminal, 903, 904 and 905 are selectors for selecting a path of a scan path, 906 and 907, Reference numeral 908 is a control signal for controlling the selectors 903, 904, and 905, respectively. Also, 909, 910, 911, 912, 91
3, 914 are signal lines connecting the scan paths inside the respective bus interface circuits, and 915a, 915.
b and 915c are the bus interface circuit 1 respectively
The latches are connected to the scan paths forming a, 1b, and 1c. The scan clock is not shown.

Next, the operation will be described. When the interface selection circuit 2 is incorporated, for example, the bus interface circuit A1a is added to the primary side bus interface 2
It is assumed that the secondary bus interface is set to select the bus interface circuit C1c.

The selector 903 controls the signal line 910 under the control of the control signal 906 from the interface selection circuit 2.
The selector 904 selects the signal line 911 by the control of the control signal 907, and the selector 905 selects the signal line 914 by the control of the control signal 908. As a result, a scan path connected from the scan input terminal 901 to the scan output terminal 902 through the latches 915a and 915c connected to the scan paths inside the bus interface circuit A1a and the bus interface circuit C1c is realized.

When the bus interface circuit A1a is selected as the primary bus interface and the bus interface circuit B1b is selected as the secondary bus interface, or the bus interface circuit B1b is used as the primary bus interface and the bus interface circuit is used as the secondary bus interface. Even when C1c is selected, by controlling the selectors 903, 904, and 905 in the same manner as described above, the latch 915a connected to the scan path inside the bus interface circuit A1a and the bus interface circuit B1b from the scan input terminal 901, respectively.
And 915b, the latch 91 connected from the scan input terminal 901 to the scan path inside the bus interface circuit B1b and the bus interface circuit C1c.
A scan path connected to the scan output terminal 902 through 5b and 915c is realized.

According to this embodiment, by connecting the scan input terminal, the scan output terminal, and the scan path in each bus interface circuit through the selector controlled by the control signal from the interface selection circuit,
Realizes a scan path for the bus interface circuit without adding signal pins outside the semiconductor integrated circuit,
This can be used to verify the operation of the bus interface circuit.

[0073]

According to the semiconductor integrated circuit of the present invention, the bus adapter circuit can be appropriately selected according to the external bus interface, so that it is possible to flexibly cope with different types of interfaces. There is.

According to the semiconductor integrated circuit of the present invention,
Since the interface selection circuit is controlled by the external input signal via the external pin of the semiconductor integrated circuit,
There is an effect that the switching process of the interface circuit can be easily performed.

According to the semiconductor integrated circuit of the present invention,
The semiconductor integrated circuit selects and controls the bus interface corresponding to the register set value based on the register set value, so that the interface can be flexibly selected.

Further, according to the semiconductor integrated circuit of the present invention, the control register of the interface selection circuit is rewritten by bit serial input, so that the number of external pins can be reduced even if the bus adapter circuit becomes complicated due to the increase in bus interface types. There is an effect that a relatively simple circuit can be used without increasing the number and the interface selection circuit can be operated by the cold start method.

According to the semiconductor integrated circuit of the present invention,
Since the control register of the interface selection circuit is controlled by the bus access method and a part of the system space address is assigned to the control register of the interface selection circuit, the system resource in which the semiconductor integrated circuit is mounted can be shared. effective.

According to the semiconductor integrated circuit of the present invention,
Since the clock is supplied to only the selected bus interface circuit to operate it and the clock is not supplied to the unused bus interface circuit, the semiconductor integrated circuit is operated without wasting power. The effect is that you can.

In the semiconductor integrated circuit of the present invention, the input / output buffer is provided for each bus interface, but the external connection circuit is provided with the input / output buffer all at once. There is an effect that the structure can be made compact and the cost can be reduced.

Further, in the semiconductor integrated circuit of the present invention, the parity check circuit is provided for each bus interface, and the external connection circuit is provided together, so that the logic circuit is compactly constructed. Therefore, there is an effect that the cost can be reduced.

In addition, according to the semiconductor integrated circuit of the present invention, the scan input terminal, the scan output terminal, and the scan path in each bus interface circuit are connected via the selector controlled by the control signal from the interface selection circuit. By doing so, it is possible to realize a scan path for the bus interface circuit without adding a signal pin to the outside of the semiconductor integrated circuit, and use this to verify the operation of the bus interface circuit.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing a second embodiment of the present invention.

FIG. 3 is a configuration diagram showing an interface selection circuit according to a second embodiment of the present invention.

FIG. 4 is a diagram showing an external input signal and contents of a bus interface selection table set in a register for explaining a bus interface selection operation in the second, third, fourth, and fifth embodiments.

FIG. 5 is a configuration diagram showing a third embodiment of the present invention.

FIG. 6 is a configuration diagram showing a fourth embodiment of the present invention.

FIG. 7 is a configuration diagram showing a fifth embodiment of the present invention.

FIG. 8 is a diagram showing the timing of register rewriting in the fifth embodiment of the present invention.

FIG. 9 is a configuration diagram showing a sixth embodiment of the present invention.

FIG. 10 is a configuration diagram showing a seventh embodiment of the present invention.

FIG. 11 is a configuration diagram showing an eighth embodiment of the present invention.

FIG. 12 is a configuration diagram showing a ninth embodiment of the present invention.

FIG. 13 is a diagram showing a configuration of a conventional semiconductor integrated circuit.

[Explanation of symbols]

1a, bus interface circuit A, 1b bus interface circuit B, 1c bus interface circuit C, 2 interface selection circuit, 3, 4 interface selection signal, 5 primary side data bus, 6 secondary side data bus, 7a, 7b, 7c , 8a, 8b, 8c, 9
a, 9b, 9c, 10a, 10b, 10c bus, 11
External connection circuit, 12 Internal bus connection circuit, 201 External input signal, 202 Interface selection signal control circuit, 301 Register for controlling selection means, 302
Register output signal for controlling selection means, 401 Shift register for controlling selection means, 402 scan clock input signal, 403 scan input signal, 404
Scan output signal, 510 register input control signal, 5
02 register for controlling selection means by bus access,
503 address bus, 504 address decoder, 5
05 data bus, 506 system clock, 601
Clock input signal, 602 Clock driver, 60
3 clock signals, 604 clock signals, 605 clock signals, 606 interface selection signals, 71
1 primary side input buffer, 712 primary side output buffer, 713 primary side input signal selection circuit, 714 primary side output signal selection circuit, 715 primary side input signal, 716 1
Secondary output signal, 721 Secondary input buffer, 722
Secondary side output buffer, 723 Secondary side input signal selection circuit, 724 Secondary side output signal selection circuit, 725 Secondary side input signal, 726 Secondary side output signal, 811 Primary side parity check circuit, 821 Secondary side Parity check circuit, 901 scan input terminal, 902 scan output terminal, 903, 904, 905 selector, 906,
907, 908 control signals to control, 909, 910,
911, 912, 913, 914 signal lines, 915a,
915b, 915c Latch.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroyuki Iida 5-1-1, Ofuna, Kamakura-shi Mitsubishi Electric Co., Ltd. Information Systems Research Institute (72) Seiji Seki 5-1-1, Ofuna, Kamakura-shi Mitsubishi Electric Corporation Company Information Systems Laboratory

Claims (9)

[Claims] 1. A semiconductor integrated circuit for a bus adapter for connecting a plurality of types of buses, wherein the semiconductor integrated circuit selects a bus interface circuit corresponding to the plurality of types of buses and the plurality of types of bus interface circuits. Interface circuit selecting means, bus connecting means for connecting the bus interface circuits selected by the interface circuit selecting means, and the bus interface circuit selected by the interface circuit selecting means to the periphery of the semiconductor integrated circuit. A semiconductor integrated circuit, comprising: external connection means for connecting to a circuit so that the circuit operates as a bus adapter between different types of bus interfaces. 2. The semiconductor integrated circuit according to claim 1, wherein the interface circuit selecting means is controlled by an external input signal from an external pin of the semiconductor integrated circuit. 3. The interface circuit selecting means comprises a register inside the semiconductor integrated circuit, and control for selecting the interface circuit is performed by an output signal of the register. Semiconductor integrated circuit. 4. A set of scan circuits comprising scan input pins, scan output pins, scan clocks and scan paths, wherein the rewriting of the register is performed by the scan circuits. Semiconductor integrated circuit. 5. The register is provided by including an input bus for the interface circuit selecting means control data, an address bus for designating a register into which the interface circuit selecting means control data is taken in, and a decoder for the address bus. 4. The semiconductor integrated circuit according to claim 3, wherein the control data is rewritten by the bus access method. 6. A bus interface circuit driving means output controlled by the interface circuit selecting means is provided, and the bus interface circuit driving means drives and controls only the bus interface circuit selected by the interface circuit selecting means. The semiconductor integrated circuit according to claim 1, wherein: 7. The external connection means is one of a semiconductor integrated circuit.
An input buffer and an output buffer are provided for each of the secondary side and secondary side external interfaces, and the primary side and secondary side external interfaces and the bus interface circuit are connected through the input buffer and the output buffer. The semiconductor integrated circuit according to claim 1, which is characterized in that. 8. The external connection means comprises a parity check circuit for the primary side and secondary side external interfaces, and a primary side and secondary side external interface and a bus interface circuit via the parity check circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is connected to the semiconductor integrated circuit. 9. The bus interface circuit comprises a set of scan input pins, scan output pins, scan clocks, and a scan path connected to each bus interface circuit, and the bus interface circuit is controlled by the interface circuit selecting means. 2. The semiconductor integrated circuit according to claim 1, wherein the scan paths are connected to form a scan path.