JPH09264935A - Electron beam inspecting apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to shorten the analyzing time of a sample to be tested by obtaining a reference image by calculation based on layout information and test pattern information (vector) of the sample. SOLUTION: First, a tester 4 gives a vector to a semiconductor chip 2, and confirms the right or wrong of its output signal value. When the inspections of all the vectors are finished, the number of the error pin vector is obtained, and sent to a control computer 5B. The computer 5B specified the vicinity of the output terminal detected by the error at a SEM image fetched position, an apparatus itself fetches a SEM image, and sends it to a SEM image storage unit 5A. On the other hand, a logical simulator 5D logically simulates the vector specified by the computer 5B in parallel with the image formation. It obtains a potential distribution of the region part, and sends it to a layout registering/ display unit 5C. The unit 5C generates a reference image in superposition with the layout of it with an object site. Then, a comparator 5E compares the SEM image with the reference image and displays the different image on a monitor 5F.

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. TECHNICAL FIELD OF THE INVENTION Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Embodiments of the Invention (1) Principle (FIG. 1) (2) Configuration of Electron Beam Inspector (FIGS. 2 to 5) ) (3) Other Examples Effects of the Invention

[0002]

TECHNICAL FIELD The present invention relates to an electron beam inspection apparatus. In particular, it is suitable for application to those that measure the state of the voltage applied to the wiring of the integrated circuit formed in the semiconductor chip.

[0003]

2. Description of the Related Art Conventionally, an EBT (Electron Beam Tester) has been known as an apparatus for analyzing a defective portion of a semiconductor chip. This EBT fixes the wiring potential to "H" or "L" by giving a specific inspection pattern signal (hereinafter referred to as a vector) from the tester to the semiconductor chip, and the state of the fixed potential is scanned by an electron beam. S
This is taken out as an EM (Scanning Electron Microscope) image. During the failure analysis, the EBT is used to give the same vector to each of the good product and the defective product to obtain two SEM images, and the defective portions are specified by comparing the two SEM images. It is done like this.

[0004]

By the way, since only one semiconductor chip can be inspected by the EBT at a time, a defective semiconductor chip can be inspected at the time of failure analysis.
It is necessary to provide a step of obtaining an EM image and a step of obtaining an SEM image of a defective semiconductor chip. However, there is a problem that it takes a very long time to replace a semiconductor chip which is a target in such an inspection.

That is, in order to obtain two SEM images, the inside of the chamber is returned to the normal pressure from the vacuum state at the stage when one of the SEM images is obtained, and after the semiconductor chips are exchanged, the inside of the chamber is returned to the vacuum state again. A series of operations are required to execute the operation for acquiring the SEM image, and it takes about 15 minutes to obtain two SEM images at one location.
It took minutes and minutes. However, in general, SE for each good product and defective product that is required for defect analysis
One set of M images (that is, two images) is not necessary, and dozens of sets 1
It was necessary to acquire more than 00 sets of SEM images. As described above, it is a reality that a great deal of labor and time are required to inspect a defective portion of one semiconductor chip.

Besides, the EBT is also used for analyzing defective products based on the difference in operating environment (for example, difference between when the power supply voltage V _CC is 5.0 [V] and 3.0 [V]). In this case, However, only a series of processes for exchanging the semiconductor chip to be inspected is not required, and two types of SEM images under a preferable operating environment and SEM images under an unfavorable operating environment must be acquired. about
Five minutes was needed for one inspection.

The present invention has been made in consideration of the above points, and an object of the present invention is to realize an electron beam inspection apparatus capable of completing inspection in a shorter time than conventional ones.

[0008]

In order to solve such a problem, in the present invention, the distribution of the potential of the sample under test at the time of acquiring the SEM image is obtained by calculating the layout information of the sample under test and the test pattern information. The reference image is generated by superimposing the calculation result on the layout information. By thus obtaining the reference image by calculation, it is not necessary to actually acquire the SEM image of the reference sample to be tested, and the analysis time can be shortened accordingly.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

(1) Principle The electron beam inspection apparatus described in this embodiment is an interface (for example, GPIB) between a tester and a logic simulator.
It should be possible to communicate with each other by connecting via (General Purpose Interface Bus) interface, and there should be a part that is the target of SEM image import based on the contents of the vector given from the tester to the semiconductor chip. It is characterized in that the potential state can be obtained by logic simulation.

The electron beam inspection apparatus is characterized in that the result obtained by the logic simulation is superposed on the layout and a reference image to be compared with the SEM image actually taken in is generated. That is, while the SEM image shown in FIG. 1 (A) is captured by scanning with an electron beam, the potential state at the corresponding position on the layout is obtained by calculation as shown in FIG. 1 (B). It is used as a reference image. In this way, only one type of SEM image is actually taken in at any one time.
It is designed so that EM images need not be captured. By the way, it takes about 3 minutes to obtain one SEM image, so that the processing time is remarkably shortened.

Incidentally, FIG. 1C shows a difference image between the SEM image actually obtained and the reference image. Also, in the figure, the black portion represents the portion where the electric potential is attached to the “H” level, and the white portion represents the portion where the electric potential is attached to the “L” level, which is indicated by the dense diagonal lines. The part marked with represents the part where the potential fluctuates with time and is not constant. In FIG. 1, the three vertically extending black lines correspond. The portion indicated by the rough diagonal lines is the portion where no wiring or the like is provided. Next, a configuration example of an electron beam inspection apparatus using such a principle will be shown.

(2) Configuration of Electron Beam Inspection Apparatus FIG. 2 shows a configuration example of the electron beam inspection apparatus. The electron beam inspection apparatus 1 scans a semiconductor chip 2 as an inspection object while illuminating it with an electron beam, and detects a secondary electron returning from the semiconductor chip 2 to detect an SEM image and a measurement voltage. The semiconductor chip 2 is provided with a tester 4 for inspecting by applying a vector, and a signal processing unit 5 for signal processing the detection result of the apparatus main body 3.

Of these, the apparatus main body 3 has substantially the same configuration as the apparatus generally used at present, and a two-dimensional moving stage 3A for moving the semiconductor chip 2 in a two-dimensional plane.
An electron gun 3B for emitting an electron beam to the semiconductor chip 2 mounted on the two-dimensional moving stage 3A, a scanning deflector 3C for deflecting and scanning the electron beam, an electron lens 3D, and detecting secondary electrons. And a detector 3E that operates. The device body 3 applies the vector input from the tester 4 to the semiconductor chip 2 to fix the potential state of the wiring in the inspection area while the SEM image is captured.
The contents of the vector are given to the signal processing unit 5 via the interface.

On the other hand, the signal processing section 5 includes an SEM image storage section 5A, a control computer 5B for controlling the entire system, a layout registration / display section 5C storing layout information of the semiconductor chip 2, and a logic simulator 5D. And a comparison unit 5E and a monitor 5F. Here, the SEM image storage unit 5A generates an SEM image based on the detection signal input from the device body 3 and stores it in the memory, and also transfers the contents of the vector detected by the device body 3 to the control computer 5B. It is done like this. The SEM image storage unit 5A
Controls the two-dimensional moving stage 3A and the deflector 3C by transferring a control signal given from the control computer 5B to the apparatus main body 3.

The layout registration / display unit 5C reads out the layout of the area part of the registered layout which is the target for taking out the SEM image, and superimposes it on the calculation result of the logic simulator 5D to generate the reference image. Has been done. At this time, the layout registration / display unit 5C is configured to perform coloring processing so that the generated reference image has the same color classification as the SEM image.

The logic simulator 5D is a circuit for simulating the operating state based on the contents of the vector given from the tester 4 with respect to the layout information read out from the layout registration / display section 5C, and is the target of the current SEM image capture. The simulation result (that is, the distribution state of the potential) of the region in which the region is present is given to the layout registration / display unit 5C.

The comparison unit 5E is a SEM image storage unit 5A.
It is a circuit that detects a difference image by comparing the SEM image read from the SEM image with the reference image read from the layout registration / display unit 5C, and outputs the difference image to the monitor 5F together with the SEM image and the reference image. ing. Thus, the monitor 5F is adapted to display three types of images as shown in FIGS. 1 (A), (B) and (C).

A flow of processing at the time of inspection by the electron beam inspection apparatus 1 having the above configuration will be described with reference to FIG.
Here, it is assumed that the layout information of the semiconductor chip 2 to be inspected is already stored in the layout registration / display unit 5C. The process starts from step SP1. Then, in the next step SP2, each input terminal A of the semiconductor chip 2 shown in FIG.
The check signals shown in FIG. 4B, that is, the vectors, are applied to 0 to AN in a time-sequential manner, and whether the values of the signals output from the output terminals D0 to DN are correct values according to the inputs. The confirmation operation is executed.

When the inspection is completed for all the prepared vectors, the processing by the electron beam inspection apparatus 1 shifts to the processing stage of step SP3, and the pin number and the error in which the output which does not match the predetermined output appears. The number of the vector that appears (that is, the pattern number) is calculated. For example, when the input / output relationships do not match at time t in FIG. 4B, the vector number at this time t is obtained. When the pin number and the vector number are obtained in this way, the processing proceeds to steps SP4, SP5 and SP.
6 and the parallel processing given by. At this stage, the information about the pin number and the vector number (that is, the contents of the vector) to be inspected is transmitted from the tester 4 to the control computer 5B side of the signal processing unit 5.

First, the processing of step SP4 will be described.
At this time, the control computer 5B specifies the vicinity of the output terminal where the error is detected as the SEM image capture position, and outputs the drive information of the two-dimensional movement stage 3A to the apparatus body 3 so that the SEM image at the relevant position can be retrieved. When the positioning is completed, the emission of the electron beam and the deflection by the deflector 3C are started, and the SEM image as shown in FIG. 5A is captured from the appearance distribution of the secondary electrons. Incidentally, in this SEM image capturing processing, several to several tens of SEM images are continuously obtained while moving the capturing area little by little as necessary.

On the other hand, in steps SP5 and SP6, in parallel with step SP4, the logic simulation is executed for the vector specified by the control computer 5B to determine what the potential of the area specified by the control computer 5B is. Ask. When the potential of which wiring in the area portion is to be calculated, the layout registration / display unit 5C displays the result on the layout,
The criteria as shown in (B) obtain the image. Also in this case, several to several tens of reference images are continuously obtained while moving the capture area little by little as needed. Since the calculation process for each reference image is completed while the SEM image is being captured, it does not take more time than it takes to capture the SEM image.

As described above, the time required to acquire these SEM images and the reference image may be, for example, 3 [minutes] * 20 [sheets] = 60 [minutes] even when obtaining 20 SEM images.
By the way, as in the conventional case, when switching the vacuum state in the chamber while alternately exchanging good and defective products, the same 20 [SEM] images can be obtained in 15 [min] ×
Since 20 [sheets] = 300 [minutes] were required, the processing time was drastically shortened.

Steps SP4 and SP5 and SP
When the processing of 6 is completed, in step SP7, SE
The comparison processing of the M image and the reference image is executed by the comparison unit 5E, and the difference image is displayed on the monitor 5F.
For example, in the case of the leftmost wiring among the three wirings shown in FIGS. 5A and 5B, when it is at the “L” level even though it is originally at the “H” level, this portion is A difference image will be displayed. Therefore, the operator can specify the location where the error appears by tracing the wiring back to the position where the difference image does not appear.

According to the above construction, the reference image to be compared with the SEM image is obtained by the logic simulation, so that S for each position on the semiconductor chip is obtained.
Only one EM image is required at any time, and the time required for inspection can be shortened. Further, even when it is necessary to compare the SEM image with the reference image at a plurality of locations, the inspection can be performed in a short time because the inspection can be continuously performed with the defective semiconductor chip to be inspected attached at a predetermined position. Not only that, the analysis process can be executed smoothly.

Conventionally, in order to analyze a defective portion of a semiconductor chip in which wirings and circuits are arranged in a complicated manner, it is necessary to have a thorough knowledge of the circuit of the semiconductor chip to be analyzed. In this case, the inspection can be carried out efficiently, so that even a designer, not a designer, can analyze the semiconductor chip. Further, similarly, since the unified inspection result can be obtained regardless of the skill of the analyst, the reliability of the inspection result can be improved as compared with the conventional case.

Furthermore, even if the wiring to be analyzed is located in the deep portion of the semiconductor chip, it is extremely difficult to detect the distribution of the potential even if it is a good semiconductor chip. If this is the case, since the accurate potential distribution state that should be adopted by a non-defective product can be obtained without fail, the reliability of the reference image can be improved and the reliability of the analysis process can be further improved.

(3) Other Embodiments In the above-described embodiment, the electron beam inspection apparatus 1 is exemplified by the operation analysis processing of a defective product whose input / output relationship is different from that of a non-defective product even though the operating environment is the same. Although the flow of the process at the time of the inspection by the above has been described, the same is true for the margin inspection performed by changing the operating environment (for example, the inspection performed by changing the power supply voltage V _CC between 5 [V] and 3 [V]). Can be done. In the case of this margin inspection, an SEM image is obtained for the semiconductor chip 2 set in an operating environment that is worse than the original operating environment, and the SEM image and the reference image under the ideal environment obtained by calculation are obtained. Necessary inspection can be performed by comparison. Even in this case, SE under ideal environment
Since it is not necessary to capture the M image, the analysis process can be executed in a much shorter time.

In the above embodiment, the monitor 5F
The case of displaying not only the SEM image and the reference image but also the difference image thereof has been described above, but the present invention is not limited to this, and can be applied to the case where the difference image is not displayed. In this case, the difference between the SEM image and the reference image will be visually confirmed by the analyst, but the time itself required to capture the SEM image and the reference image is shorter than the conventional one, and therefore shorter than the conventional one. Processing can proceed in time.

[0030]

As described above, according to the present invention, the calculation result obtained by inputting the test pattern information into the layout information of the sample under test and analyzing the reference image to be compared with the SEM image. It is possible to realize the electron beam inspection apparatus in which the analysis of the sample under test can be completed in a shorter time than in the past by superimposing the information on the layout information.

[Brief description of drawings]

FIG. 1 is a schematic diagram for explaining an inspection principle used in an electron beam inspection apparatus according to the present invention.

FIG. 2 is a block diagram showing an example of an electron beam inspection apparatus according to the present invention.

FIG. 3 is a flow chart showing an example of a failure analysis process executed by the electron beam inspection apparatus according to the present invention.

FIG. 4 is a signal waveform diagram showing the relationship between a vector and its output voltage.

FIG. 5 is a schematic diagram showing a relationship between an SEM image obtained for a certain vector and a reference image.

[Explanation of symbols]

1 ... Electron beam inspection device, 2 ... Semiconductor chip, 3 ...
... Device main body, 3A ... Two-dimensional moving stage, 3B ... Electron gun, 3C ... Scan deflector, 3D ... Electronic lens, 3E
...... Detector, 4 …… Tester, 5 …… Signal processing unit, 5A
…… SEM image storage unit, 5B …… Control computer, 5C ……
Layout registration / display section, 5D ... Logic simulator,
5E: Comparison section, 5F: Monitor.

Claims (3)

[Claims] 1. A sample under test is scanned by an electron beam,
By detecting secondary electrons that sequentially appear from the irradiation position of the electron beam, the potential distribution of the sample under test can be determined by S
The time at which the SEM image is acquired based on the SEM image acquisition unit that is extracted as an EM image, the layout information of the sample under test, and the test pattern information applied to the sample under test when the SEM image is acquired. The electron beam inspection apparatus according to claim 1, further comprising: a reference image generation unit that calculates a potential distribution state of the sample under test by calculation and superimposes the calculation result on the layout information to generate a reference image. 2. The electron beam inspection apparatus according to claim 1, wherein the reference image generation unit displays the state of electric potential in the same notation as the SEM image when the reference image is displayed. 3. The SE obtained by the SEM image acquisition unit
The electron beam according to claim 1, further comprising a signal processing unit that obtains a difference between the M image and the reference image generated by the reference image generation unit, and advances the analysis by using the difference as a defective portion. Inspection device.