JP2000088925A - Method and apparatus for specifying fault position of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a time required for specifying a fault position of a defective semiconductor device. SOLUTION: In the case of specifying a fault position of a defective semiconductor device, nodes of a fault candidate existing on a flow of a series of signals are summarized as one path. This path is normally a plurality, but one of the paths is selected, a waveform of the node nearest an output stage is measured. If the waveform of the node is normal, the other node included in the path is judged to be normal. Accordingly, the nodes to be measured for the waveforms can be reduced, and hence a time and a labor for specifying the fault position can be alleviated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for identifying a failure location in a semiconductor device.

[0002]

2. Description of the Related Art When analyzing a failure of a semiconductor device,
It is necessary to specify a failure location of the semiconductor device. As described above, the following three methods have conventionally been mainly used to track the failure origin, which is the failure location.

[0003] (1) EB (electron be
am) Perform image comparison using a tester. Then, the fault location is tracked from the output terminal where the fault is detected, toward the inside of the circuit.

(2) Observe the waveform from the output terminal where the failure of the defective product is detected using an EB tester, a manual prober, or the like. Then, a method of tracing a fault location toward the inside of the circuit while comparing with a waveform of a good product.

(3) As in (2) above, the waveform is observed from the output terminal where the failure of the defective product is detected, using an EB tester, a manual prober or the like. Then, instead of using a normal semiconductor device to obtain a non-defective waveform, a non-defective waveform is obtained from a simulation result.

[0006]

Of these, the above (1) and (2) use a normal semiconductor device for comparison with a defective product, so that a good product and a defective product are alternately replaced. Observation is required, and requires a great deal of labor and time. This is because it is not realistic to prepare data of good products in advance because the data is so large that it is necessary to obtain necessary good data every time a failure is detected. In addition, in the above (1), in order to compare images, it is necessary to match images between non-defective products and defective products.
It requires more time and effort. This is E in human eyes
When checking the images of the B tester, there is a high possibility that the difference between the two images is overlooked. Therefore, such image matching is necessary because the two images are compared using a computer.

In the method (3), it is difficult to predict in advance the path of the signal flow to be tracked, and it is also difficult to prepare only a simulation result of only a necessary portion. For this reason, it is necessary to measure the waveform of each node and carry out a logic simulation of the necessary nodes sequentially to obtain simulation results, or to prepare simulation results of all internal nodes in advance. However, in the method of sequentially performing the necessary logic simulation of the node, it is necessary to perform the logic simulation for each defective waveform, which is a very time-consuming operation. Another problem is that it is difficult for engineers who are not familiar with CAD tools and simulators to use such simulation tools. On the other hand, the method of preparing the logic simulation results of all the internal nodes in advance requires the number of internal nodes to increase with the increase in the scale of the LSI. There is a problem that it is unrealistic.

Further, since the number of failure candidate nodes usually becomes a considerable number, it is impossible to mechanically cover these failure candidate nodes to track / specify a failure location. During tracking / identification work, manual work must be relied on.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and a method and an apparatus for identifying a faulty part of a semiconductor device which can mechanically track or specify a faulty part of a defective semiconductor device to some extent. The purpose is to provide. It is another object of the present invention to improve the effective operation rate of the failure point identification device and to provide a method that can efficiently use an expensive failure point identification device.

[0010]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, a method for specifying a fault location in a semiconductor device according to the present invention is a fault location specifying method for specifying a fault location in a semiconductor device when the fault location exists. There, a failure dictionary obtained when performing a failure simulation, and a test result obtained when testing the semiconductor device using a tester using the same test pattern as when performing this failure simulation, By comparing, the process of obtaining a plurality of fault candidate nodes, and, for the plurality of fault candidate nodes, the fault candidate nodes existing on a series of signal flows are collectively collected as one path,
A step of allocating all of the plurality of failure candidate nodes to one or a plurality of paths, a step of assigning a priority from a node closer to an output stage of the semiconductor device in the path, and a step of sequentially selecting one from the paths. One of the selected paths, measure the waveform of the node with the highest priority from the selected path, compare the measured waveform with the waveform of the logic simulation result obtained in advance, and determine that there is no difference between the two. Excludes all nodes included in this path from failure candidate nodes, and when there is a difference between the two, measures the waveforms in the descending order of the priority of the nodes included in the path. And comparing the waveforms with each other to identify a node in which the difference between them has disappeared, thereby identifying a faulty part.

Further, a method for identifying a failure location of a semiconductor device according to the present invention is a failure location identification method for identifying a failure location when a failure location exists in the semiconductor device. By comparing the obtained fault dictionary with a test result obtained by testing the semiconductor device using a tester using the same test pattern as that used when the fault simulation was performed, a plurality of fault candidate nodes were obtained. And for the plurality of fault candidate nodes, the fault candidate nodes present on a series of signal flows are collected as one path, and all of the plurality of fault candidate nodes are connected to one or a plurality of fault candidate nodes. The process of assigning the paths and assigning priorities to the nodes in the path closer to the output stage of the semiconductor device. And the process that, in order 1 from among the path
One of the selected paths, measure the waveform of the node with the highest priority from the selected path, compare the measured waveform with the waveform of the logic simulation result obtained in advance, and determine that there is no difference between the two. Excludes all the nodes included in this path from the failure candidate nodes, and when there is a difference between the two, measures the waveforms in the descending order of the priority of the nodes included in the path, and converts the measured waveform into a logical waveform. Measuring one or a plurality of input waveforms in a logic gate that outputs the node from which the measurement waveform has been obtained, and from the input waveform, a logic waveform expected as a logic operation of the logic gate;
Comparing the logical waveform of the measured waveform with a logical gate that is different from the measured waveform to specify a faulty portion.

On the other hand, a fault location specifying device for a semiconductor device according to the present invention includes a fault analysis device for measuring a waveform of a node in a semiconductor device, a control computer for controlling the operation of the fault analysis device, and The device for identifying a failure location of a semiconductor device, wherein the control computer, based on the design information of the semiconductor device, the layout of the layout between the control computer and the semiconductor device in the failure analysis device For synchronization, a navigation function processing unit, a logic simulation result storage unit storing results of the logic simulation, and a plurality of semiconductor device test results obtained by testing the semiconductor device. Regarding the failure candidate node, regarding the failure candidate node existing on a series of signal flows A path group information storage unit for storing path information generated by distributing all of the plurality of failure candidate nodes to one or more paths collectively as one path, and measuring by the failure analysis device. A comparison / judgment processing unit for comparing the measured waveform of the node of the semiconductor device with the waveform for the node obtained from the result of the logic simulation, and one path sequentially from the path group information storage unit And the comparison / determination processing unit compares and determines the node having the highest priority from the selected paths. If there is no difference between the two, all nodes included in this path are excluded from the failure candidate nodes. Then, the next path is selected from the path group information storage unit. If there is a difference between the two, the priority order of the nodes included in the path is selected. To measure the waveform in descending order, to the instruction command to the navigation function unit, characterized in that it comprises a next candidate selection processing section.

Further, a fault location specifying device for a semiconductor device according to the present invention includes a fault analyzing device for measuring a waveform of a node in the semiconductor device, a control computer for controlling an operation of the fault analyzing device, and The device for identifying a failure location of a semiconductor device, wherein the control computer, based on the design information of the semiconductor device, the layout of the layout between the control computer and the semiconductor device in the failure analysis device For synchronization, a navigation function processing unit, a logic simulation result storage unit storing results of the logic simulation, and a plurality of semiconductor device test results obtained by testing the semiconductor device. Regarding the failure candidate node, regarding the failure candidate node existing on a series of signal flows A path group information storage unit for storing path information generated by distributing all of the plurality of failure candidate nodes to one or more paths collectively as one path, and measuring by the failure analysis device. A logic waveform conversion unit for converting the measured waveform of the node of the semiconductor device into a logic waveform, a measured waveform of the node of the semiconductor device measured by the failure analysis device, and a node for the node obtained from the logic simulation result storage unit. A comparison / judgment comparing a waveform with the logic waveform of the node of the semiconductor device converted by the logic waveform conversion unit and a logic waveform as an output of a logic gate obtained from the design information; The processing unit and one path are sequentially selected from the path group information storage unit, and the highest priority is selected from the selected paths. The comparison / judgment processing unit compares and determines the next node. If there is no difference between them, all the nodes included in this path are excluded from the failure candidate nodes, and the next path is selected from the path group information storage unit. If there is a difference between the two, the waveforms are measured in the order of the priority of the nodes included in the path, the logical waveform is obtained from the logical waveform conversion unit, and the node that obtained the measured waveform is output as a logic. An input waveform at one or more inputs of the gate is measured, and a logic waveform expected from the logic operation of the logic gate is obtained based on the input waveform, and the expected logic waveform and the logic of the measured waveform are obtained. A next candidate selection processing unit that instructs the navigation function processing unit to compare the waveform with the waveform.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] In a first embodiment of the present invention, in the failure analysis of a semiconductor device, when a failure location is specified, an internal waveform of a defective product is observed to track the failure location. Then, the comparison with the reference waveform is performed. By using the logic simulation result of only the waveform narrowed down as the failure candidate node as the reference waveform at this time, the necessary data amount is reduced, and the necessary data is prepared in advance. In addition, the failure candidate nodes are grouped as one path related to the signal flow as one path, and the waveform of the node closest to the output stage in this path is measured, and this node is normal. In such a case, it is possible to judge that all the other nodes included in the path are normal, and to proceed with the failure analysis to some extent mechanically. One in which the. This will be described in more detail below.

FIG. 1 is a view for explaining a procedure for obtaining a logic simulation result in the present invention, FIG. 2 is a view showing a flowchart for specifying a fault location, and FIG. 3 is related to a first embodiment. It is a figure showing an example of composition of a failure analysis device.

First, a procedure for obtaining a simulation result as a reference waveform in the first embodiment according to the present invention will be described with reference to FIG. 1 by taking as an example a case where a fault candidate is obtained using a fault dictionary. .

As can be seen from FIG. 1, a test vector 12 and a netlist 14 are created based on a CAD system 10 for development and design. The test vector 12 is a so-called test pattern database, and the netlist 14 is a circuit connection information database. The test vector 12 and the netlist 14 are used when finding a failure candidate. The failure simulator 16 generates a failure dictionary 18 based on the netlist 14. That is, the failure simulator 16 performs a failure simulation assuming all kinds of failures, and creates a failure dictionary 18 necessary for limiting failure candidate nodes.

Next, the test vector 12 used for performing the failure simulation by the failure simulator 16 is shown.
ATE (Automatic Test Equi
In step (pment) 20, the semiconductor device is tested. Then, a data log 22 is created based on the test result.
Subsequently, by referring to the failure dictionary 18 and the failure occurrence time in the data log 22, a failure candidate extraction process 24 is performed to obtain a failure candidate 26.

Next, in order to obtain a reference waveform for determining whether or not a waveform obtained from a defective product differs from a non-defective product operation, the test vector 12 and the netlist 14 used in obtaining the failure candidate 26 are used. A logic simulation is performed by the logic simulator 28. that time,
The logic simulation is performed in the failure candidate extraction processing 2
4 is only the node related to the failure candidate 26 extracted and the test vector 12 to be input is the data log 2
The logic simulation is not performed for the test vector after that until the failure occurrence time obtained in step 2. Logic simulation result 3 by this logic simulator 28
Generate 0.

Next, with reference to FIG. 2, a method for tracking / identifying a fault location using the logic simulation result 30 will be described.

First, the connection relation of the nodes of the failure candidate 26 is examined, and the nodes of the related failure candidate 26 are collected for each path (S10). FIG. 4 is a diagram for explaining the grouping for grouping the paths. As can be seen from FIG. 4, the node in the semiconductor device SD and the failure candidate 2
Among the nodes listed in No. 6, nodes existing on a series of signal flows are grouped as a path for each group. At that time, nodes not listed in the failure candidate 26 also
Take in this group and perform grouping. Therefore, in this grouping, one path is formed including the logic gates between the nodes.
In FIG. 4, nodes of the failure candidates listed as the failure candidates 26 are represented by “x”, and nodes not listed as the failure candidates 26 are represented by “○”. In this way, nodes and logic gates in a series of signal flows are combined into one path as much as possible. In FIG. 4, two paths, a path 1 and a path 2, are shown. However, when trying to identify a failure location of an actual semiconductor device, the number of paths becomes much larger.

Next, as can be seen from FIG. 2, in one path, a higher priority is assigned to a node closer to the output stage of the semiconductor device SD (S11). For example, in FIG. 4, in each of the paths 1 and 2, the priorities are assigned in order from the one closest to the output stage, and the node closest to the input stage is assigned the lowest priority in the path. Can be

Next, as can be seen from FIG. 2, one path is selected from a plurality of paths, and a reference waveform of a node having the highest priority among the selected paths is obtained from a logic simulation result 30. Obtain (S12). Subsequently, the waveform of this node is measured from the defective semiconductor device (S13). Then, the waveform of this node obtained from the defective product and the logic simulation result 30
The reference waveform thus obtained is compared with the reference waveform to determine whether there is any difference between them (S14). If there is no difference, it is determined that no failure has occurred in this path, the next path is selected (S15), and the processing from S12 is repeated. That is, all nodes included in this path are determined to be normal, and are excluded from the failure candidates 26. On the other hand, if a difference is recognized, it means that there is a faulty node in this path, and the following processing is performed.

First, a reference waveform of a node having the next highest priority in the same path is obtained from the logic simulation result 30 (S16). Next, the waveform of this node is measured from the defective semiconductor device (S17). Then, the waveform of the defective product is compared with the waveform obtained from the logic simulation result 30 to check whether there is any difference between them (S18). If there is no difference, it can be determined that a failure has occurred between the node whose waveform has been measured here and the node whose waveform has been measured in the previous step. Therefore, the node that is the failure location is specified (S19). On the other hand, if there is no difference, it can be determined that there is a failure point in a node with a lower priority in the same path, so that the above-described S1
The processing from step 6 is repeated.

After the node at the failure point in the path is specified in S19, it is determined whether or not the path is the last path (S20). That is, it is checked whether there is a path that has not been subjected to the processing for specifying the failure location. If it is not the last pass, an untested path is selected (S
15) Repeat the processing of S12 and subsequent steps. If it is the last pass, the processing for tracking / identifying the failure location ends.

Next, an overall analysis flow will be described based on the configuration of the fault location device shown in FIG.

As can be seen from FIG. 3, the fault location specifying device includes a fault analyzing device 40 and a control computer 50. The failure analysis device 40 is controlled by a control computer 50.

The control computer 50 forms layout information based on the design information 51 output from the CAD system 10. Then, the control computer 50 moves the sample stage 42 in the failure analysis device 40 based on the layout information. On this sample stage 42, a semiconductor device SD which is a defective product is mounted. For this reason, the control computer 50 is configured to be controllable by moving the sample stage so that the layout of the semiconductor device SD on the sample stage 42 and the layout information obtained from the design information 51 match. I have. The design information 51 stores, for example, connection information such as node names and circuit information in addition to the layout information. Further, the control computer 50 has a function of associating a node name in the design information 51 with a pattern on the layout of the semiconductor device SD. The function of synchronizing the layout information with the defective semiconductor device SD is realized by the navigation function processing unit 52.

Further, the control computer 50 includes a waveform comparison / judgment processing unit 53 for comparing the waveform obtained from the failure analysis device 40 with the 30 waveforms of the logic simulation result for the node to judge the quality. I have. This waveform comparison /
The waveform data 54 of the semiconductor device SD is input to the determination processing unit 53 via the waveform acquisition processing unit 44 provided in the failure analysis device 40. The waveform comparison / judgment processing unit 53 also receives path group information 55 in which failure candidate nodes are grouped for each path group. further,
The control computer 50 also includes a next candidate selection processing unit 56 that searches for a node to be measured next based on the determination result of the waveform comparison / determination processing unit 53.

The operation of the fault location specifying device when performing an actual analysis is as follows. First, the control computer 50
By operating the navigation function processing unit 52 in
The layout information in the design information 51 and the failure analysis device 40
The position of the semiconductor device SD on the sample stage 42 is set to coincide. Next, an appropriate path is selected from the path group information 55 in which the nodes of the failure candidates 26 are grouped for each path group, and a node having the highest priority among the paths is selected. Then, the position of this node is obtained by the navigation function processing unit 52, the sample stage 42 of the failure analysis device 40 is moved, and the waveform of the selected node in the semiconductor device SD is obtained by the waveform acquisition processing unit 4.
4 to obtain waveform data 54. At the same time, a reference waveform corresponding to the selected node is extracted from the logic simulation result 30, and the measured waveform and the waveform of the logic simulation result are compared and collated by the waveform comparison / judgment processing unit 53 to determine whether they match the simulation result. Determine whether or not. Based on this determination result, the next candidate selection processing unit 56 extracts the node to be measured next according to the flow shown in FIG.
Tracks / specifies the origin of failure. In other words, the next candidate selection processing unit 56 issues an instruction command for the next path or node to be measured to the navigation function processing unit 52, and performs the processing of FIG.

As described above, according to the first embodiment of the present invention, the nodes of the failure candidates 26 are obtained in advance, and the nodes of the failure candidates 26 are grouped as paths for each series of signal flows. Nodes that need to be subjected to logic simulation can be limited in advance, and if the node closest to the output stage in one path is normal, all other nodes included in that path can be determined to be normal, and the fault location can be determined. Can be reduced when specifying the number of nodes. In addition, the time and effort for analysis can be significantly reduced as compared with the conventional method of comparing non-defective products with defective products.

In comparison with the conventional method in which logic simulation results of all nodes are prepared and the logic simulation results are used as reference waveforms, a failure is detected by the tester only for the node in the failure candidate 26. A logic simulation may be performed up to the specified address. Therefore, the simulation time can be shortened, and the simulation result 3
0 file size can be reduced. That is, it is possible to drastically reduce the advance preparation required for specifying the defective portion of the defective product and the time and labor required for specifying the defective portion.

In the conventional technique of performing a logic simulation of a node which is required sequentially, a portion to be measured is often examined / determined on the spot, and a node waveform is measured when an actual fault location is specified. Not only study /
A time for making a determination is also required, and the cost of the failure analysis apparatus is generally occupied including this examination / determination time, thereby reducing the actual operation rate of the failure analysis apparatus. On the other hand, according to the present embodiment, it is possible to prepare in advance the data necessary for the determination as to the location to be measured by the failure location identification device, so that it is necessary to specify the failure location. The analysis can be mechanically advanced to some extent, and the operating rate of the substantial failure analysis device can be improved.

[Second Embodiment] In a second embodiment of the present invention, when an abnormal path in the first embodiment is detected, the logic gates constituting the path are logically arranged in the order closer to the output stage. The fault location is tracked / specified by measuring the output waveform and the input waveform of the gate from the semiconductor device, and calculating the back and forth from these input / output waveforms to search for a logic gate that does not operate normally. . Hereinafter, a method for identifying a failure portion according to the second embodiment of the present invention will be described with reference to FIGS.

FIG. 5 is a diagram showing a flowchart for specifying a fault location in the second embodiment, and FIG. 6 is a diagram showing an example of a configuration of a fault location device according to the second embodiment.

First, a flow for specifying a failure location will be described with reference to FIG. As can be seen from FIG. 5, the connection relation of the nodes included in the failure candidate 26 is checked, and the paths are collected for each related path (S30). That is, FIG.
As can be seen from FIG.
Nodes that are not included in the failure candidates 26 and logic gates between these nodes are all obtained and grouped, and collected as paths.

Next, in one pass, the semiconductor device S
A higher priority is assigned to a node closer to the output stage of D (S31). Subsequently, one path is selected from the plurality of paths, and a reference waveform is obtained from the simulation result 30 for the node having the highest priority among the selected paths (S32). Next, using defective products,
The waveform of the same node is measured (S33). Then, the reference waveform obtained from the simulation result 30 and the waveform of the defective product are compared to determine whether or not they match (S34). If there is no difference between them,
Since it can be considered that no failure has occurred in this path, all other nodes included in this path are excluded from the failure candidates 26, and the next path is selected (S35), and Is repeated. The processing so far is the same processing as in the above-described first embodiment.

On the other hand, if a difference is found between the two, the following processing is performed. First, the waveform measured from the defective node is converted into a logical waveform (S36). Next, from the selected path, the input node (input terminal) of the logic gate whose node is the output node (output terminal) for which the logic waveform has been obtained in S36 is specified, and the input waveform of the node is measured. (S37). For example, when there are two input nodes of this logic gate, these two input waveforms are measured. Next, the measured input waveform is converted into a logical waveform (S38). Subsequently, the logic operation of this logic gate is extracted (S39). That is, what operation the logic gate should correctly perform is acquired. Next, an expected output logic waveform is obtained from the input waveform of the logic gate converted into the logic waveform and the logic operation of the logic gate (S40). That is, an output logic waveform that would have been obtained if this logic gate operated normally is determined. Subsequently, the expected output logic waveform is compared with a logic waveform obtained from a defective product (S41). If they match, it can be determined that there is a failure origin at the preceding stage (input stage side) of the node selected here, so the node with the next highest priority is selected and the waveform of this node is measured ( S42). Then, the processing from S36 is repeated.

On the other hand, if the logic waveforms of the two are different, it means that the operation of the logic gate is not normal, and therefore, it can be determined that this node is the origin of the failure. For this reason, the failure location is specified (S43). Next, it is determined whether or not this path is the last one (S44). If this path is the last path, the processing for specifying the failure location is terminated. If this path is not the last path, another unmeasured path is selected (S35), and the processing from S32 is repeated.

Next, with reference to FIG. 6, an example of the configuration of the fault location specifying device using the method shown in FIG. 5 will be described, and the overall operation will be described. The failure analyzer 40 according to the second embodiment has the same configuration as the failure analyzer 40 according to the above-described first embodiment, and a detailed description thereof will be omitted. Also, in the control computer 60, the same reference numerals are used for the substantially same components as those in the first embodiment.

First, as can be seen from FIG. 6, the failure analysis device 40 is controlled by the control computer 60. CA
The D system 10 outputs the design information 51. The design information 51 also includes layout information. Based on the layout information, the control computer 60 moves the sample stage 42 in the failure analysis device 40, and Semiconductor device SD
Is controlled so as to match the pattern. Then, the control computer 60 associates the node name in the design information 51 with the pattern on the layout of the semiconductor device SD. These processes are performed via the navigation function processing unit 52 in the control computer 60. In addition, the control computer 60 includes a waveform comparison / determination processing unit 53 that compares waveforms to determine pass / fail, and a next candidate selection processing unit 56 that searches for a node to be measured next based on the determination result.

Further, the control computer 6 according to the present embodiment
0 includes a logical operation definition unit 61 for defining the logical operation of the logical gate in the connection information in the design information 51, and a storage device 62 for storing the defined logical operation.
Further, the control computer 60 stores the logical waveform converter 63 for converting the waveform data 54 measured by the failure analyzer 40 into a logical waveform, and the output expected value logical waveform of the logical gate in the logical operation storage device 62. And an expected value logical waveform output processing section 64 for generating the logical value based on the logical operation.
Therefore, the waveform comparison / judgment processing unit 53 compares the measured waveform from the waveform data 54 of the node of the semiconductor device SD with the waveform of the logic simulation result 30, and converts the measured waveform from the logical waveform conversion unit. The logical waveform and the logical waveform from the expected value logical waveform output processing unit 64 are compared.

Next, the operation when the analysis is actually performed using the fault location specifying device will be described. First, the control computer 60
Then, the navigation function processing unit 52 is operated to make the layout information in the design information 51 coincide with the position of the semiconductor device SD on the sample stage 42 in the failure analyzer 40. Next, the nodes in the failure candidate 26 are grouped for each path as in the first embodiment. Then, an appropriate path is selected from the path group information 55 collected for each path, and a node having the highest priority in the path is selected. Subsequently, the position of the node is obtained by the navigation function processing unit 52, and the sample stage 42 of the failure analysis device 40 is moved so that the waveform of the selected node in the semiconductor device SD can be obtained. Then, the waveform acquired from this node is transmitted to the waveform acquisition processing unit 44, and the waveform data 54 is generated. Simultaneously with these operations, a reference waveform corresponding to the selected node is extracted from the logic simulation result 30. Next, the waveform of the logic simulation result 30 for this node and the waveform data 54 are compared and collated by the waveform comparison / determination processing unit 53 to determine whether or not they match. If it is determined from the result of this determination that there is no failure in the measured path, the next path is selected and the above operation is repeated.

On the other hand, if it is determined that the measured path has a failure, the input node of the logic gate that outputs the measured node is obtained from the path group information 55. There may be one input node or a plurality of input nodes depending on the type of the logic gate. Next, the position on the layout of the input node is calculated by the navigation function processing unit 52, and the sample stage 42 in the failure analysis apparatus 40 is moved to a position corresponding to the semiconductor device SD to acquire the waveform data 54.

In the control computer 60, the waveform data 54 as the output node of the logic gate of interest is converted into a logic waveform by the logic waveform conversion processing unit 63. The waveform data 54 as an input node of the logic gate is also converted into a logic waveform by the logic waveform conversion processing unit 63. Based on the logical waveform obtained from the input waveform and the information in the logical operation storage device 62, an expected value waveform output processing unit 64
A more expected value logic waveform is output. The waveform comparison / judgment processing unit 53 compares these expected value logical waveforms with the measured waveforms converted into the logical waveforms. Then, from the determination result, the next candidate selection processing unit 56 extracts the node to be measured next by the flow shown in FIG. 5 described above, and repeats these processes, thereby tracking / identifying the failure origin. Do.
That is, the next candidate selection processing unit 56 issues an instruction command to the navigation function processing unit 52 regarding a path or a node to be measured next, and performs the processing of FIG.

As described above, according to the present embodiment, once a path including a failure can be specified, it is not necessary to refer to the reference waveform in the simulation result 30 for nodes existing in the same path. Thus, it is possible to efficiently perform the analysis for specifying the failure location. That is, the failure location can be tracked / specified only by observing the operation waveform of the defective product, so that the analysis can be performed more efficiently.

The present invention is not limited to the above embodiment, but can be variously modified. For example, in the second embodiment, the logic simulation result 30 is not always necessary and can be omitted. In this case, it is sufficient that the required reference waveform is obtained from the storage device 62 storing the logical operation.

[0048]

As described above, according to the present invention, for a plurality of fault candidate nodes, those existing on a series of signal flows are grouped as one path, and are closest to the output stage of this path. Measures the waveform of the node and, if this node has a normal waveform, determines that all other nodes in this path are also normal, greatly reducing the time required for failure analysis can do.

[Brief description of the drawings]

FIG. 1 is a view for explaining steps required until a logical simulation result is obtained in the first and second embodiments of the present invention.

FIG. 2 is a view showing a flowchart for explaining a method for specifying a failure location according to the first embodiment of the present invention;

FIG. 3 is a diagram showing an example of a configuration of a failure point specifying device according to the first embodiment of the present invention.

FIG. 4 is a view for explaining a process in which failure candidate nodes are put together as paths and priorities are assigned to the failure candidate nodes;

FIG. 5 is a diagram illustrating a flowchart for explaining a method for specifying a failure location according to a second embodiment of the present invention.

FIG. 6 is a diagram illustrating an example of a configuration of a failure point specifying device according to a second embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 10 CAD system 12 Test vector 14 Netlist 16 Failure simulation 18 Failure dictionary 20 ATE 22 Data log 24 Failure candidate extraction processing 26 Failure candidate 28 Logic simulator 30 Logic simulation result 40 Failure analysis device 42 Sample stage 44 Waveform acquisition processing unit 50 Control Computer 51 Design information 52 Navigation function processing unit 53 Waveform comparison / judgment processing unit 54 Waveform data 55 Path group information 56 Next candidate selection processing unit

Claims (6)

[Claims] 1. A failure location identification method for identifying a failure location in a semiconductor device when the failure location exists, comprising: a failure dictionary obtained when a failure simulation is performed; By comparing the test results obtained when testing the semiconductor device using a tester using the same test pattern as described above, a process of obtaining a plurality of fault candidate nodes, and for the plurality of fault candidate nodes, For the failure candidate nodes existing on a series of signal flows, as a single path, distributing all of the plurality of failure candidate nodes to one or a plurality of paths, and the semiconductor device in the path From the node closer to the output stage of step (a), and a step of sequentially selecting one of the paths, and The waveform of the node with the highest priority is measured from the selected path, and the measured waveform is compared with the waveform of the logic simulation result obtained in advance. If there is no difference between the two, the waveform is included in this path. All nodes are excluded from the failure candidate nodes.If there is a difference between the two, the waveform is measured in the order of the priority of the nodes included in the path, and the measured waveform is compared with the waveform of the logic simulation result. A method of specifying a node in which the difference between the two has disappeared to specify a fault location, and a fault location specifying method for a semiconductor device. 2. The fault of a semiconductor device according to claim 1, wherein the logic simulation result is generated from a result of performing a logic simulation up to a time when a fault is detected when a test is performed by a tester. Location identification method. 3. A process for allocating a plurality of fault candidate nodes to paths, wherein the fault candidate nodes, normal nodes existing on a flow of a series of signals not included in the fault candidate nodes, 3. The semiconductor device according to claim 1, wherein all logic gates existing between the nodes are obtained, and the logic gates are included in one path and are rearranged in an order closer to an output stage of the semiconductor device. Failure location identification method. 4. A failure location identification method for identifying a failure location in a semiconductor device when the failure location exists, comprising: a failure dictionary obtained when a failure simulation is performed; and a failure dictionary obtained when the failure simulation is performed. By comparing the test results obtained when testing the semiconductor device using a tester using the same test pattern as described above, a process of obtaining a plurality of fault candidate nodes, and for the plurality of fault candidate nodes, For the failure candidate nodes existing on a series of signal flows, as a single path, distributing all of the plurality of failure candidate nodes to one or a plurality of paths, and the semiconductor device in the path From the node closer to the output stage of step (a), and a step of sequentially selecting one of the paths, and The waveform of the node with the highest priority is measured from the selected path, and the measured waveform is compared with the waveform of the logic simulation result obtained in advance. If there is no difference between the two, the waveform is included in this path. Exclude all nodes from the failure candidate nodes, if there is a difference between them, measure the waveforms in the order of the priority of the nodes included in the path, convert the measured waveforms to logical waveforms, and convert the measured waveforms One or a plurality of input waveforms in a logic gate having the obtained node as an output are measured, and a logic waveform expected as a logic operation of the logic gate from the input waveform is compared with a logic waveform of the measured waveform. A method for specifying a logic gate that is different from the other, thereby specifying a fault location, and a method for specifying a fault location of a semiconductor device. 5. A fault location specifying device for a semiconductor device, comprising: a fault analysis device for measuring a waveform of a node in a semiconductor device; and a control computer for controlling an operation of the fault analysis device. A navigation function processing unit for synchronizing a layout between the control computer and the semiconductor device in the failure analysis apparatus, based on semiconductor device design information; A logic simulation result storage unit storing a result of the simulation, and a plurality of failure candidate nodes obtained from test results of the semiconductor device obtained by testing the semiconductor device, on a series of signal flows. The existing fault candidate nodes are put together as one path, and the plurality of fault candidate nodes are collected. A path group information storage unit for storing path information generated by allocating all of the nodes to one or a plurality of paths, a measured waveform of a node of a semiconductor device measured by the failure analysis apparatus, and the logic simulation A comparison / judgment processing unit for comparing the waveform for the node obtained from the result, and one path is sequentially selected from the path group information storage unit, and priority is selected from among the selected paths. The comparison / determination processing unit compares and determines the highest node, and if there is no difference between them, all nodes included in this path are excluded from the failure candidate nodes, and the next path is stored in the path group information storage unit. If there is a difference between the two, the navigation function is used to measure the waveform in the order of the priority of the nodes included in the path. An instruction command to the processing section, a semiconductor device failure place specifying device, characterized in that it comprises a next candidate selection processing section. 6. A failure location specifying device for a semiconductor device, comprising: a failure analysis device for measuring a waveform of a node in the semiconductor device; and a control computer for controlling an operation of the failure analysis device. A navigation function processing unit for synchronizing a layout between the control computer and the semiconductor device in the failure analysis apparatus, based on semiconductor device design information; A logic simulation result storage unit storing a result of the simulation, and a plurality of failure candidate nodes obtained from test results of the semiconductor device obtained by testing the semiconductor device, on a series of signal flows. The existing fault candidate nodes are put together as one path, and the plurality of fault candidate nodes are collected. A path group information storage unit for storing path information generated by allocating all of the nodes to one or more paths, and converting a measured waveform of a node of the semiconductor device measured by the failure analyzer into a logical waveform. A logic waveform conversion unit to be converted; a measured waveform of the node of the semiconductor device measured by the failure analysis apparatus, and a waveform for the node obtained from the logic simulation result storage unit, and the logic waveform conversion unit A comparison / judgment processing unit for comparing the logic waveform of the node of the semiconductor device converted by the above with a logic waveform as an output of a logic gate obtained from the design information; and a path group information storage unit. One path is sequentially selected, and the comparison / determination processing unit compares and determines the node having the highest priority from among the selected paths. If there is no difference between them, all nodes included in this path are excluded from the failure candidate nodes, and the next path is selected from the path group information storage unit. If there is a difference between both, it is included in that path. Obtaining a logical waveform from the logical waveform conversion unit by measuring the waveform in the order of the priority of the node, measuring the input waveform at one or more inputs of a logic gate that outputs the node that obtained the measured waveform, Based on the input waveform, obtain a logic waveform expected from the logic operation of the logic gate, and in order to compare the expected logic waveform with the logic waveform of the measurement waveform, the navigation function processing unit And a next candidate selection processing unit that issues an instruction instruction.