JPH09261069A - Coder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To confirm quality of data in the case of decoding coded data while coding input data. SOLUTION: A video coding circuit 21 of a video coder 11 encodes input original image data DI1 , and the coded data are outputted from an output as a bit stream DO0 . The coded data outputted from the video coding circuit 21 are stored tentatively in a FIFO memory 22 and read out and decoded by a video decoding circuit 23 and outputted as a video monitor output data DO2 . The video monitor output data DO2 is inputted to a monitor, on which a reproduced image is displayed and while encoding the input original image data DI1 with the video coder 11, the quality of the reproduced image obtained by decoding the coded data is confirmed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a coding device for coding data such as image data and audio data.

[0002]

2. Description of the Related Art Conventionally, image data, image data There is an information compression technique for compressing information such as audio data. The international standard for this information compression technology is MPEG (Moving Pictu).
re Experts Group) standard is widely known. In the present application, MPEG1 and MPEG2 for moving image compression are used.
MP such as MPEG audio for audio and audio compression
All standards standardized by EG are called MPEG standards.

[0003]

By the way, for example, when image data is compressed using an encoding device, the quality and encoding of an image (hereinafter referred to as a reproduced image) obtained by decoding the compressed data. In order to confirm the operation of the device, it is necessary to confirm the reproduced image. To confirm the reproduced image while encoding the input original image data by the encoding device, a method of connecting the decoding device to the outside of the encoding device,
A method of using a local decoding circuit (for example, an inverse quantization circuit and an inverse DCT (Inverse Discrete Cosine Transform) circuit) provided inside the encoding device to create the prediction reference image can be considered.

However, when the decoding device is connected to the outside of the coding device, the system becomes large, and there is a problem that two monitors are required to compare the input original image and the reproduced image. Further, when the input original image and the reproduced image are separately displayed on the two monitors, it is difficult to compare the two images.

Further, when the data generation amount per unit time of the coding device is variable by a device such as a multiplexer (multiplexing device) connected to the subsequent stage of the coding device, the coding device is simply If the decoding device is connected to the output end, there is a problem that the buffer memory in the decoding device overflows or underflows.

On the other hand, when the local decoding circuit inside the encoder is used, there are the following problems. That is,
In the case of an encoding device that adopts the MPEG standard (hereinafter, referred to as an MPEG encoding device), in the MPEG encoding device, the next I picture (within the frame) is preceded by the B picture (bidirectional predictive encoded image). Since a coded image) or a P picture (inter-frame forward prediction coded image) is coded first, the order of coding processing differs from the order of frames of the input original image. Therefore, the image of the output data of the local decoding circuit cannot be viewed as an image as it is because the frame order is exchanged with the input original image, and it is necessary to rearrange the original order by the frame memory. Also, there is a problem that the operation becomes complicated. Also, the local decoding circuit uses variable length coding (VLC).
Since the quantized data before being subjected to the decoding is decoded, there is a problem in that the reproduced image by the complete bit stream subjected to the variable length coding cannot be confirmed depending on the output of the local decoding circuit. .

Further, conventionally, after input original image data is encoded by an encoding device and compressed and then recorded on a storage medium, the data recorded on the storage medium is reproduced and decoded to reproduce a reproduced image. When confirming the quality and the like, a decoding device different from the coding device is used, but in this case as well, there is a problem that the system becomes large.

The present invention has been made in view of the above problems, and a first object thereof is to confirm the quality of data when the encoded data is decoded while the input data is encoded. Provided is an encoding device capable of decoding encoded data without causing overflow or underflow even when the amount of data generated per unit time of the encoding device is variable. Especially.

A second object of the present invention is, in addition to the first object, a comparison between an image based on data obtained by decoding the encoded data and an image based on the input image data while encoding the input image data. An object of the present invention is to provide an encoding device capable of easily performing the above.

A third object of the present invention is, in addition to the above-mentioned first object, of encoding the input data, inputting the encoded data from the outside, and decoding the data. An object of the present invention is to provide an encoding device capable of confirming quality.

[Means for Solving the Problems]

The encoding apparatus of the present invention comprises an encoding means for encoding input data and outputting the encoded data, and a decoding means for decoding the encoded data output from the encoding means and outputting the decoded data. Means, and between the encoding means and the decoding means, the encoded data output from the encoding means is temporarily stored, output to the decoding means, and output to the decoding means. And a buffer memory for adjusting the amount of data.

In this encoding device, the input data is encoded by the encoding means and the encoded data is output. The encoded data is temporarily held by the buffer memory and then decoded by the decoding means to output the decoded data. Therefore, in one encoder, it is possible to confirm the quality of data when the encoded data is decoded while the input data is encoded.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

First, for comparison with the present invention, FIG.
An example of the structure of the MPEG encoding device is shown in FIG. This MPEG
The encoding device 110 uses the digital video input data D
A video encoder 111 for encoding I ₁ based on the MPEG standard and a digital audio input data DI
₂ , an audio encoding device 112 that encodes ₂ based on the MPEG standard, a subtitle encoding device 113 that encodes digital subtitle data DI ₃ that is incidental information such as subtitles, and these encoding devices 111, 1
MPE by multiplexing coded data by 12, 113
It is provided with a primary multiplexer 114 as a multiplexing device for outputting as a G standard output bit stream DO ₀₁ .

Further, as shown in FIG. 12, a plurality of MPs are used.
The EG encoding devices 110 _{1 to} 110 _n are provided, and each MPEG
The output bit streams of the encoding devices 110 _{1 to} 110 _n are provided with a secondary multiplexer 11 as a multiplexing device.
It is also possible to configure a multi-channel encoding device by multiplexing the data by 5 and outputting it as an output bit stream DO ₀₂ . In addition, each MPEG encoding device 11
0 _{1 to} 110 _n are adapted to input respective channel input data CH _{1 to} CH _n including video input data, audio input data and subtitle data.

The MPEG encoding device 110 shown in FIG.
The output bit stream DO ₀₁ output from the device is delivered to a general home through a modulator, an artificial satellite or the like, or is recorded in a storage medium. In order to reproduce this bit stream, MPEG as shown in FIG. 13 is used.
Decoding device 120 is required. The MPEG decoding device 120 includes a demultiplexer 121 that separates an input bit stream DI ₀₁ into video coded data, audio coded data, and subtitle coded data, and video coded data output from the demultiplexer 121. The video output data DO is decoded by decoding the audio coded data and the subtitle coded data.
₁₁ , a video decoding device 12 for outputting as audio output data DO ₁₂ and subtitle output data DO ₁₃
2. An audio decoding device 123 and a subtitle decoding device 124 are provided.

Next, an encoding apparatus according to the first embodiment of the present invention will be described with reference to FIGS. 1 and 2.

FIG. 1 is a block diagram showing the configuration of an MPEG coding apparatus including a coding apparatus according to the first embodiment of the present invention. This MPEG encoding device 10 includes a video encoding device 11 for encoding video input data DI ₁ based on the MPEG standard and an audio input data DI ₂
Audio encoding device 12 that encodes data based on the MPEG standard, and subtitle encoding device 13 that encodes subtitle data DI ₃ that is incidental information such as subtitles.
And an output bit stream, which is encoded data by each of the encoding devices 11, 12, and 13, is multiplexed, and M
It is provided with a primary multiplexer 14 as a multiplexing device for outputting as an output bit stream DO ₁ of the PEG standard.

In the present embodiment, the video encoding device 11 further decodes the encoded data and outputs the video monitor output data DO ₂ as the decoded data. Similarly, the audio encoding device 12
Decodes the encoded data and outputs audio monitor output data DO ₃ as the decoded data. These points are different from the video encoding device 111 in FIG. The video encoding device 11 and the audio encoding device 12 correspond to the encoding device according to the present embodiment.

FIG. 2 is a block diagram of the video encoding device 1 shown in FIG.
2 is a block diagram showing a configuration of No. 1. Video encoding device 1
Reference numeral 1 denotes video input data (hereinafter referred to as input original image data. An image based on this data is referred to as an input original image) DI ₁ is encoded based on the MPEG standard, and output bits as encoded data. A video encoding circuit 21 as an encoding means for outputting the stream DO _0, and a FIFO (first in / first out) as a buffer memory for temporarily holding the encoded data output from the video encoding circuit 21. The memory 22 and the encoded data read from the FIFO memory 22 are stored in M
A video decoding circuit 23 as a decoding means for decoding based on the PEG standard and outputting video monitor output data DO ₂ as the decoded data, and a decoding memory 24 connected to the video decoding circuit 23. , And a control unit 25 for controlling the video encoding circuit 21 and the video decoding circuit 23. The video encoding circuit 21 uses the MPE
Based on the G standard, processing such as inter-frame prediction motion vector detection, DCT (discrete cosine transform), quantization, and variable length coding is executed to encode and compress the input original image data DI _1. It has become. The video decoding circuit 23 performs variable length code decoding based on the MPEG standard,
Each processing such as inverse quantization, inverse DCT, and inter-frame prediction motion compensation is executed to decode the input encoded data. The decoding memory 24 is a video decoding circuit 23.
Memory used in the decoding process in
For example, it is used as a buffer for data input, a buffer for data output, a memory for rearranging frames and motion compensation, and the like. The control unit 25 is composed of, for example, a microcomputer.

The video decoding circuit 23 confirms the syntax of the input coded data (rule of the data structure in the MPEG standard), and if there is an error in the syntax, a flag indicating that fact is coded. The time code, which is time information included in the encoded data, is output to the control unit 25. The syntax is specifically confirmed by confirming a code such as a start code included in each layer of the data structure in the MPEG standard. The control unit 25 uses the video decoding circuit 23.
A flag indicating that there is an error in the output syntax is stored in association with the time code, and this information is output from the data input / output unit when an output command is input from the data input / output unit (not shown). It is designed to output to.

Although not shown, the configuration of the audio encoding device 12 in FIG. 1 is different from that of FIG. 2 except that the video encoding circuit 21 is an audio encoding circuit and the video decoding circuit 23 is an audio decoding circuit. , Fig. 2
This is the same as the video encoding device 11 shown in FIG. In this case, the audio encoding circuit encodes audio input data (hereinafter referred to as input original audio data) DI ₂ based on the MPEG standard, and the audio decoding circuit outputs M.
The encoded data is decoded based on the PEG standard and output as audio monitor output data DO ₃ .

Next, the operation of the video coding apparatus 11 as the coding apparatus according to this embodiment will be described. The input original image data DI ₁ is encoded by the video encoding circuit 21 based on the MPEG standard, and is output to the primary multiplexer 14 as an output bit stream DO ₀ which is encoded data. Video encoding circuit 21
The coded data output from the video memory 22 is temporarily stored in the FIFO memory 22, read by the video decoding circuit 23, decoded according to the MPEG standard, and is the video monitor output data DO which is decoded data. It is output as ₂ .

Here, the role of the FIFO memory 22 will be described. The amount of data per unit time of the output bit stream DO ₀ output from the video encoding circuit 21 is not constant. This is because even if the output rate of the video encoding circuit 21 is a variable rate or the output rate of the video encoding circuit 21 is a fixed rate, the audio encoding device 1 can be processed by the primary multiplexer 14 in the subsequent stage.
This is because the amount of data taken from the video encoding circuit 21 changes because the data is multiplexed with other data such as the data output from 2 and the like. Therefore, if the output bit stream DO ₀ output from the video encoding circuit 21 is directly input to the video decoding circuit 23, the buffer for data input prepared in the decoding memory 24 will overflow or underflow. Therefore, in the present embodiment, the video encoding circuit 21 and the video decoding circuit 2
A FIFO memory 22 is provided between the first and second memory cells 3 and 3 to control excess and deficiency of data. As a result, the video decoding circuit 23 does not depend on the amount of data of the output bit stream DO ₀ from the video coding circuit 21 per unit time, that is, the buffer for data input does not overflow or underflow, and the FIFO Only the required amount of data can be read from the memory 22 and decoded.

The video monitor output data DO ₂ output from the video decoding circuit 23 is the MPEG encoding device 10.
Is output to the outside of. Therefore, the video monitor output data DO ₂ is digital-analog converted and is input to the monitor to display a reproduced image, whereby the input original image data DI ₁ is encoded by _one video encoding device 11. It is possible to confirm the quality of the reproduced image obtained by decoding the encoded data.

Further, the video decoding circuit 23 confirms the syntax of the input encoded data, and if there is an error in the syntax, outputs a flag indicating that to the control unit 25 together with the time code. . The control unit 25
A flag indicating that there is an error in the syntax output from the video decoding circuit 23 is stored in association with the time code, and this information is stored as data when an output command is input from a data input / output unit (not shown). Output from the input / output unit to the outside. As a result, it is possible to confirm whether the syntax of the output bitstream output from the video encoding device 11 is correct.

Similarly, in the audio encoding device 12,
The input original audio data DI ₂ is encoded according to the MPEG standard by an audio encoding circuit (not shown), and is output to the primary multiplexer 14 as an output bit stream which is encoded data. The encoded data output from the audio encoding circuit is also temporarily stored in a FIFO memory (not shown), read by an audio decoding circuit (not shown), and MPEG
The audio data is decoded according to the standard and is output to the outside of the MPEG encoding apparatus 10 as audio monitor output data DO ₃ which is the decoded data. Therefore, the audio monitor output data DO ₃ is digital-analog converted, input to the audio output device and reproduced, thereby
It is possible to confirm the quality of the reproduced sound obtained by decoding the encoded data while encoding the original input audio data DI ₂ by the audio encoding device 12 on the stand. Further, as in the case of the video encoding device 11, the audio decoding circuit and the control unit (not shown) can confirm whether or not the syntax of the output bitstream output from the audio encoding device 12 is correct. .

As described above, according to the video encoding device 11 or the audio encoding device 12 according to the present embodiment, the input original image data DI _{1 is} input by one video encoding device 11 or the audio encoding device 12. Alternatively, it is possible to confirm the quality of a reproduced image or reproduced sound obtained by decoding the encoded data while encoding the input original audio data DI ₂ , and at the same time, the video encoding device 1
1 or it is possible to confirm whether the syntax of the output bit stream output from the audio encoding device 12 is correct. Further, since the FIFO memory 22 is provided between the video encoding circuit 21 and the video decoding circuit 23, and similarly, the FIFO memory is provided between the audio encoding circuit and the audio decoding circuit, the video decoding circuit Two
3 or audio decoding circuit, the buffer for data input does not overflow or underflow,
The encoded data can be decoded. FIG.
When the video encoding device 11 and the audio encoding device 12 are used independently without using the ply multiplexer 14 as shown in FIG. If the amount of data is substantially constant, the FIFO memory does not necessarily have to be provided.

FIG. 3 is a block diagram showing the configuration of a video encoding apparatus according to the second embodiment of the present invention. In the present embodiment, the video encoding device 31 shown in FIG. 3 is used instead of the video encoding device 11 shown in FIG. This video encoding device 31 is the same as the video encoding device 11 shown in FIG.
3, the monitor output switching circuit 32 as a synthesizing unit
Is provided. Monitor output switching circuit 32
Is the decoded data (hereinafter referred to as reproduced image data) DR output from the video decoding circuit 23 and the input original image data DI _1, and both data are input according to a select signal SE input from the outside. DR and DI ₁ are switched to output as video monitor output data DO ₂ .

FIG. 4 shows the monitor output switching circuit 3 in FIG.
2 is a block diagram showing a configuration of FIG. The monitor output switching circuit 32 includes a delay circuit 33 that delays the input original image data DI ₁ for a predetermined time, a delay circuit 34 that delays the reproduced image data DR for a predetermined time, and a delay circuit 33 according to the select signal SE. , 34 for outputting one of the output data of the video monitor output data DO ₂ as video monitor output data DO ₂ . Delay circuit 3
3,34, like the same region of the reproduced image based on the input original image and the reproduced image data DR based on the input original image data DI ₁ is divided displayed on the same screen of the monitor, and the input original image data DI ₁ Play At least one of the image data DR is delayed by a predetermined time. Therefore, only one of the delay circuits 33 and 34 may be provided. Further, when delaying the input original image data DI ₁ , a delay circuit 33 is required, but when delaying the reproduced image data DR, the decoding memory 24 can be used instead of providing the delay circuit 32. The configuration of the video encoding device 31 in this case is shown in FIG.

The video encoding device 31 shown in FIG. 5 is provided with a monitor output switching circuit 36 instead of the monitor output switching circuit 32 shown in FIG. The structure of the monitor output switching circuit 36 is shown in FIG. The monitor output switching circuit 36 outputs a selector 35 for outputting _{one of the} input original image data DI ₁ and the reproduced image data DR as video monitor output data DO ₂ in response to the select signal SE, and for decoding based on the select signal SE. A read timing signal generation circuit 37 that generates a read timing signal RT that determines the read timing of the memory 24 is provided. The video decoding circuit 23 reproduces the reproduced image data D from the decoding memory 24 according to the read timing signal RT.
R is read and sent to the monitor output switching circuit 36. In the configurations shown in FIGS. 5 and 6, by appropriately setting the timing of the read timing signal RT, the same region of the input original image based on the input original image data DI ₁ and the reproduced image based on the reproduced image data DR are made the same. It becomes possible to divide and display on the screen.

Next, in order to divide and display the same area of the input original image based on the input original image data DI ₁ and the reproduced image based on the reproduced image data DR in the video encoding device 31 according to the present embodiment in the same screen. The operation of will be described. First, an outline of this operation will be described with reference to FIG. 7. In FIG. 7, (a) is input original image data D
The input original image 41 based on I ₁ is shown, and (b) shows the reproduced image 42 based on the reproduced image data DR.

First, a case will be described in which the same area of the input original image 41 and the reproduced image 42 is divided and displayed vertically in the same screen. The monitor output switching circuits 32 and 36 delay the reproduced image data DR by a time V / 2 which is half the vertical period V of the video signal, and the selector 35 selects the input original image data DI ₁ in the upper half period of the screen. In the lower half period of the screen, the reproduced image data DR is selected and output as the video monitor output data DO ₂ , and when this video monitor output data DO ₂ is input to the monitor and displayed, as shown in (c), The upper half of the input original image 41 is displayed on the upper half of the screen, and the upper half of the reproduced image 42 is displayed on the lower half of the screen. In the selector 35, the reproduced image data D is displayed in the upper half period of the screen.
When R is selected and the input original image data DI ₁ is selected and output as the video monitor output data DO _{2 in} the lower half period of the screen, the lower half of the reproduced image 42 is displayed in the upper half of the screen, and the input original image is displayed. The lower half of 41 is displayed in the lower half of the screen.

In the above example, the reproduced image data DR
However, the monitor output switching circuit 32 shown in FIG. 4 may delay the input original image data DI ₁ by V / 2. In this case, if the selector 35 selects the reproduced image data DR in the upper half period of the screen and the input original image data DI ₁ in the lower half period of the screen, the upper half of the reproduced image 42 becomes the upper half of the screen. Displayed and input original image 41
The upper half of is displayed in the lower half of the screen. On the other hand, when the selector 35 selects the input original image data DI ₁ in the upper half period of the screen and the reproduced image data DR in the lower half period of the screen, the lower half of the input original image 41 becomes the upper half of the screen. The lower half of the reproduced image 42 displayed is displayed in the lower half of the screen.

Next, a case where the same area of the input original image 41 and the reproduced image 42 is divided and displayed on the left and right sides of the same screen will be described. The monitor output switching circuits 32 and 36 delay the reproduced image data DR by a time H / 2 which is half the horizontal period H of the video signal, and the selector 35 selects the input original image data DI ₁ in the left half period of the screen. , The reproduced image data DR is selected and outputted as the video monitor output data DO _{2 in} the right half period of the screen, and when this video monitor output data DO ₂ is input to the monitor and displayed, as shown in (d), The left half of the input original image 41 is displayed on the left half of the screen, and the left half of the reproduced image 42 is displayed on the right half of the screen. In the selector 35, the reproduced image data D is displayed in the left half period of the screen.
When R is selected and the input original image data DI ₁ is selected and output as the video monitor output data DO _{2 in} the right half period of the screen, the right half of the reproduced image 42 is displayed in the left half of the screen, and the input original image is displayed. The right half of 41 is displayed in the right half of the screen.

In the above example, the reproduced image data DR
However, the input original image data DI ₁ may be delayed by H / 2 in the monitor output switching circuit 32 shown in FIG. In this case, when the selector 35 selects the reproduced image data DR in the left half period of the screen and the input original image data DI ₁ in the right half period of the screen, the left half of the reproduced image 42 becomes the left half of the screen. Displayed and input original image 41
The left half of is displayed on the right half of the screen. On the other hand, if the selector 35 selects the input original image data DI ₁ in the left half period of the screen and the reproduced image data DR in the right half period of the screen, the right half of the input original image 41 becomes the left half of the screen. The right half of the reproduced image 42 is displayed on the right half of the screen.

Thus, the input original image 41 and the reproduced image 4
The input original image data DI ₁ and the reproduced image data D ₁ are displayed depending on which area of the monitor screen is displayed in which area of 2
Which of R is to be delayed and select signal S
The timing and phase of switching E may be selected. In each of the above examples, the delay amount is not always V
The delay amount does not have to be 1/2 or H / 2, and may be any delay amount such that the same region of the input original image 41 and the reproduced image 42 is divided and displayed in the same screen. In this case, the timing of switching the select signal SE is determined according to the delay amount.

Next, with reference to FIG. 8, the operation in the case where the same region of the input original image based on the input original image data DI ₁ and the reproduced image based on the reproduced image data DR is divided and displayed on the left and right sides within the same screen This will be specifically described. FIG.
In the example shown in (1), the reproduced image data DR is delayed by H / 2 in the monitor output switching circuits 32 and 36. In FIG. 8, (b) represents a reproduced image, and (c)
Represents a delayed reproduced image, and (d) represents an input original image. When the select signal shown in (a) is at the L level, the input original image data DI ₁ is selected, and when it is at the H level, the reproduced image data DR is selected. The switching cycle of the select signal SE is 1H, the switching timing from the L level to the H level is the timing corresponding to the left and right center positions in the input original image,
The timing of switching from the H level to the L level is the timing corresponding to the left end of the input original image. In addition,
Although one screen is shown every 1H in (b) to (d), these do not represent separate frames, but 1H
The reproduced image data DR and the input original image data DI ₁ in the period are each data for one line in one frame. In this way, the monitor output switching circuits 32 and 36 delay the reproduced image data DR by H / 2,
In the selector 35, the input original image data DI ₁ is selected in the left half period of the screen, and the reproduced image data DR is selected in the right half period of the screen to output the video monitor output data DO.
_When output as ₂ , the video monitor output data DO ₂ is input to the monitor and displayed, as shown in (e), the left half of the input original image is displayed on the left half of the monitor screen, and the left half of the reproduced image is displayed. Is displayed on the right half of the monitor screen. In addition, in (c) to (e), a dashed arrow indicates the correspondence between the area on the monitor screen and the area in the delayed reproduced image and input original image.

When confirming or evaluating the image quality of the reproduced image obtained by decoding the compressed data, it is an effective means to compare with the input original image before compression. In general, the input original image and the reproduced image are often displayed on separate monitors and arranged side by side for comparison. However, in this case, two monitors are required to compare the input original image and the reproduced image, and it is difficult to compare both images. On the other hand, according to the video encoding device 31 of the present embodiment, as described above, the input original image and the reproduced image are divided into upper and lower or left and right free positions within the same screen of one monitor. Since it can be displayed as a single monitor, only one monitor is required and both images can be easily compared. Other configurations, operations, and effects in the present embodiment are the same as those in the first embodiment.

FIG. 9 is a block diagram showing the arrangement of a video encoding apparatus according to the third embodiment of the present invention. In the present embodiment, the video encoding device 51 shown in FIG. 9 is used instead of the video encoding device 11 shown in FIG. This video encoding device 51 is the same as the video encoding device 11 shown in FIG.
A delay memory 52 as a delay means for delaying I ₁ by a predetermined time, and a difference between the input original image data DI ₁ ′ delayed by the delay memory 52 and the reproduced image data DR output from the video decoding circuit 23 are obtained. And a compression distortion measuring circuit 53 as a difference output means for outputting as video monitor output data DO ₂ . Delay memory 52 (encoding and decoding system delay amount including the video encoding device 51) only by delaying the input original image data DI ₁ delay amount of the reproduced image data DR for the input original image data DI _1, Delayed input original image data D
The phase of I ₁ ′ is made to match the phase of the reproduced image data DR.

Video coding apparatus 51 according to the present embodiment
Then, the delay memory 52 delays the input original image data DI _{1 by} the delay amount of the reproduced image data DR with respect to the input original image data DI ₁ , and the compression distortion measuring circuit 5
Input original image data DI ₁ ′ delayed by 3
And the reproduced image data DR output from the video decoding circuit 23 are obtained, and this difference is output as video monitor output data DO ₂ . Therefore, by inputting and displaying the video monitor output data DO ₂ on a monitor, for example, while encoding the input original image data DI ₁ , the difference between the input original image and the reproduced image is displayed on the monitor and the compression distortion is displayed. Can be confirmed on the monitor screen. Further, the compression distortion is quantitatively measured by outputting the video monitor output data DO ₂ as a numerical value or by obtaining and outputting the integrated value of the video monitor output data DO ₂ on one screen or a plurality of screens. Will also be possible.

In order to make it easy to confirm the compression distortion on the monitor screen, the compression distortion measuring circuit 53 may expand the difference and add an offset to output it as video monitor output data DO _2. . Also, the audio encoding device 12 in FIG. 1 may have the same configuration as the video encoding device 51 according to the present embodiment. In this case, by inputting the output data of the compression distortion measuring circuit to the audio output device and reproducing it,
The compression distortion can be confirmed as sound. In addition, the compression distortion can be quantitatively measured as in the case of the video encoding device 51. Other configurations, operations, and effects in the present embodiment are the same as those in the first embodiment.

FIG. 10 is a block diagram showing the structure of a video encoding apparatus according to the fourth embodiment of the present invention. In this embodiment, the video encoding device 61 shown in FIG. 10 is used instead of the video encoding device 11 shown in FIG. This video encoding device 61 is different from the video encoding device 31 shown in FIG. 3 in that a switch 62 as a switching unit is newly provided at the subsequent stage of the video encoding circuit 21 and the input end of the input bit stream DI ₀ is connected. It has a configuration provided. The movable contact of the switch 62 is FIF
It is connected to the input end of the O memory 22, one fixed contact is connected to the output end of the video encoding circuit 21 and the output end of the output bit stream DO ₀ in the video encoding device 61, and the other fixed contact is the video end. It is connected to the input end of the input bit stream DI ₀ in the digitizer 61.
The switch 62 is an input / output switching signal S input from the outside.
It can be switched according to W.

Video coding apparatus 61 according to the present embodiment
Then, when used as an ordinary encoding device, the movable contact of the switch 62 is changed by the input / output switching signal SW.
Output end of video encoding circuit 21 and video encoding device 61
At one of the fixed contacts connected to the output end of the output bitstream DO ₀ at. In this state, the video encoding device 61 has the same configuration as the video encoding device 31 according to the second embodiment shown in FIG. 3 and performs the same operation as the video encoding device 31.

On the other hand, the video coding device 61 according to the present embodiment can also be used as a decoding device.
When used as a decoding device, the input / output switching signal S
W connects the moving contact of the switch 62 to the other fixed contact connected to the input end of the input bitstream DI ₀ . In this state, the encoded data output from the video encoding circuit 21 is not input to the FIFO memory 22, and the external input bit stream DI ₀ is FIFO.
The data can be input to the memory 22. Therefore, for example, by inputting the input bitstream DI ₀ from an external storage medium or the like from the input end of the input bitstream DI ₀ and inputting it to the FIFO memory 22 via the switch 62, the input bitstream DI ₀ is video-coded. It can be decoded by the decoding circuit 23 and output as video monitor output data DO ₂ via the monitor output switching circuit 32.

Video coding apparatus 61 according to the present embodiment
Is effectively used, for example, after the input original image data DI ₁ is encoded and compressed, the data is recorded in a storage medium, and then the data recorded in the storage medium is reproduced and decoded. In some cases, the quality of the reproduced image may be confirmed by the confirmation. In such cases, conventionally,
Although a decoding device different from the coding device is used, according to the video coding device 61 according to the present embodiment, the input original image data DI ₁ is coded and compressed by the video coding device 61. After recording the subsequent data (output bit stream DO ₀ ) in the storage medium, the data recorded in the storage medium is reproduced and input as an input bit stream DI ₀ to the video encoding device 61 for decoding, and the video monitor It can be output as output data DO _{2 and} can be handled by one video encoding device 61.

When the video encoding device 61 is used as a decoding device and only the reproduced image obtained by decoding the input bit stream DI ₀ input from the outside is to be displayed on the monitor, the monitor output is used. In the switching circuit 32, only the reproduced image data DR output from the video decoding circuit 23 is selected. Further, at the same time when the input bit stream DI ₀ is input from the outside, the uncompressed input original image data DI ₁ corresponding to the input bit stream DI ₀ is also input at the same time, and monitor output switching is performed as in the second embodiment. In the circuit 32, the input original image data DI ₁ and the reproduced image data DR are switched and output, so that the input original image and the reproduced image are divided and displayed on the same screen of one monitor, and both images can be compared. It is possible.

As described above, according to the video coding apparatus 61 according to the present embodiment, it is possible to input coded data from the outside and confirm the quality of the data when the data is decoded. Yes, in particular, after recording the data after encoding and compressing the input original image data in the storage medium, play back the data recorded in this storage medium and decode it to check the quality of the playback image, etc. Will be easier.

The audio encoding device 12 in FIG. 1 may have the same configuration as the video encoding device 61 according to this embodiment. Other configurations, operations and effects in this embodiment are the same as those in the first embodiment or the second embodiment.

The present invention is not limited to each of the above-described embodiments. For example, the present invention is not limited to a coding apparatus adopting the MPEG standard, but can be applied to a coding apparatus according to various coding methods. it can.

[0051]

As described above, according to the encoding device of any one of claims 1 to 4, together with the encoding means for encoding the input data and outputting the encoded data,
Decoding means for decoding the encoded data output from the encoding means and outputting the decoded data, and temporarily holding the encoded data output from the encoding means and outputting to the decoding means for decoding Since the buffer memory for adjusting the data amount of the encoded data output to the encoding means is provided, the quality of the data when the encoded data is decoded while encoding the input data in the encoding device. It is possible to confirm that, and even if the data generation amount per unit time of the encoding device is variable, it is possible to decode the encoded data without causing overflow or underflow. .

According to the encoding device of the second aspect, the decoding is performed so that the image based on the decoded data output from the decoding means and the image based on the input data are divided and displayed in the same screen. Since the synthesizing means for synthesizing the decoded data output from the synthesizing means and the input data is provided, in addition to the first effect described above, while encoding the input image data,
It is possible to easily compare the image based on the data obtained by decoding the encoded data with the image based on the input image data.

According to the encoding device of the third aspect, the delay means for delaying the input data according to the delay amount of the decoded data output from the decoding means for the input data, and the output data of the delay means. And the difference output means for obtaining and outputting the difference between the decoded data output from the decoding means, and in addition to the above first effect, there is an effect that it is possible to confirm and measure the compression distortion. .

Further, according to the encoding device of the fourth aspect, the switching means for switching between the encoded data output from the encoding means and the encoded data input from the outside and inputting to the decoding means. In addition to the above first effect, it is possible to encode the input data, input the encoded data from the outside, and confirm the quality of the data when the data is decoded. It has the effect of being able to.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an MPEG encoding device including an encoding device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a video encoding device in FIG.

FIG. 3 is a block diagram showing a configuration of a video encoding device according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a monitor output switching circuit in FIG.

5 is a block diagram showing a configuration of a modified example of the video encoding device shown in FIG.

6 is a block diagram showing a configuration of a monitor output switching circuit in FIG.

FIG. 7 is an explanatory diagram for explaining an outline of an operation of the video encoding device according to the second embodiment of the present invention.

[Fig. 8] Fig. 8 is an explanatory diagram for describing a specific example of the operation of the video encoding device according to the second embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of a video encoding device according to a third embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration of a video encoding device according to a fourth embodiment of the present invention.

FIG. 11 is a block diagram showing a configuration example of an MPEG encoding device for comparison with the present invention.

FIG. 12 is a block diagram showing a configuration of a multi-channel encoding device.

FIG. 13 is a block diagram showing the structure of an MPEG decoding device.

[Explanation of symbols]

10 ... MPEG coding device, 11 ... Video coding device,
12 ... Audio encoding device, 14 ... Primary multiplexer, 21 ... Video encoding circuit, 22 ... FIFO memory, 23 ... Video decoding circuit, 24 ... Decoding memory,
25 ... Control unit, 32 ... Monitor output switching circuit

Claims (4)

[Claims] 1. Encoding means for encoding input data to output encoded data, decoding means for decoding encoded data output from said encoding means and outputting decoded data, said code Coded data that is provided between the encoding means and the decoding means, temporarily holds the encoded data output from the encoding means, outputs the encoded data to the decoding means, and outputs the encoded data to the decoding means. And a buffer memory for adjusting the data amount of the encoding device. 2. The decoding is such that the input data is image data, and the image based on the decoded data output from the decoding means and the image based on the input data are divided and displayed in the same screen. The encoding device according to claim 1, further comprising a combining unit that combines the decoded data output from the converting unit and the input data. 3. A delay means for delaying the input data according to a delay amount of the decoded data output from the decoding means with respect to the input data, output data of the delay means and output from the decoding means. The encoding device according to claim 1, further comprising: a difference output unit that obtains and outputs a difference from the decoded data. 4. A switching means for switching between encoded data output from the encoding means and encoded data input from the outside and inputting to the decoding means. 1. The encoding device according to 1.