JPH09261056A - Analog/digital converter of half pipeline type - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify the physical structure of a parallel analog/digital converters by providing a rough A/D converter converting an analog voltage signal into a roughly decomposed digital code and first and second precise A/D converter converting the analog voltage signal into a precise resolution digital code. SOLUTION: An analog input voltage(Vin ) 150 is applied to the rough A/D converter 400 and the precise A/D converters 401 and 402. Vin 150 is sampled and held by the rough A/D converter 400 and the precise A/D converter 401 and 402 in the first period of a clock. In the second period of the clock, the rough A/D converter 400 compares a voltage generated by a resistance type potential divider circuit network forming a rough reference voltage generator 100 and the sample of Vin 150. The resistance type potential divider circuit network is connected between reference voltage sources VRB 120 and VRT 130. As a result of comparing Vin 150 and the rough reference voltage generator 100, a thermometer code which is a rough digital code 475 is formed.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates generally to analog-to-digital (A / D) converters and conversion methods, and more particularly to determining a coarse range of input voltage using the first stage of conversion. However, the subsequent stage relates to a multi-stage parallel type converter that decomposes the analog input signal into finer increments. The invention has applications in video and digital signal processing.

[0002]

BACKGROUND OF THE INVENTION Applying digital processing and transmission methods to analog information requires that signals be converted from their analog form to a digital representation. Known types of A /
The D converter is a parallel comparator type or flash (FLASH) converter that compares a plurality of reference voltages with an input voltage and outputs a digital code representing the reference voltage closest to the input voltage from the encoding logic circuit in one operation, and Includes a continuous approximation type that uses a digital-to-analog converter to iterate successive trial and error approximations to the input to produce a digital output. FIG. 1 shows a flash type A / D converter. Typically the output is the encoder logic 30
And a resolution of n bits of the input signal can be obtained. This structure is typically 2 ⁿ
A level reference voltage 10 and 2 ⁿ comparators 20 are required. Attempts to improve the resolution of this type of converter (increasing the number of output bits) add to the complexity of the design.

FIG. 2 shows a continuous approximation A / D converter. The analog input signal V _in is applied to the input of the sample hold circuit 50. Sampled analog input signal 55
Is applied to the cord 60. Data encoder 70
Sets the most significant bit 90d of the data output word 90a, ..., 90d to a logic "1" and all other bits 90a, 90b, 90c to a logic "0". The output 85 of the D / A converter 80 in this case is D / A
It is the voltage at the midpoint of the voltage range of the A converter 80. If D /
If the output 85 of the A converter 80 is greater than the sampled analog signal 55, the output of the comparator 60 will be 0 and the clock will not be able to pass through the AND gate 65. Therefore, the data encoder 70 sets the most significant bit 90d to logic "0", and the next most significant bit 90d
Set c to logic "1". In this case, the voltage of the output 85 of the D / A converter 80 is 1/4 of the voltage range of the D / A converter 80. If the output 85 of the D / A converter 80 is less than the sampled analog signal 55, the output of the comparator 60 will be a logical "1". This causes AND gate 65 to pass the clock, the next most significant bit 90c continues to be set to logic "1", and the next least significant bit to logic "1".

This process of trialing and setting output bits 90a, ..., 90d continues until it is determined that all bits represent the magnitude of the sampled input signal. This process only outputs bits 90a, ..., 90d after the process has completed.
Need to find out. The continuous approximation A / D converter requires a separate sample and hold circuit and a complicated A / D converter, and thus may cause a process error. Two techniques are known for simplifying the design of flash A / D converters. Both of these techniques achieve A / D conversion using a multi-stage conversion. The first technique is US Pat. No. 5,302,869 (Hosotani et al.), US Pat. No. 5,389,9.
29 (Nayebi et al.), U.S. Pat.No. 5,353,027 (Vorenkam
, et al., US Pat. No. 5,369,309 (Bacrania et al.), and US Pat. No. 5,387,914 (Mangelsdorf), the first step is coarse resolution flash A / D conversion, and a digital-to-analog converter. The second stage, which adjusts the reference voltage of the voltage comparator, achieves the final resolution conversion. The results of the two converters are encoded and formed into a digital output word representing the magnitude of the analog input voltage. In the second technique, US Pat.
1,198 (Dingwall et al.), U.S. Pat.No. 5,223,836 (Kom
atsu), U.S. Pat.No. 5,400,029 (Kobayashi), U.S. Pat.No. 4,733,217 (Dingwall), U.S. Pat.
No. 9,354 (Ho et al.), Patent Application Serial Number 08 / 497,881 assigned to the same assignee as the present application, and ERSO 85-0009 assigned to the same assignee as the present application,
A plurality of conversion stages are provided, and the decision logic circuit appropriately switches the reference voltage to each stage based on the result of the preceding comparison stage.

[0005] In the circuit of the multi-stage second U.S. Patent No. 4,903,028 shown in Figure 3 as an example of a technique of converting (Fukashima), a value that increases incrementally from V _RefBot (minimum value) to V _RefTop (maximum value) The range of conversion of the voltage input (V _in ) is determined by providing a set of voltage sources 1 having Voltage input, a set of applied in crude Subrange comparator 2, also the set of reference coarse subranges voltage discrete intervals being applied to crude sub-range comparator 2 V _in 1
a and 1b are decided. The output 5 of the coarse subrange comparator is an input to the steering logic and switch logic circuit 3, which is a set of fine subrange comparators 4.
To the appropriate subrange of the set of reference voltages 1. 1 set of reference voltages 1a is divided in fine increments, the digital output from the _{V in (D0, D1, D2} , ···, Dn)
Determine the minimum resolution for conversion to. When V _in changes, the output code, that is, the value of the coarse subrange comparator 5, changes, and the steering and switch logic circuit 3 moves the fine subrange comparator 4 to the next subrange (from 1a to 1b).

Due to tolerances in component selection and process variations, the output code 5 of the coarse subrange comparator 2 can produce errors. In order to detect this error, the subrange 1a or 1b determined by V _in
Are provided above and below the sub-range comparators 4a and 4b. The outputs of the extreme comparators 4a and 4b form an error code 7. The output code 6 of the fine sub-range comparator, the set of error codes 7 and the set of the coarse sub-range codes 5 are the output encoding logic circuit 8.
Is interpreted by the output digital representation of the voltage input _{V in (D0, D1, D2} , ···, Dn) is determined. A
An important component of the / D converter is the voltage comparator. Voltage comparators are known and consist of an operational amplifier with one input connected to a reference voltage source and the other input to which the analog voltage signal of interest is applied.
If the analog voltage signal is greater than the reference voltage source, the output will assume the first logic state. However, if the analog voltage signal is less than the reference voltage source, the output will assume a second logic state.

Another type of comparator, disclosed in patent application Ser. No. 08 / 405,721, assigned to the same assignee as this application, uses multiple amplifiers to compare an analog voltage signal with a reference voltage. Form a partition comparator.

[0008]

SUMMARY OF THE INVENTION It is an object of the present invention to reduce the complexity of the physical structure of a parallel analog-to-digital converter. Another object of the present invention is to provide a D / D converter for a continuous approximation A / D converter.
To reduce power consumption by eliminating unnecessary circuits such as A converters and sample and hold circuits. A further object of the invention is to improve the settling time of the reference voltage generator of the parallel A / D converter. Semi-pipelined A to achieve these and other objectives
The / D converter includes a coarse A / D converter for converting an analog voltage signal into a coarse resolution digital code and first and second fine A / D converters for converting an analog voltage signal into a fine resolution digital code. Have The coarse reference voltage generator is
Generating a first plurality of reference voltages applied to the coarse A / D converter. The fine reference voltage generator includes first and second fine A / Ds.
Generating a second plurality of reference voltages applied to the converter.

Coarse reference voltage switching means is connected to the coarse reference voltage generator to selectively apply one of the plurality of coarse reference voltages to the first and second fine A / D converters. Which coarse reference voltage is applied depends on the value of the coarse digital code. The output encoding means converts the coarse digital code and the first and second fine digital codes into an output digital code representing the magnitude of the analog input voltage. The fine digital code is generated in the first fine A / D converter at the first conversion time and is generated in the second fine A / D converter at the second conversion time. The first conversion time and the second conversion time are repeatedly switched to form a series of output digital codes from the continuous analog voltage signal.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. The analog input voltage (V _in ) 150 is used for the coarse A / D converter 400 and the fine A / D converter 400.
It is applied to the D converters 401 and 402. V _in 150
Is a coarse A / D converter 400 during the first period of the clock,
It is sampled and held by the fine A / D converters 401 and 402. During the second period of the clock, the coarse A / D converter 400 compares the voltage generated by the resistive voltage divider network forming the coarse reference voltage generator 100 with a sample of V _in 150. The resistor divider network includes a reference voltage source V _RB 120
And V _RT 130. The comparison of V _in 150 with the coarse reference voltage generator 100 results in the thermometer code being the coarse digital code 475. The thermometer code is a binary code, and this binary code changes each continuous digit of the code to "1" as the code increases, such as the lowest value of the 0000 code 0001 0011 0111 1111 the highest value of the code. It is like this.

The coarse digital code 475 is provided to the reference voltage selection logic network 300 to provide the coarse reference voltage generator 10.
The reference voltage of 0 is selected, and the fine A / D converters 401 and 4 are selected.
02 is applied. That is, the switches 301, 302, 3
03 and 304 operate to supply an appropriate reference voltage from the coarse reference voltage generator 100 to the fine A / D converters 401 and 402. The fine reference voltage generator 200 is another resistive voltage divider network and is connected in parallel with one of the resistors of the coarse reference voltage generator 100, for example resistor 101. Each reference voltage of the fine reference voltage generator 200 is the fine A / D converters 401 and 402.
Is applied to During the third and fourth periods of the clock, the analog input signal 150 has a selected coarse reference voltage 350.
And the voltage of the fine reference voltage generator 200.
As a result of this comparison, the fine digital codes 425 and 45
0, a thermometer code is formed.

The coarse digital code 475 and the fine digital codes 425 and 450 are converted into the output digital code 510 in the output encoder 500. Output digital code 510 is a binary number having a set of most significant bits of coarse digital code 475 and a set of least significant bits of fine digital code 425 or 450. The output digital code 510 is output during the fifth period of the clock and held during the fifth and sixth periods.
The conversion cycle consisting of the first to sixth periods of the clock is repeated many times to form a series of output digital codes representing the magnitude of V _in . The fine A / D converter 401 outputs the fine digital code 425 in one conversion cycle. In another conversion cycle, the fine A / D converter 402 outputs the fine digital code 450. Like this
The alternating use of the / D converters 401 and 402 allows the sampling of the next conversion cycle to begin while the previous conversion cycle is being processed. Then, the sampling rate can be doubled as compared with the case where only one fine A / D converter is provided.

Each of the precise A / D converters 401 and 402 is formed by a plurality of comparator cells 410.
5 and 6 show circuit diagrams of the comparator cell. The analog input voltage V _in is applied to the first terminal of a metal oxide semiconductor field effect transistor (MOSFET) switch 600. The voltage (V _R1 ) 645 that is the selected coarse reference voltage (350 in FIG. 4) becomes the MOSFET switch 640.
Is applied to the first terminal of the. Voltage (V _R2 ) which is one of the voltages generated by the fine reference voltage generator (200 in FIG. 4)
655 is applied to the first terminal of the MOSFET switch 650, and the threshold reference voltage (V _th ) 635 is
It is applied to the first terminal of the FET switch 630.
The capacitor 620 is the MOSFET switch 600, 6
40 second terminal and MOSFET switch 630 second terminal
It is connected between the terminal and. MOSFET switch 670 is connected between the second terminal of MOSFET switch 630 and the second terminal of MOSFET switch 650. The first terminal of the capacitor 660 is MOSF
It is connected to the second terminals of the ET switches 650 and 670. The second terminal of the capacitor 660 is connected to the amplifier 730.
Is connected to the input terminal of The output of amplifier 730 is the output of comparator circuit 715 (V _O4 ), which is the fine digital comparator (425 and 450 in FIG. 4).
Is a single bit that forms

Amplifier 730 can be configured depending on the application. In FIG. 5, the input of the amplifier 730 is a MOS
It is connected to the first terminal of the FET switch 685 and the input terminal of the amplifier 680. MOSFET switch 68
The second terminal of 5 and the output terminal of the amplifier 680 are connected to the first terminal of the capacitor 690. The second terminal of the capacitor 690 is connected to the first terminal of the MOSFET switch 695 and the input terminal of the amplifier 700. The second terminal of MOSFET switch 695 and the output terminal of amplifier 700 are connected to the input terminal of latching amplifier 710. The output terminal of the latching amplifier 710 is the output of the amplifier 730. In FIG. 5, three inverters 680, 700 and 710 are shown. Each inverter stage operates as an amplifier and the number of inverter stages can be changed depending on the application.

An alternative design of amplifier 730, shown in FIG.
The input of amplifier 730 is connected to the first terminal of MOSFET switch 750 and the negative terminal of operational amplifier 740. Since the positive terminal of the operational amplifier 740 is connected to the reference voltage V _REF , the operational amplifier 740 functions as a voltage comparator. The second terminal of MOSFET switch 750 and the output of operational amplifier 740 form the output of amplifier 730. MOSFET switch 600, 63
0, 640, 650, 670, 685, 695, and 7
50 is controlled by a control timing signal 720. The operating modes of the comparators shown in Figures 5 and 6 are shown in Figures 7-10. FIG. 7 shows the comparator during the first period of the clock at which V _in 605 is sampled. MOSFET switches 600, 630, 65
0, 685, and 695 are conducting, and MOSFET switches 640 and 670 are non-conducting. Capacitor 620
The voltage generated across V is −V _in −V _th . Voltage generated across the capacitor 660, V _R2 -V
_th2 (V _th2 is the self-bias voltage of the amplifier 680). Amplifier 700 is also biased with its self-bias voltage.

FIG. 8 shows the operation of the comparator during the second period of the clock. Since MOSFET switch 600 is non-conducting, the voltage across capacitor 620 is held constant, thus maintaining a sample of V _in 605. In this operation, the MOSFET switch 63
0 has no effect on the voltage held across capacitor 620, so it can be either on or off. FIG. 9 shows the operation of the comparator in the third period of the clock. The MOSFET switch 640 is turned on, and V _R1 645 is at point A (capacitor 620).
First terminal) of. As a result, the voltage at the point B (the second terminal of the capacitor 620) becomes V _th + (V _R1 −V
_in ). The value of V _R1 depends on the selected coarse reference voltage (see FIG.
350).

The operation of the comparator during the fourth period of the clock is shown in FIG. MOSFET switch 640 remains conductive and MOSFET switches 600, 63
0, 650, 685, and 695 are made non-conductive. M
OSFET switch 670 conducts and capacitor 620
Has a second terminal connected to the first terminal of the capacitor 660. With this connection, the voltage appearing at the point D (input to the amplifier 680) becomes [V _th2 + {V _th + (V _R1 −V _in ) −V _R2 ]. V _R2 is equal to V _th + k ^* LSB (k ^* LSB is the finest voltage to be compared), so the above equation becomes V _th2 + (V _R1 −V _in −k ^* LSB). The input terminals of the amplifiers 680 and 700 are
Because they are set to their self-bias level,
Only the value V _R1 -V _in -k ^* LSB is amplified. Output V _{O4 of the} latching amplifier 710
Is, if V _in <if V _R1 -k ^* LSB, will be a logic "1", if V _in> if V _R1 -k ^* LSB, becomes a logic "0".

The timing diagram of FIG. 11 illustrates a method of half pipelined A / D conversion. During the first period of the clock 2000, the analog input signal changes to the coarse A / D converter 21.
00 (2110) and by the first fine A / D converter 2200 (221).
0). During a second period of clock 2000, coarse A / D converter 2100 compares the sampled analog input signal to the coarse reference voltage (2120). While the first fine A / D converter 2200 holds (2220) the sampled analog input voltage, an appropriate coarse reference voltage is selected and provided to the first fine A / D converter 2200. , Shift the voltage as described in FIG. Clock 2000
During the fourth period of time, the sampled and shifted analog input signal is compared by the first fine A / D converter 2200 (2240). Results of these rough and fine comparisons 24
05 is transferred to the output encoder and converted to the output digital code 2410 during the fifth period of the clock 2000 to become the data output 2400. The output digital code 2410 remains valid during the sixth period of clock 2000.

The second comparison cycle is clock 2000.
Sampling 2130 of the analog input signal by the coarse A / D converter 2100 during the third period of
Beginning with sampling 2310 of the analog input signal by converter 2300. Second coarse comparison 2140 and second holding 232 in second fine A / D converter 2300
0 occurs during the fourth period of clock 2000. Second
Are held and shifted during the fifth period of clock 2000. The coarse digital data and the fine digital data of the second conversion are converted into the output digital code 2 (2420) and output as the data output 2400 during the seventh period of the clock 2000, and are valid until the eighth period of the clock 2000. Retained. A method of deriving a code for the least significant bit is shown in FIG. Crude reference voltage generator (100 in FIG. 4) is, V _R1 (n) 3010 from V _R1 (n-
1) Up to 3030, each can be viewed as spanning between V _RT and V _{RB in} increments of one of the reference voltages. The fine A / D converter (401 and 402 in FIG. 4) divides the coarse increment into fine increments 3040.

If the analog input signal (V _in ) 3020
But, V _R1 (n) 3010 and V _R1 (n-1) If a point between 3030 receives coarse A / D converter V _R1 (Figure 400 4) in the (n) as a reference voltage Comparing comparator generates a logic "0", and a comparator receiving _VR1 (n-1) as a reference voltage generates a logic "1". The switch selection logic (300 in FIG. 4) feeds V _R1 (n) to the fine A / D converter (401 and 402 in FIG. 4). The fine A / D converter (401 and 402 in FIG. 4) is V
_R1 (n) -V _in (3050) is derived and this voltage is shifted into the fine comparator range 3150. Voltage 3170
Is based on V _th 3160. Reference voltage V _R2
(K) 3190 is derived from the fine reference voltage generator (200 in FIG. 4). The usable code 3180 is derived in the output encoder (500 in FIG. 4).

Although the present invention has been described with reference to preferred embodiments, it will be understood by those skilled in the art that various modifications in form and detail can be devised without departing from the spirit and scope of the invention. I want to be done.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a prior art parallel or flash A / D converter.

FIG. 2 is a circuit diagram of a conventional continuous approximation A / D converter.

FIG. 3 is a functional block diagram of a prior art two-stage A / D converter.

FIG. 4 is a functional block diagram of a semi-pipelined A / D converter of a preferred embodiment of the present invention.

FIG. 5 is a circuit diagram of the voltage comparator of the present invention.

FIG. 6 is a circuit diagram of another voltage comparator of the present invention.

FIG. 7 is a circuit diagram showing the operation of the comparator of the present invention in the first stage of the A / D conversion process.

FIG. 8 is a circuit diagram showing the operation of the comparator of the present invention in the second stage of the A / D conversion process.

FIG. 9 is a circuit diagram showing the operation of the comparator of the present invention in the third stage of the A / D conversion process.

FIG. 10 is a circuit diagram showing the operation of the comparator of the present invention in the fourth stage of the A / D conversion process.

FIG. 11 is a timing diagram of the steps of the A / D conversion method of the present invention.

FIG. 12 is a diagram showing the resolution of the precise digital comparator of the present invention.

[Explanation of symbols]

100 coarse reference voltage generator 101 resistance 150 analog input voltage signal 200 fine reference voltage generator 300 switch selection logic circuit 301-304 switch 400 coarse A / D converter 401, 402 fine A / D converter 410 fine comparator cell 425 475 Precision digital code 475 Coarse digital code 500 Output encoder 510 Output digital code 600, 630, 640, 650, 670, 685, 6
95,750 MOSFET switch 620,660,690 capacitor 680,700,710,740 amplifier 720 control timing signal 730 amplifier

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[Procedure amendment]

[Submission date] December 19, 1996

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

14. A voltage comparing means for generating an output comparison signal by comparing an analog input signal with a first reference voltage and a second reference voltage, wherein: a) an input terminal to which the analog input signal is applied; B) a first reference terminal to which the first reference voltage is applied, c) a second reference terminal to which the second reference voltage is applied, d) a threshold voltage source, and e) A first capacitor consisting of a first electrode plate and a second electrode plate; f) a first switch for selectively coupling the input terminal to the first electrode plate of the first capacitor; g) The first reference terminal is connected to the first capacitor of the first capacitor.
A second switch selectively coupled to the electrode plate of the first capacitor; and h) connecting the threshold voltage source to the second capacitor of the first capacitor.
A third switch selectively coupled to the electrode plate, i) a second capacitor composed of a first electrode plate and a second electrode plate, and j) the second reference terminal connected to the second capacitor. First of
A fourth switch selectively coupling to the electrode plate of the second capacitor, and k) a fifth switch selectively coupling the second electrode plate of the first capacitor to the first electrode plate of the second capacitor. L) amplifier means including an amplifier input terminal, an amplifier output terminal, an amplifier means for amplifying a signal applied to the amplifier input terminal and supplying the amplified signal to the amplifier output terminal, m) the amplifier A comparison output terminal that is connected to the output terminal and supplies an output comparison signal.

15. A given sample time, operating the first switch couples the said analog input signal to the first electrode plate of the first capacitor, the threshold operating the third switch The value voltage source is the second capacitor of the first capacitor.
15. Comparing means according to claim 14 coupled to said electrode plate.

Voltage between the 16. said first capacitor of said first electrode plate and second electrode plate, to claim 15 which is the difference between the analog input signal and the threshold voltage source Described comparison means.

17. The comparing means according to claim 14 , wherein at a sample time, the fourth switch is activated to couple the second reference voltage to the first electrode plate of the second capacitor.

To 18. The sample time, the voltage generated between the second first electrode plate and second electrode plate of the capacitor, the second reference voltage and the first amplifier self The comparing means according to claim 16 , which is a difference from a bias voltage.

To 19. The sample time, the second switch and the fourth switch comparison means of claim 14 that does not perform the binding become inoperative.

To 20. There retention time following the sample time, the first switch according to claim 14 which does not bind the analog input signal becomes inoperative to the first electrode plate of said first capacitor Means of comparison.

21. Comparing means according to claim 14 , wherein during said holding time said third switch is deactivated and disconnects said threshold voltage source from the second electrode plate of said first capacitor.

To 22. The retention time, the second switch and the fourth switch comparison means according to claim 14 which is left not performed bonded in inoperative.

23. The comparing means according to claim 14 , wherein during the holding time, the fifth switch, the sixth switch and the seventh switch are activated and remain engaged.

To 24. The retention time followed some retention shift time, claim 1, wherein said second switch for coupling said first reference voltage to the first electrode plate of said first capacitor
4. The comparison means described in 4 .

25. The voltage generated in the second electrode plate of the first capacitor during the holding / shifting time is the magnitude of the first reference voltage and the magnitude of the analog input signal, and the threshold voltage source. 25. The comparing means according to claim 24 , which is a magnitude obtained by adding the magnitude of the threshold voltage to the difference from the magnitude of the threshold voltage.

To 26. The holding-shift time, the first,
15. Comparing means according to claim 14 , wherein the third and fourth switches are deactivated and left uncoupled.

To 27. The time comparison in the following the retention-shift time, the fifth switch comparison means of claim 14 that does not perform the binding become inoperative.

To 28. The comparison time, claim 14 that binds to actuated the fourth switch and the second electrode plate of the first capacitor to the first electrode plate of said second capacitor
The comparison means described in.

29. voltage applied to the amplifier input terminal, the total size of the magnitude and the threshold voltage source self-bias voltage of the amplifier means of said first reference voltage magnitude and the analog input 15. The comparison means according to claim 14 , wherein the comparison result has a magnitude that is added to the difference from the signal and the magnitude of the second reference voltage is subtracted from the result.

30. The magnitude of the second reference voltage is equal to the magnitude of the threshold voltage source added to the comparison voltage which is the smallest increment of the voltage from the first voltage source. The comparison means according to claim 29 .

31. latching amplifier means, if the magnitude of the analog input signal is the first state is greater than the difference between the first reference voltage and the comparison voltage, if the analog input signal magnitude the first 31. The comparing means according to claim 30 , wherein the comparing means is in the second state if it is smaller than the difference between the reference voltage and the comparison voltage.

32. A method of semi-pipelining converting a continuous analog input signal into a series of digital output codes representative of its magnitude, comprising: a) at a first time, converting the continuous analog input signal into a first sample and Sampling into a second sample, b) comparing the first sample with a plurality of coarse reference voltages to form a coarse thermometer code at a second time, and c) simultaneously with the second sample. Holding a sample of d), d) selecting and shifting the plurality of coarse reference voltages at a third time, and e) providing one or more of the plurality of coarse reference voltages at a fourth time. Comparing the second sample with a difference from a fine reference voltage to form a fine thermometer code; and f) encoding the coarse and fine thermometer codes to form one of the digital output codes. , G) the above Method characterized by comprising forming a sequence of digital output code by repeating a floor continuously, the.

Claims (46)

[Claims] 1. A semi-pipelined analog-to-digital converter for converting a continuous analog input signal into a series of first and second digital output codes, comprising: a) coarse analog for converting the analog input signal into a coarse digital code. A digital converter, b) a coarse reference voltage generator for generating a first plurality of reference voltages, c) a fine reference voltage generator for generating a second plurality of reference voltages, and d) a first conversion. A first fine analog-to-digital converter for converting the analog input signal into a first fine digital code in time; and e) converting the analog input signal into a second fine digital code in the second conversion time. A second fine analog-digital converter, and f) a coarse range selection for selectively applying one of the first plurality of reference voltages to the first and second fine analog-digital converters. Switching means: g) at the first conversion time, the coarse digital code and the first fine digital code to a first digital output code, and at the second conversion time, the coarse digital code and the coarse digital code. And an output encoding means for encoding the second fine digital code into the second digital output code. 2. The converter of claim 1, wherein the first conversion time and the second conversion time alternate in time. 3. The converter according to claim 1, wherein each digital output code of the series of digital output codes is a binary number consisting of a plurality of most significant bits and a plurality of least significant bits. 4. The converter of claim 3, wherein the coarse digital code determines the most significant bit. 5. The converter of claim 3, wherein the first and second fine digital codes determine the least significant bit. 6. The coarse reference voltage generator comprises: a) a first reference voltage source; b) a first resistor coupled to the first reference voltage source; and c) a first reference voltage source. D) a final resistance coupled to the second reference voltage source, and e) a first plurality of resistances connected in series between the first resistance and the final resistance. The converter of claim 1 having. 7. The first resistor, the first plurality of series-connected resistors, and the last resistor generate a voltage at each junction of the first plurality of series-connected resistors. Item 7. The converter according to Item 6. 8. The converter of claim 7, wherein each voltage generated at each junction of the first plurality of series-connected resistors is one of the first plurality of reference voltages. 9. The fine reference voltage generator comprises a plurality of series-connected resistors between the last resistance, the plurality of series-connected resistors, and the connection of the second reference voltage source. The converter of claim 1 connected in parallel to one. 10. The converter of claim 1, wherein the fine reference voltage generator comprises a second plurality of series connected resistors. 11. The converter according to claim 10, wherein the voltage generated at each junction of the second plurality of series-connected resistors is one of the second plurality of reference voltages. 12. The first and second fine analog-to-digital converters include: a) a comparison input terminal to which the analog input signal is applied;
A first reference terminal to which one of the first plurality of reference voltages is applied, a second reference terminal to which one of the second plurality of reference voltages is applied, a comparison output terminal that outputs a comparison output signal, And a plurality of voltage comparators each having voltage comparator means for generating a comparison output signal, and b) encoding means for converting the comparison output signals from the plurality of voltage comparators into the fine digital code. The converter according to item 1. 13. The comparison output signal is in a first state if the voltage on the comparison input terminal is greater than the difference between the voltages on the first and second reference terminals, and on the comparison input terminal. 13. The converter of claim 12, in a second state if the voltage is less than the difference between the voltages on the first and second reference terminals. 14. The converter according to claim 1, wherein the first conversion time and the second conversion time are alternately repeated to perform conversion of the continuous analog input signal into the series of digital output codes. . 15. A voltage comparison means for generating an output comparison signal by comparing an analog input signal with a first reference voltage and a second reference voltage, wherein: a) an input terminal to which the analog input signal is applied. B) a first reference terminal to which the first reference voltage is applied, c) a second reference terminal to which the second reference voltage is applied, d) a threshold voltage source, and e) A first capacitor consisting of a first electrode plate and a second electrode plate; f) a first switch for selectively coupling the input terminal to the first electrode plate of the first capacitor; g) The first reference terminal is connected to the first capacitor of the first capacitor.
A second switch selectively coupled to the electrode plate of the first capacitor; and h) connecting the threshold voltage source to the second capacitor of the first capacitor.
A third switch selectively coupled to the electrode plate, i) a second capacitor composed of a first electrode plate and a second electrode plate, and j) the second reference terminal connected to the second capacitor. First of
A fourth switch selectively coupling to the electrode plate of the second capacitor, and k) a fifth switch selectively coupling the second electrode plate of the first capacitor to the first electrode plate of the second capacitor. L) amplifier means including an amplifier input terminal, an amplifier output terminal, an amplifier means for amplifying a signal applied to the amplifier input terminal and supplying the amplified signal to the amplifier output terminal, m) the amplifier A comparison output terminal that is connected to the output terminal and supplies an output comparison signal. 16. At a sample time, a first switch is activated to couple the analog input signal to a first electrode plate of the first capacitor, and a third switch is activated to activate the threshold. The value voltage source is the second capacitor of the first capacitor.
16. The comparing means according to claim 15, which is connected to the electrode plate of. 17. The voltage between the first electrode plate and the second electrode plate of the first capacitor is the difference between the analog input signal and the threshold voltage source. Described comparison means. 18. Comparing means according to claim 15, wherein at a sample time the fourth switch is activated to couple the second reference voltage to the first electrode plate of the second capacitor. 19. The voltage generated between the first electrode plate and the second electrode plate of the second capacitor at the sample time is the self-voltage of the second reference voltage and the first amplifier plate. The comparison means according to claim 18, which is a difference from a bias voltage. 20. The comparing means according to claim 15, wherein at the sample time, the second switch and the fourth switch are inactive and do not combine. 21. At a hold time following the sample time, the first switch is inactive and does not couple the analog input signal to the first electrode plate of the first capacitor. Means of comparison. 22. The comparing means according to claim 15, wherein during the holding time, the third switch is deactivated to disconnect the threshold voltage source from the second electrode plate of the first capacitor. 23. Comparing means according to claim 15, wherein during the holding time the second switch and the fourth switch are deactivated and left uncoupled. 24. Comparing means according to claim 15, wherein during the holding time the fifth switch, the sixth switch and the seventh switch are left in the actuated coupling state. 25. The second switch couples the first reference voltage to the first electrode plate of the first capacitor during a holding / shifting time that follows the holding time.
5. The comparison means described in 5. 26. The voltage generated in the second electrode plate of the first capacitor during the holding / shifting time is the magnitude of the first reference voltage and the magnitude of the analog input signal, and the threshold voltage source. 26. The comparing means according to claim 25, which is a magnitude obtained by adding the magnitude of the threshold voltage to the difference from the magnitude of the threshold voltage. 27. In the holding / shifting time, the first,
16. Comparing means according to claim 15, wherein the third and fourth switches are deactivated and left uncoupled. 28. The comparing means according to claim 15, wherein at a certain comparison time following the holding and shifting time, the fifth switch is deactivated and does not engage. 29. At the comparison time, the fourth switch is activated to couple the second electrode plate of the first capacitor to the first electrode plate of the second capacitor.
The comparison means described in. 30. The voltage applied to the amplifier input terminal is the sum of the magnitude of the self-bias voltage of the amplifier means and the magnitude of the threshold voltage source, the magnitude of the first reference voltage, and the analog input. 16. The comparing means according to claim 15, wherein the comparing means has a magnitude that is added to the difference from the signal and the magnitude of the second reference voltage is subtracted from the result. 31. The magnitude of the second reference voltage is equal to the magnitude of the magnitude of the threshold voltage source added to the comparison voltage which is the smallest increment of the voltage from the first voltage source. The comparison means according to claim 30. 32. The latching amplifier means is in the first state if the magnitude of the analog input signal is greater than the difference between the first reference voltage and the comparison voltage, and the magnitude of the analog input signal is the first state. 32. The comparing means according to claim 31, wherein a second state is established when the difference between the reference voltage and the comparison voltage is less than the second state. 33. A method of semi-pipelining converting a continuous analog input signal into a series of digital output codes representative of its magnitude, comprising: a) at a first time, converting the continuous analog input signal into a first sample and Sampling into a second sample, b) comparing the first sample with a plurality of coarse reference voltages to form a coarse thermometer code at a second time, and c) simultaneously with the second sample. Holding a sample of d), d) selecting and shifting the plurality of coarse reference voltages at a third time, and e) providing one or more of the plurality of coarse reference voltages at a fourth time. Comparing the second sample with a difference from a fine reference voltage to form a fine thermometer code; and f) encoding the coarse and fine thermometer codes to form one of the digital output codes. , G) the above Method characterized by comprising forming a sequence of digital output code by repeating a floor continuously, the. 34. The method of claim 33, wherein each digital output code of the series of digital output codes is a binary number consisting of a plurality of most significant bits and a plurality of least significant bits. 35. The method of claim 33, wherein the coarse thermometer code determines the most significant bit. 36. The method of claim 33, wherein the precision thermometer code determines the least significant bit. 37. The coarse reference voltage is generated by a coarse reference voltage generator, the coarse reference voltage generator comprising: a) a first reference voltage source; and b) being coupled to the first reference voltage source. A first resistor being present, c) a second reference voltage source, d) a last resistor coupled to the second reference voltage source, and e) a series between the first resistor and the last resistor. 34. The method of claim 33, comprising a first plurality of resistors connected to. 38. The first resistor, the first plurality of series-connected resistors, and the last resistor generate a voltage at each junction of the first plurality of series-connected resistors. Item 38. The method according to Item 37. 39. The method of claim 38, wherein each voltage developed at each junction of the first plurality of series connected resistors is one of the coarse reference voltages. 40. The fine reference voltages are generated by a fine reference voltage generator, the fine reference voltage generator comprising: the last resistor, the plurality of series-connected resistors, and the second reference voltage. 38. The method of claim 37, connected in parallel to one of the plurality of series connected resistors between source connections. 41. The method of claim 33, wherein the fine reference voltage generator comprises a second plurality of series connected resistors. 42. The method of claim 41, wherein the voltage developed at each junction of the second plurality of series connected resistors is one of the fine reference voltages. 43. The method of claim 33, wherein the comparing of the first samples is performed at the first analog-to-digital converter. 44. The comparison of the second sample is performed in a second analog to digital converter, the second analog to digital converter comprising: a) a comparison input terminal to which the analog input signal is applied;
A first reference terminal to which one of the first plurality of reference voltages is applied, a second reference terminal to which one of the second plurality of reference voltages is applied, a comparison output terminal that outputs a comparison output signal, And a plurality of voltage comparators each having voltage comparator means for generating a comparison output signal, and b) encoding means for converting the comparison output signals from the plurality of voltage comparators into the fine digital code. Item 33. The method according to Item 33. 45. The output signal is in a first state if the voltage on the comparison input terminal is greater than the difference between the voltages on the first and second reference terminals, and the voltage on the comparison input terminal is 45. The method of claim 44, wherein is a second state if is less than the difference between the voltages on the first and second reference terminals. 46. By the completion of the steps of the method,
34. The method of claim 33, wherein the iteration can be initiated.