TW293204B - A like-series analog digital converter - Google Patents

Abstract

A like-series analog digital converter for transferring the continuous analog input signals into the series of first and second digital output codes, which includes: 1. A coarse analog digital converter for transferring the analog input signals into the coarse digital codes; 2. A coarse reference voltage generator for generating a first set of reference voltage; 3. A fine reference voltage generator for generating a second set of reference voltage; 4. A first fine analog to digital converter for transferring the analog input signals into a first fine digital codes in the first period of the transferring time; 5. A second fine analog to digital converter for transferring the analog input signals into a second fine digital code in the second period of the transferring time; 6. A coarse region selection logic device for selecting one voltage among the first set of reference voltage and connecting to the first and second fine analog to digital converter; 7. An output encoding device for encoding the coarse digital code and the first fine digital code into a first digital output code in the period of the first transferring time, and encoding the coarse digital code and the second fine digital code into a second digital output code in the period of the second transferring time.

Description

393204 Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs ^ A7 B7 V. Description of the invention (/) Scope of the invention The present invention relates to an analog-to-digital converter and its conversion method, more specifically, it refers to multi-level parallel conversion The first conversion stage is used to determine the rough range of the input voltage, and the subsequent conversion stage then solves the analog input signal to a more accurate increment. The invention can be applied to the field of video and digital signal processing. Description of the Related Art The application of digital processing and transmission of analog data requires the conversion of the analog form into a digital representation. The types of analog digital converters commonly known are parallel comparator type or flash converter. It compares the relationship between multiple reference voltages and input voltages, and outputs the result from the coding logic. In each conversion, the digital code Represents the reference voltage closest to the input voltage; the converter of the gradually approaching comparator uses a digital analog converter to try to approximate the input by mistake to generate the digital output code. Figure 1a is a flash converter. The output code is usually a binary code, which is created by coding logic 3G and provides n-bit resolution to represent the input signal. This architecture usually requires 2′η reference voltages 10 and 2, and 20 comparators. When the resolution of this type of comparator is higher (the number of output bits increases), the design becomes extremely complicated. FIG. 1b shows a gradually tracking analog-to-digital converter. The analog input signal vin is input to the sampling and holding circuit 50, and the sampled input signal 55 is the input of the comparator 60. The data encoder 70 sets the maximum effective bit 9Qd of the output word group 9Ga ... 9Gd to logic 1, while the other bits 9Ga, 9Gb, 9Gc are logic 0. The output signal 85 of the digital-to-analog converter 80 represents the midpoint voltage of the voltage range of the digital-to-analog converter 80. If the output voltage 85 of the digital-to-analog converter 80 is greater than the sampled analog signal 55, the output of the comparator 60 becomes a logic 0 'and the clock signal is not blocked by the AND gate 65. The data encoder 70 sets the maximum effective size of the paper. The Chinese national standard (CNS) A4 specification (210X297 mm) is applicable ---------- ^ — (please read the precautions on the back before filling this page) Bookmark ^^ 3204 Employee Consumption Cooperation of the Central Bureau of Economics of the Ministry of Economics, A7 B7. V. Description of invention (2) Bit 90d is logic 0, and the next largest valid bit 9Gc is logic 1. The output voltage of the output 85 of the digital analog converter 80 is 1/4 of the voltage range of the digital analog converter 80. The comparator 60 compares the output 85 of the digital-to-analog converter with the sampled analog input signal 55. If the output voltage 85 of the digital-to-analog converter 80 is less than the sampled analog input signal, the comparator 60 will generate an output logic one. AND gate 65 will prevent the clock signal from passing, and the next most significant bit 9Gc will remain at logic 1, and the next least significant bit will be set to logic 1. This process of trying and setting the output bits 90a, ..., 90d will be carried out until all the bits have been determined, which can represent the size of the input signal sampled. Only when the process is completed, the output bits 9Ga, ..., 9Gd need to be checked by the output line. Approaching analog-to-digital converters require different sample-and-hold circuits, while a complex digital-to-analog converter increases the likelihood of errors. To simplify the design of flash analog-to-digital converters, two techniques are known to be used. Both of these multi-level conversion techniques can be used to complete the conversion of analog digits. In the first technique, such as US Patent No. 5302869 (Hosotani et al.), US Patent No. 5389929 (Nayebi et al.), US Patent No. 5353027 (Vorenkamp et al.), US Patent No. 53693G9 (Bacrania et al. ), As shown in US Patent No. 5387914 (Mangclsdof), the first stage is the rough resolution of the flash analog-to-digital converter; the second stage with the digital-to-analog converter adjusts the reference voltage of the voltage comparator to complete the analysis Better conversion. The results of these two conversions are then encoded into digital output bytes to represent the magnitude of the analog input voltage. In the second technology, such as US Patent No. 5291198 (Dingwair et al.), US Patent No. 5223836 (Komatsu), US Patent No. 5400029 (Kobayashi), US Patent No. 4733217 (DingWaii), US Patent No. .5349354 (Ho et al.) Shows that this technique using multiple conversion stages uses decision logic to switch the reference voltage to each stage appropriately based on the result of the previous comparison stage. Take the second multi-level conversion technology as an example, please refer to Figure 2, which is a US patent. The paper size is applicable to the Chinese National Standard (CNS) M specification (210X29.7mm) (please read the notes on the back before filling in This page). Packing. Order A7 B7 Printed by the Consumer Standardization Bureau of the Central Standards Bureau of the Ministry of Economic Affairs V. Invention Instructions (3) No.4903028 (Fukashima) circuit diagram, it first generates a set of voltage sources, which is generated by V-REFBOT (minimum Value) is gradually increased to V-REFTOP (highest value) to establish the conversion range of the voltage input (Vin). A set of coarse range comparators 2 are connected to the rough range of la, lb of Vin established by the input voltage and a set of reference voltages in separate intervals. The output of the coarsely divided domain comparator 5 is the input of the control logic and the switching unit 3, which can connect a set of finely divided domain comparators 4 to the appropriate range 1 of the reference voltage. This set of reference voltages ia is divided into finer increments' to establish the maximum resolution of converting Vin to digital output {D0, D1, D2 ..., Dn}. When Vin changes, the value of the output code or the output code of the coarse sub-domain comparator 5 also changes, and the control logic and the switching unit 3 also move the fine differential domain comparator 4 to the next sub-domain range (from la to lb) . Due to the different tolerances in component selection and process drift, the output code 5 of the coarsely divided domain comparator 2 may be wrong. In order to check this error, additional fine differential domain comparators 4a and 4b are required, which will be placed next to sub-domain ia or lb depending on the size of Vin, respectively. The output codes of the additional fine differential domain comparators 4a and 4b are error correction codes 7, and this set of coarse sub-domain codes is determined by the output coding logic 8 to determine the digital output representative codes of the input voltage Vin {D0, D1, D2, ..Dn}. An analog-to-digital converter has a very important component as a voltage comparator, which is known to those skilled in the art as 'it includes an operational amplifier' with one input terminal connected to a reference voltage source and the other input terminal If the analog voltage signal is greater than the reference voltage source, the output can be assumed to be in the first logic state. However, if the analog voltage signal is less than the reference voltage source, the output will assume the second logic state. For another type of comparator, please refer to another patent application that is the same as the applicant of this application. The application number is 841,061,172. Use multiple comparators to form a double fractional comparison To compare the analog voltage signal and the reference voltage. (Please read the precautions on the back before filling in this page). Install. • IT — ^ 1 --- Γ XV. *-'Β makes the paper size suitable for financial standards and standards (CNS) A4 specifications (210 ^^ jy A7 B7 293204 V. Description of Invention (Bucket) Brief Description of the Invention One purpose of the present invention is to reduce the size and complexity of the actual implementation of a parallel analog-to-digital converter; another object of the present invention is to eliminate the gradual approach of analog-to-digital conversion The digital class in the device _Ya and E-Tear line; in addition, this repurchase-the settling time required to improve the reference voltage generator of the parallel analog digital converter ° To achieve these purposes, it seems like a series The column-type analog-to-digital converter has a rough analog-to-digital converter that changes legs f | The job title is a little bit painful, and the first two sub-classes Code; a _ reference axis charm creation record-lung test Ju to _ analog digital converter; a fine reference voltage generator to establish a second set of reference voltage, connected to the first and second analog digital converter. The rough reference voltage generator is connected roughly Reference voltage switching device, which can select one of the rough reference voltages of the operation group to connect to the second and second fine analog digital converters. The position of the rough reference voltage is determined by the value of the rough digital code. An output code袈 遛, convert the coarse digital code and the first and second fine digital codes into the output digital code to represent the magnitude of the analog input voltage ^ The fine digital code is generated in the first fine analog digital converter at the first-conversion time And the second conversion time is generated by the second subtle analog-to-digital converter. The first conversion time and the second conversion time are carried out interactively to convert the continuous analog voltage signal into a continuous digital output code. This paper scale is applicable to China National Standard (CNS) Α4 specification (210Χ297mm) (please read the precautions on the back before filling this page) -Shen. Employees of the Central Bureau of Standards of the Ministry of Economic Affairs Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economy Consumer Cooperation Du Printed 293204 A7 B7 V. Description of the invention (friends) A brief description of the figure Circuit diagram of a digital or flash analog digital converter. FIG. 1b is a circuit diagram of a gradually approaching analog digital converter in the conventional technology. FIG. 2 is a functional block diagram of a two-step analog digital converter in the conventional technology. Fig. 3 is a functional block diagram of a tandem analog-to-digital converter of the present invention. Figs. 4a and 4b are functional block diagrams of a voltage comparator of the present invention. Fig. 5 a-5d are voltage comparators of the present invention. The circuit diagram shows the operating conditions of the process of analog digital conversion. Figure 6 is a timing diagram of the present invention, showing the time steps of the analog digital conversion method. Figure 7 is the resolution diagram of the fine digital code of the present invention. Referring to FIG. 3, the analog input voltage (Vin) 150 is applied to the coarse analog digital converter 400 and the fine analog digital converters 401 and 402. Vinl50 is sampled at the first time increment and held in the coarse analog digital converter 400 and the fine analog digital converters 401 and 402. The sampled Vin 150 is compared with the voltage generated by the resistor divider network in the rough analog-to-digital converter at the second time increment. This voltage divider network is a rough reference voltage generator 100. The resistor divider network is connected between two reference voltage sources Vrb 120 and Vrt 130. The comparison result between Vin 150 and the rough reference voltage generator forms a temperature scale (temperature scale is a binary code, the code is formed by consecutive numbers, when the code increases, the number of consecutive 1s also increases, such as the paper size Applicable to China National Standard (CNS) A4 specification (210X297mm) (please read the precautions on the back before filling in this page)-Pack. Order A7 B7 printed by Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Invention Instructions (6) 0000 is the lowest code 0001 0011 0111 1111 is the highest code). This is roughly 475. The coarse digital code 475 is passed to the switch selection logic 300 to select the reference voltage of the coarse reference voltage generator 1GG and is connected to the fine analog digital converters 401 and 402. Switches 301, 302, 303 and 304 will be activated to connect the reference voltage of the appropriate rough reference voltage generator 100 to the fine analog digital converters 401 and 402. The subtle reference voltage generator 20 () is another resistor divider network. It can be connected in parallel with the resistor 101 in the rough reference voltage generator 100. The reference voltage of each subtle reference voltage generator 200 is connected to the subtle analog digital converters 401 and 402. At the third and fourth time increments, the analog input signal 150 is compared with the selected voltage difference between the coarse reference voltage 350 and the fine reference voltage generator 200. The comparison results in a temperature scale, which is the fine digital codes 425 and 450. The coarse digital code 475 and the fine digital codes 425 and 450 are converted into the output digital code 510 in the output encoder 500. The output digital code 510 is a binary number, with a set of maximum significant bits determined by the coarse digital code 475 and a set of minimum effective bits determined by the fine digital code 425 or 450. The output digital code 510 is generated and held during the fifth and sixth time increments. A conversion cycle contains the first to sixth time increments, and is executed repeatedly to form a continuous digital output code to represent the sample size of Vin 150. The fine analog digital converter 401 generates a fine digital code 425 in one conversion cycle. In another conversion week, the paper standard is applicable to China National Standards (CNS) A4 (2〇〇297 public daughter) {--------- ^ — (please read the precautions on the back before filling this page) Order 293204 A7 B7 printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Invention description (7) Period, the subtle analog-to-digital converter 402 generates a subtle digital code 450. This interaction uses subtle analog-to-digital converters 401 and 402 to allow processing at the beginning of the next conversion cycle while the previous conversion cycle is still being processed. This approach allows sampling to be performed at twice the speed of a single analog-to-digital converter. Each subtle analog-to-digital converter 401 and 402 is composed of a group of comparator units 410. Figures 4a and 4b each show the circuit diagram of this comparator unit. The analog input signal Vin is connected to the first terminal of a metal oxide semiconductor field effect transistor (MOSFET) switch 600. The voltage (Vrl) 645, which is the selected rough reference voltage (350 in FIG. 3), is connected to the first terminal of the MOSFET switch 640. The voltage (Vr2) 655, which is a point in the fine reference voltage generator (200 in FIG. 3), is connected to the first terminal of the MOSFET switch 650. The critical reference voltage 635 is connected to the first terminal of the MOSFET switch 630. The capacitor 620 is connected between the second terminal of the MOSFET switches 600, 640 and the second terminal of the MOSFET switch 630. The MOSFET switch 670 is connected between the second end of the MOSFET switch 630 and the second end of the MOSFET switch 650. The first terminal of the capacitor 660 is connected to the second terminal of the MOSFET switches 650 and 670. The second terminal of the capacitor 660 is connected to the input terminal of the amplifier 73G. The output end of the amplifier 730 is the comparator circuit output Vo 715, which is a single bit, and can form a fine digital code (425 and 450 in FIG. 3). The amplifier 730 may be implemented according to application needs. In FIG. 4a, the input terminal of the amplifier 730 is connected to the first terminal of the MOSFET switch 685, and the input terminal of the amplifier 680. The second terminal of the MOSFET switch 685 and the output terminal of the amplifier 680 are connected to the first terminal of the capacitor 690. The second terminal of the capacitor 69G is connected to the first terminal of the MOSFET switch 695 and the input terminal of the amplifier 7GG. The second terminal of the MOSFET switch 695 and the output terminal of the amplifier 7GG are connected to the input terminal of a latching amplifier 71 {). The output terminal of the latch amplifier 710 is the output of the amplifier 730. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 gong) (please read the precautions on the back and fill in this page). Install. * Vs The A7 B7 is printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. V. Description of invention (沄) Figure 4a shows three inverters 68G, 7GG and 71G. Each inverter is used as an amplifier, and the number of stages can be changed according to the needs of the application. FIG. 4b is another design method of the amplifier 730. The input terminal of the amplifier 730 is the first terminal of the MOSFET switch 750 and the negative input terminal of the operational amplifier 740. The positive input terminal of the operational amplifier 740 is connected to the reference power, so that the operational amplifier can be set as a voltage comparator. The second terminal of the MOSFET switch 750 and the output of the operational amplifier 740 are connected together to form the output of the amplifier 730. The MOSFET switches 600, 630, 640, 650, 670, 685, 695 and 750 are all controlled by the timing control signal 720. The mode of operation of the comparator in Figure 4 is shown in Figures 5a-5d. Figure 5a is the first time increment, the comparator starts sampling Vin 605. MOSFET switches 600, 630, 650, 685, and 695 are turned on, and MOSFET switches 640 and 670 are not turned on. The voltage across the capacitor 620 is Vin-Vthref. The voltage across the capacitor 660 is Vr2_Vth2 (where Vth2 is the self-biasing of the amplifier 680). The amplifier 700 is also biased on the self-bias voltage. Figure 5 b is the second time increment! Comparator operation. The MOSFET switch 600 is not turned on, so that the voltage across the capacitor 62G is kept constant, that is, the voltage of Vin 605 is maintained. During this operation, the switch 630 may be in a conducting or non-conducting state because it does not affect the effective voltage stored in the capacitor 620. Figure 5c shows the operation of the comparator at the third time increment. The MOSFET switch 640 is turned on to connect Vrl 645 to the first terminal A of the capacitor 620. It appears at point B (the second end of capacitor 620) and now becomes Vthref + (Vrl-Vin). The voltage of Vrl 645 is the selected rough reference voltage (350 in Fig. 3). This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X 297mm) ---------- installed --------- set ------ line (please read first (Notes on the back and then fill in this page) A7 B7 of the Consumer Cooperation Cooperation of the Central Standards Bureau of the Ministry of Economic Affairs. V. Invention description (9) At the fourth time increment, the operation of the comparator is shown in Figure 5d. The MOSFET switch 640 remains on, while the Sin 3 "£ 1 'switches 600, 630, 650, 685, and 695 do not turn on. The turned on MOSFET switch 670 connects the second end of the capacitor 620 to the first end of the capacitor 660. A suitable connection will be at Point D, which is the voltage generated at the input of the amplifier 680 (Vth2 + (Vthref + (Vrl-Vin))-Yr2)

Vr2 is set equal to Vthref + k * LSB (where k * LSB is the subtle voltage to be compared), so that the above equation becomes

Vth2 + (Vrl-Vin-k * LSB). Because the input terminals of the amplifiers 680 and 700 are set at their respective bias levels, only the voltage difference Vrl-Vin-k * LSB will be amplified. If VinCVrl-k * LSB, ask the amplifier 710 to output logic 1 at V〇4 715; if Vin> Vrl-k * LSB, the output logic is 0. FIG. 6 is a timing diagram illustrating a tandem analog-to-digital conversion method. At the first time increment of the clock signal (2000), the coarse analog digital converter (2100) samples the analog input signal (2110); the fine analog digital converter (22GG) samples the analog input signal (2210). At the second time increment of the clock signal 2000, the rough analog-to-digital converter 2100 compares the sampled analog input signal with the rough reference voltage (2120). When the appropriate coarse reference voltage is chosen to connect the first fine analog-to-digital converter, the sampled analog input voltage remains at the same time (2200). At the third time increment of the clock signal (2000), an appropriate rough reference voltage is connected to the first fine analog-to-digital converter (2200), as shown in Figure 5c, to shift the voltage. The sampled and shifted analog input signal is compared at the fourth time increment of the clock signal (2000). At the fifth time increment of the clock signal (2000), the results of the coarse and fine comparison (2405) are sent to the output coding logic, which is converted into the output digital code 1 (241Q) and sent to the data output (2400). The output paper size is in accordance with the Chinese National Standard (CNS) A4 specification (210X297mm) ----------- ^-(please read the precautions on the back and then fill out this page). DESCRIPTION OF THE INVENTION (丨 0) A7 B7 bit code 1 (2410) remains valid during the sixth time increment of the clock signal (2GGG). The second comparison cycle begins at the third time increment of the clock signal (2000) 'sampling the analog input signal (2130) by the coarse analog digital converter (21GG)' and the second fine analog digital converter (2300) Sampling the analog input signal (2310) ° The second coarse comparison (2140) and the second data hold (2320) of the second fine analog-to-digital converter occur at the fourth time increment of the clock signal (2000). The second sampling and shifting occurs during the fifth time increment of the clock signal (2000). The coarse digital code and fine digital code of the second conversion will be converted into the output digital code 2 (2420), which will be output in the seventh time increment and maintained to the eighth time increment of the clock signal (2000). Figure 7 illustrates the way to obtain the least significant byte encoding. The rough reference voltage generator (100 in Fig. 3) is regarded as an extension of Vrt (3000) to Vrb (3100) in increments of Vrl (n) (3010) and Vrl (n-1) (3G3G). The fine analog-to-digital converter (401 and 402 in Fig. 3) cuts the coarse increment into a fine increment (3040).

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If the analog input signal (Vin) (3G2G) falls between Vrl (n) (3 () 10) and Vrl (nl) (3030), the rough analog-to-digital converter (400 in Figure 3.) will use Vrl ( n) The comparator with reference potential generates the state "0"; and the comparator with Vrl (nl) as the reference potential generates state "1". The switch selection logic (30G in Fig. 3) will connect Vrl (n) to the subtle analog-to-digital converters (40 in Fig. 3) and 402). The fine analog-to-digital converter (401 and 402 in Figure 3) will obtain the voltage difference Vrl (n) Vin (3G5G) and shift this voltage to the comparison range (3150) of the fine comparator. The magnitude of the voltage 3170 starts from Vthref (3160). The reference voltage Vr2 (k) (3190) is obtained by a fine reference voltage generator (200 in FIG. 3). The output encoder (500 in Figure 3) will get the output code (3180). The present invention uses embodiments in particular to make a descriptive description until it can be implemented, but those skilled in the art should understand that different forms or details can be changed without departing from the spirit of the present invention and applying for patent .

Silk A This paper scale is applicable to China National Standard (CNS> A4 specification (210X 297mm)

I

Claims (1)

2〇32〇4 Λ8 B3 C8 D8 Employee consumption cooperation of the Central Bureau of Economic Affairs of the Ministry of Economic Affairs, printed by Du ☆, patent application scope 1. A quasi-serial analog digital converter 'that converts continuous analog input signals into a sequence of first and second digits Output code, including a) — a rough analog digital converter ”to convert the analog input signal to a rough digital code; b) — a rough reference voltage generator to generate the first set of reference voltages; c) a fine reference voltage Generator, used to generate the second set of reference voltages; d) The first fine analog digital converter converts the analog input signal into the first fine digital code at the first conversion time; e) The second fine analog Digital converter, at the second conversion time, convert the analog input signal into the second fine digital code; f) ~ a rough range selection logic device, used to select one of the first set of reference voltages, connected to The first and second subtle analog-to-digital converters mentioned above; g)-an output encoding device 'used to convert the coarse digital code and the first fine digital code in the first Between the first digit output code compiled; the coarse digital code and the second compiled code of the second minute digit output code digits in the second transition time. 2. The converter according to item 1 of the patent application scope, in which the first-to-conversion time and the second to-conversion time will be continuously alternated. 3. The converter according to item 1 of the scope of the patent application, wherein each output code of the serial output code is a binary code 'containing a maximum significant byte and a minimum significant byte. 4. The converter according to item 1 of the patent application scope, in which the rough digital code determines the maximum valid byte. 5. The converter according to item 1 of the patent application park, where the first and second fine digits determine the least significant byte. : | ~ Package: ~ Order ^. (Please read the precautions on the back and then fill out this page) This paper standard is applicable to the Chinese National Standard (CNS) A4 present format (210X297 degrees) ABCD Ministry of Economic Affairs Central Standards Bureau Staff Consumer Cooperative Printed 6. Patent application scope 6 · The converter according to item 1 of the patent application scope, where the rough voltage generator contains: a) the first reference voltage source; b) the first resistor connected to the first reference voltage source ; C) The second reference voltage source; d) The last resistor is connected to the second reference voltage source; and e) The first set of series resistors is connected between the first and last resistors mentioned above. 7. The converter according to item 6 of the patent application, in which the first resistor, the first series resistance and the last resistance all have a voltage at each connection point of the first series resistance. 8. The converter according to the first item in the scope of the patent application, wherein the voltage at each connection point of the above-mentioned first set of series resistances is one of the first set of reference voltages. 9 · The converter according to item 1 of the patent application scope, in which the fine reference voltage generator can be connected between the first resistor, the last resistor, the first set of series resistors and the second reference voltage source. One of a series of resistors is connected in parallel. 1 ◦The converter according to item 1 of the patent application scope, in which the subtle reference voltage generator contains a second set of series resistors. 1 1 · The converter according to item 1Q of the patent application scope, wherein the voltage at each connection point of the above-mentioned second set of series resistors is one of the second set of reference voltages-〇1 2 · According to the application The converter of the first item of the Patent Fan Garden, of which the first and second subtle analog-to-digital converters include:............................ Please read the precautions on the back and then fill out this page) This paper uses the Chinese National Standard (CNS) A4 (210 X 297 mm). The ASB8 C8 D8 is printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economy. Range a) —Group voltage comparators, where each comparator includes a comparison input connected to the analog input signal 'first reference voltage terminal, connected to one point of the first group of reference voltages, and the second reference voltage terminal, connected To one point of the second set of reference voltages, a comparison output sends a comparison result, and a voltage comparison device can generate a comparison output signal; and b)-an encoding device that converts the comparison output signal obtained by a set of voltage comparators A fine micro-digit code. 13. The converter according to item 12 of the scope of patent application 'where the input voltage of the comparison is greater than the difference between the reference voltages of the first and second terminals', the comparison output signal is in the first state; and if the voltage of the input terminal of the comparison Less than the reference voltage difference between the first end and the second end, the comparison output signal is in the second state. 14. The converter according to item 1 of the patent application scope, wherein the first conversion time and the second conversion time are repeated alternately to complete the continuous analog input signal conversion into a serial digital output signal. 1 5 ·-A voltage comparison device for comparing the analog input signal with the first reference voltage and the second reference voltage, and provides an output comparison signal, including: a)-an input terminal, connected to the analog input signal ; B) The first reference terminal, connected to the first reference voltage; c) The second reference terminal, connected to the second reference voltage; d) — a critical voltage source; e) the first capacitor Contains the first metal plate and the second metal plate; 〇The first switch is used to select the first metal plate connecting the input terminal to the first capacitor: This paper standard is applicable to China National Standard (CNS) A4 (210X297 public epidemic) ---------- installed ------ Ί order ----------- (please read the precautions on the back before filling this page) Ministry of Economic Affairs Printed 293204 B8, C8, D8 by Beigongxiao Cooperative of Central Bureau of Standards. 6. Scope of patent application. G) The second switch is used to select the first metal plate connecting the first reference terminal to the first capacitor; h ) The third switch is used to select the second metal plate connecting the junction voltage source to the first capacitor; i) Two capacitors, including the first metal plate and the second metal plate; j) The fourth switch, used to select the first metal plate connecting the second reference terminal to the second capacitor; k) The fifth Switch, used to select the second metal plate connecting the first capacitor to the first metal plate of the second capacitor; l) An amplifier device, including an amplifier input terminal, an amplifier output terminal 'an amplifier device, with To amplify the signal appearing at the input of the amplifier, and send the amplified signal to the output of the amplifier; and m) a comparison output, connected to the output of the amplifier to provide the output comparison signal. 16. The comparison device according to item 15 of the patent application, in which the first switch is activated at the sampling time to connect the analog input signal to the first metal plate of the first capacitor, and the third switch is activated to connect The critical voltage source is the second metal plate of the first capacitor. 1 7. The comparison device according to item 16 of the patent application park, wherein the voltage between the first metal plate and the second metal plate of the first capacitor is the voltage difference between the analog input signal and the critical voltage source. 1 8 • The comparison device according to item 15 of the patent application park, in which the fourth switch is activated at the sampling time, connecting the second reference voltage to the first metal plate of the second capacitor. This paper music scale is suitable for China National Standard (CNS) A4 specification (210X297mm) --------- j—installed ----- 丨 ordered ------ ^ body (please read first Note on the back and then fill out this page) Printed AS B8 C8 D8 by the Employees ’Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 6. Scope of patent application _ 1 9 · Comparison device according to patent application _ item 18, which was established at the sampling time The voltage between the first metal plate and the second metal plate of the second capacitor is the difference between the second reference voltage and the self-bias voltage of the first amplifier. 2◦ According to the comparison device of patent application No.15, the second switch and the fourth switch are not activated at the sampling time. 2 1 · The comparison device according to item 15 of the patent application, in which the holding time is after the sampling time, the first switch is not activated, and the analog input signal is not connected to the first metal plate of the first capacitor. 2 2 • The comparison device according to item 1.5 of the patent application circle, in which the third switch is not activated during the hold time, and the critical voltage source is not connected to the second metal plate of the first capacitor. 2 3 _ The comparison device according to item 15 of the patent application park, in which the second switch and the fourth switch are not activated during the hold time. 2 4 • The comparison device according to item 15 of the patent application park, in which the fifth switch, the sixth switch, and the seventh switch maintain the conductive connection during the hold time. 2 5 · Comparative device according to item 15 of patent application fan circle, where after holding time to hold a displacement, the second switch activates the first gold-given board connecting the first reference voltage to the first capacitor . 2 6 · Comparing device according to item 25 of the patent application patent valve, in which the voltage of the second metal plate established in the first correction volume is the size of the critical voltage source plus the first reference while maintaining a displacement time Voltage difference between the electrical source and the analog input signal. 2 7 • The comparison device according to item 15 of the patent application, in which the first, third, and fourth switches remain unactivated while maintaining a displacement time. ---- J ---- 装 -----— 定 ------ Ι 旅 (please read the precautions on the back and then fill in this page) This paper standard is applicable to the Chinese National Standard (CMS) Α4 Specifications (210Χ297 g; t) Printed and printed AS B8 C8 D8 by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs VI. Patent application scope 2 8 · Comparative device according to item 15 of the patent application park, where after a displacement time is maintained as Comparing the time, the fifth switch becomes inactive connection signal. 2 9 • The comparison device according to item 15 of the patent application plan, in which the fourth switch is activated at the comparison time to connect the second metal plate of the first capacitor to the first metal plate of the second capacitor. 3 0 · The comparison device according to item 15 of the patent application scope, in which the voltage established at the input of the amplifier is the self-bias voltage of the amplifier plus the sum of the voltage difference between the critical voltage source and the first reference voltage and the magnitude of the analog input signal. Subtract the magnitude of the second reference voltage. 3 1 · The comparison device according to item 30 of the patent application Fan You, in which the size of the second reference voltage is equal to the size of the critical electrical source plus a comparison voltage, which is the minimum command of the first voltage source ;. 3 2 · Comparative device according to patent application No. 31, where when the magnitude of the analog input signal is greater than the difference between the first reference voltage and the comparison voltage, the latch amplifier device is in the first state; the analog input signal If the magnitude is smaller than the difference between the first reference voltage and the comparison voltage, the latch amplifier device is in the second state. 3 3-A tandem analog-to-digital conversion method that converts continuous analog round-robin signals into the digital output codes represented by it, including the following steps: a) Sampling the continuous analog input signal at the first time, Become the first sample and the second sample; b) Compare the first sample with a Shao.f [Slight reference voltage, produce a rough temperature size at the second time; c) Hold the second sample at the same time; d) At the third time, select f: the pull reference displacement group of rough reference batteries; e) At the fourth time, compare the first sample: the difference between a set of rough reference voltage and a fine reference voltage, Generate…! Μ 丨 Subtle temperature size ^ f) Encode the coarse and subtle temperature K code to produce a digital output code; g) Repeat the above steps repeatedly to produce a continuous digital output code. The silver standard of this paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) ---- ^ ---- ^ —installed -----— order ----- J line (please read the back side first (Notes and then fill out this page) A8 B8 C8 DS • Sixth, the scope of patent application 3 4 · According to the method of patent application item No. 3 3, in which the number of consecutive digital output codes described in each number ((round out The code is a binary number, including a set of maximum effective bits and a set of minimum effective bits. 3 5 · According to the method of item 3 3 of the patent application, the rough temperature size determines the maximum effective bit. 3 6 · According to the method of item 3 and item 3 of the patent application review, the smallest effective byte is determined by the fine temperature size.-^ --- „----“ 装 ------- 定 ----- -(Please read the precautions on the back before filling in this tile) The standard of the paper wave printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs is applicable to the Chinese National Standard (CNS) Α4 specification (210Χ297 mm)