JPH09260630A - Solid-state imaging device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce gate-drain capacitance and reduce also a dark current caused by avalanche by a method, wherein an insulation film on a drain region end in a pixel transistor is formed thicker than a gate insulation film. SOLUTION: After a source region 39 and a drain region 40 are formed utilizing a silicon nitride film 61 formed on a gate insulation film 36, they are thermally oxidized; and on the source region 39 and the drain region 40 which are not covered with the silicon nitride film 61, an insulation film thicker than the gate insulation film 36, namely a thermal oxide film 43, is formed. An insulation film on an end part in which the drain region 40 and a gate electrode 37 are thereby, partially overlapped, an electric field in a vertical direction is weakened near a drain region end. Further, near the drain region end, a drain diffused layer reaching a bird's beak 65 by thermal diffusion becomes a slow impurity distribution, and further, since an electric field in a vertical direction is weakened, it is possible to reduce a generation of a hot carrier due to avalanche when a channel is pinched off.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplification type solid state image pickup device and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, in response to a demand for higher resolution of a solid-state imaging device, an amplification type solid-state imaging device which has no smear and can realize fine pixels has been developed in place of a CCD solid-state imaging device. This amplification type solid-state imaging device includes a MOS type transistor for amplifying an optical signal for each pixel,
A signal is read out by using the electric charge accumulated in the pixel by photoelectric conversion as the current modulation of the transistor.

[0003]

FIG. 10 and FIG.
A first comparative example of the previously proposed amplification type solid-state imaging device will be shown. As shown in FIG. 11, this amplification type solid-state imaging device 1 has a second conductivity type, that is, an n type semiconductor region, that is, an overflow barrier region 3 and a p type, on a first conductivity type, for example, p type silicon semiconductor substrate 2. A semiconductor well region 4 is formed, and a ring-shaped gate electrode 6 capable of transmitting light is formed on the p-type semiconductor well region 4 through a gate insulating film 5 made of SiO ₂ or the like, and the center of the ring-shaped gate electrode 6 is formed. The gate electrode 6 is formed in the p-type semiconductor well region 4 corresponding to the hole and the outer periphery.
An n-type source region 7 and a drain region 8 are formed by self-alignment using the mask as a mask, and a MOS type transistor (hereinafter referred to as a pixel MOS transistor) 9 which constitutes one pixel is formed therein. The ring-shaped gate electrode 6 is
A thin or transparent material is selected so as not to absorb light as much as possible. In this example, a thin film of polycrystalline silicon is used.

This pixel MOS transistor 9 is shown in FIG.
As shown in FIG. 2, the source regions 7 of the pixel MOS transistors 9 arranged in a matrix and corresponding to each column are connected to a common signal line 11 formed by, for example, the first layer Al formed along the vertical direction, A vertical selection line 12 made of, for example, the second layer Al is formed in the horizontal direction at a position corresponding to each row of the pixel MOS transistors 9 so as to be orthogonal to the signal line 11.

[0005] Two horizontally adjacent pixels M
For example, a V-shaped inter-pixel wiring layer 13 is formed so as to straddle the annular gate electrodes 6 of the OS transistor 9 and extend to the corresponding vertical selection line 12, and both ends of the inter-pixel wiring layer 13 are formed. The two pixel MOS transistors, that is, the gate electrodes 6 and 6 thereof are electrically connected, and the intermediate portion is electrically connected to the vertical selection line 12.
Reference numeral 14 is a contact portion between the inter-pixel wiring layer 13 and the vertical selection line 12, and 15 is a contact portion between the inter-pixel wiring layer 13 and the gate electrode 6. Reference numeral 16 is a contact portion between the source region 7 and the signal line 11.

Further, a drain power source line 18 made of, for example, the first layer Al and connected to the drain region 8 is formed between the pixel MOS transistors 9 not extending over the inter-pixel wiring layer 13. Reference numeral 17 is a contact portion between the drain region 8 and the drain power supply line 18. Reference numeral 19 denotes a pixel area in which the pixel MOS transistor 9 is formed.

The pixel MOS transistor 9 shown in FIG.
As shown in FIG. 1, the light transmitted through the ring-shaped gate electrode 6 is photoelectrically converted in silicon to generate electrons-holes, and one of the charges, in this example, the hole h is a ring-shaped signal charge. It is accumulated in the p-type semiconductor well region 4 below the gate electrode 6. When a high voltage is applied to the ring-shaped gate electrode 6 through the vertical selection line 12 and the pixel MOS transistor 9 is turned on, a drain current (so-called channel current) Id flows to the surface channel, and this drain current Id is the signal charge h. The drain current Id is output through the signal line 11 and the amount of change is used as a signal output.

FIGS. 8 and 9 show a second comparative example of a further improved amplification type solid-state image pickup device. This amplification type solid-state image pickup device 21 has
Below the source region 7 and the drain region 8, the source region 7
And n-type impurity regions 24 and 25 of the same conductivity type as the drain region 8 are formed, and a p-type charge accumulation well having a higher impurity concentration than the p-type semiconductor well region 4 is formed in a region corresponding to the channel under the gate electrode 6. A region, a so-called sensor well region 26, is formed. Further, the gate electrodes 6 and 6 of adjacent pixels are connected to each other by the inter-pixel wiring layer 27 made of the same material as that of the gate electrode 6 extending integrally. Other configurations are the same as those in FIGS. 10 and 11 described above, and therefore, corresponding parts will be denoted by the same reference numerals and redundant description will be omitted.

In the pixel MOS transistor 22, charges passing through the gate electrode 6 and photoelectrically converted in silicon,
That is, the holes h are accumulated in the sensor well region 26 below the gate electrode 6. The sensor well region 26 is electrically surrounded by the shallow source region 7 and the drain region 8, the deep impurity regions 24 and 25, and the deeper overflow barrier region 3. Excess accumulated charges h when a large amount of light is received are discharged to the substrate 2 side through the overflow barrier region 3. In order to obtain red sensitivity, the overflow barrier region 3 is usually formed at a deep position of several μm.

Therefore, the deep impurity regions 24 and 25
Must be electrically connected to the shallow source region 7 and drain region 8 and the overflow barrier region 3. That is, the impurity region 25 below the drain region 8
Plays the role of releasing the charges on the non-accumulation side of the electrons and holes that have been photoelectrically converted to the shallow drain region 8 and also serving as a potential barrier for preventing blooming with adjacent pixels.

In forming the pixel MOS transistor 22, since the gate electrode 6 is thin and does not serve as an ion implantation mask when forming a deep impurity region, another resist mask is used before forming the gate electrode.
At the same time, ions are implanted to simultaneously form the shallow source region 7 and drain region 8 and the deep impurity regions 24 and 25 in a self-aligning manner. After that, a polycrystalline silicon layer to be the gate electrode 6 is formed and patterned using another resist mask to simultaneously form the gate electrode 6 and the inter-pixel wiring layer 27 extending from the gate electrode 6. The contact with the gate electrode 6 is made in the inter-pixel wiring layer 27.

In the amplification type solid-state imaging device 21 as compared with the amplification type solid-state imaging device 1 of FIGS. 10 and 11, the impurity regions 24 and 25 provided below the source region 7 and the drain region 8 in the pixel MOS transistor 22. This surely prevents blooming to adjacent pixels, and
By forming the inter-pixel wiring layer 27 integrally with the gate electrode 6, the conventional inter-pixel wiring layer 13 is omitted, and the wiring structure is simplified.

By the way, in the amplification type solid-state image pickup device 21 shown in FIGS. 8 and 9, as shown in FIG. 9, the insulating film below the inter-pixel wiring layer 27 is the pixel MOS transistor 22.
In addition to being thin, it is usually 1 × 10 ¹³ c through this insulating film when the drain region 8 is formed.
Since a dose of m ⁻² or more is ion-implanted, the dielectric strength is low, and there are problems in terms of manufacturing yield deterioration and reliability.

Further, since the capacitance between the drain and the gate inevitably becomes large, the circuit for driving the gate becomes large, and the crosstalk between the drain and the gate (that is, when a voltage is applied to the gate, the drain potential is increased). However, there was a problem that Therefore, it is necessary to reduce the area of the inter-pixel wiring layer 27.
In order to secure the alignment margin with the contact portion 14 in FIG. 10, there is a limit to the reduction.

As another problem, since the gate insulating film 5 is thin, the electric field in the vertical direction becomes strong near the drain region 8. Therefore, when a channel current flows such as when reading a pixel signal, hot carriers are easily generated by the drain avalanche. This hot carrier is one of the causes of the dark current, and it is very difficult to drive the pixel to suppress the dark current generation.

Further, the hot carriers are generated in the pixel MO.
There is a problem that fixed charges are generated in the insulating film, that is, an oxide film, or an interface state is generated at the end of the drain region of the S-transistor 21, which causes deterioration of image quality with time.

In view of the above points, the present invention more preferably maintains the basic characteristics of the pixel and more preferably forms the impurity region at a position deeper than the source region and the drain region in a serfaline manner. The present invention provides an amplification type solid-state imaging device capable of reducing the gate-drain capacitance and reducing the dark current due to avalanche while maintaining the above, and a manufacturing method capable of manufacturing the amplification type solid-state imaging device with a yield.

[0018]

The amplification type solid-state image pickup device according to the present invention has a structure in which the insulating film on the edge of the drain region of the pixel transistor is formed thicker than the gate insulating film.

In this structure, since the insulating film on the edge of the drain region is formed thicker than the gate insulating film,
The drain-gate capacitance is reduced. Further, the vertical electric field in the vicinity of the drain can be reduced, and the generation of dark current can be suppressed.

In the method for manufacturing an amplification type solid-state image pickup device according to the present invention, after the silicon nitride film on the oxide film which becomes the gate insulating film in the pixel region is patterned into the channel shape of the pixel, the source region and the drain region are formed. Then, a thick oxide film is formed on the source region and the drain region by oxidation treatment, and the silicon nitride film is removed to form a gate electrode.

In this manufacturing method, a thick oxide film is formed on the source region, the drain region, and the like in a self-aligning manner, and the amplification type solid-state image pickup device according to the present invention can be manufactured with high yield.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION In an amplification type solid-state imaging device according to the present invention, an insulating film on a drain region of a pixel transistor, that is, on an end of the drain region where at least a gate electrode partially covers is formed thicker than a gate insulating film. It has a different configuration.

According to the present invention, in the amplification type solid-state imaging device, the gate electrodes of adjacent pixel transistors are connected to each other by an inter-pixel wiring layer extending integrally with the gate electrodes on the insulating film in the drain region. And

A method for manufacturing an amplification type solid-state image pickup device according to the present invention comprises a step of sequentially forming an oxide film and a silicon nitride film to be a gate insulating film in a pixel region, and patterning the silicon nitride film into a pixel channel shape. , Forming source and drain regions, forming an oxide film thicker than the gate insulating film on the source and drain regions by oxidation, removing the silicon nitride film, and forming a gate electrode of the pixel Have steps.

According to the present invention, in the method for manufacturing an amplification type solid-state image pickup device, the source region and the drain region are formed by ion implantation using the resist layer after patterning the silicon nitride film as a mask.

According to the present invention, in the above-described method for manufacturing an amplification type solid-state image pickup device, ion implantation is performed by using the resist layer used for patterning the silicon nitride film as a mask, the source region and the drain region, and the source region and the drain region. The impurity region at a deeper position is formed in a self-aligned manner.

According to the present invention, in the method for manufacturing an amplification type solid-state image pickup device, after removing the silicon nitride film, a charge storage well region (so-called sensor well region) is formed by ion implantation using a thick oxide film as a mask.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

As shown in FIGS. 1 and 2, the amplification type solid-state imaging device 31 according to the present embodiment has a second conductivity type or n type semiconductor layer on a silicon semiconductor substrate 32 of the first conductivity type, for example, p type. That is, an overflow barrier region 33 and a p-type semiconductor well region 34 are formed, and a p-type charge accumulation well region, which is a so-called sensor well region 35, which forms a channel is further formed, and S is formed on the sensor well region 35.
An annular gate electrode 37 capable of transmitting light is formed through a gate insulating film 36 made of iO ₂ or the like, and an ion implantation method is performed on the p-type semiconductor well regions 34 corresponding to the central hole and the outer periphery of the annular gate electrode 37, respectively. The n-type source region 39 and the drain region 40 are formed by the
The OS transistor 41 is configured.

In this example, in the pixel OS transistor 41, an insulating film (so-called oxide film) 43 is formed as an insulating film on the source region 39 and the drain region 40 by the so-called selective oxidation (LOCOS) method. Further, so-called n-type impurity regions 44 and 45 having the same conductivity type as the source region 39 and the drain region 40 are formed below the shallow source region 39 and the drain region 40, respectively. In particular, the impurity region 45 below the drain region 40
In the same manner as described above with reference to FIGS. 8 and 9, the non-accumulation side charges (electrons in this example) of the photoelectrically converted electrons and holes escape to the shallow drain region 40, and A potential barrier for preventing blooming serves as a so-called channel stop region.

In addition, adjacent pixel MOS transistors 4
The first gate electrodes 37, 37 are connected to each other by the inter-pixel wiring layer 47 extending integrally with the gate electrode 37 on the thick insulating film 43 of the drain region 40. Gate electrode 37
The inter-pixel wiring layer 47 is formed of the same electrode material by simultaneous patterning.

The n-type impurity regions 44 and 45 are formed so as to electrically connect the shallow source region 39 and drain region 40 and the overflow barrier region 33, respectively.
For example, the n-type impurity regions 44 and 45 may be formed from the source region 39 and the drain region 40 to the overflow barrier region 33, respectively, or the source region 3
9 so that a potential dip is formed from 9 and the drain region 40 to the overflow barrier region 33,
It may be formed between the source region 39 and the drain region 40 and the overflow barrier region 33.

The impurity concentrations of the n-type impurity regions 44 and 45 are set to be lower than the impurity concentrations of the source region 39 and the drain region 40 and higher than that of the overflow barrier region 33.

On the other hand, regarding the impurity concentration relationship among the p-type semiconductor substrate 32, the p-type semiconductor well region 34, and the p-type sensor well region 35, the sensor well region 35 has the highest impurity concentration, followed by the p-type semiconductor substrate 32 and the p-type semiconductor well. It becomes lower in the order of the region 34.

The ring-shaped gate electrode 37 is made of a thin material or a transparent material so as not to absorb light as much as possible. For example, polycrystalline silicon, tungsten polycide, tungsten silicide or the like can be used. In this example, a thin film of polycrystalline silicon having a good light-transmitting property is used.

The pixel MOS transistor 41 shown in FIG.
As shown in FIG. 2, the source regions 3 of the pixel MOS transistors 41 corresponding to each column are arranged in a matrix.
9 is connected to a common signal line 51 made of, for example, the first layer Al formed along the vertical direction, and is provided at a position corresponding to each row of the pixel MOS transistors 41 so as to be orthogonal to the signal line 51, for example, the second layer. A vertical selection line 52 made of Al is formed along the horizontal direction, and the vertical selection line 52 is connected to the inter-pixel wiring layer 47 connected to the gate electrode.

Further, between the pixel MOS transistors 41 not connected by the inter-pixel wiring layer 47, the drain electrode line 53 made of, for example, the first layer Al connected to the drain region 40 is formed. Reference numeral 55 is a drain contact portion between the drain power supply line 54 and the drain region 40, 56 is a source contact portion between the source region 39 and the signal line 51, and 57 is a contact portion between the inter-pixel wiring layer 47 and the vertical selection line 52. In FIG. 1, reference numeral 58 represents a pixel region in which the pixel MOS transistors 41 are arranged.

The operation of the amplification type solid-state image pickup device 31 is similar to that described above in that the light passing through the ring-shaped gate electrode 37 is photoelectrically converted so that one of the charges, that is, the hole h, is in the sensor well region under the gate electrode 37. It is accumulated in 35. Then, when a high voltage is applied to the ring-shaped gate electrode 37 through the vertical selection line 52 and the pixel MOS transistor 41 is turned on,
A drain current (so-called channel current) flows in the channel on the surface of the sensor well region 34, and the drain current is changed by the signal charge h, so that the drain current is output through the signal line 51 and the amount of change is output as a signal. And

According to the amplification type solid-state image pickup device 31 described above, since the insulating film 43 thicker than the gate insulating film 36 is provided on the drain region 40 and the source region 39, the dielectric breakdown voltage between the gate and the drain and between the gate and the source is increased. It is possible to increase the production yield, improve the production yield, and improve the reliability.

Further, the thick insulating film 43 causes the drain-
The capacitance between the gates is reduced and the drain-gate crosstalk is also reduced. For this reason, the inter-pixel wiring layer 47 can be made to have a sufficient area, and a matching margin with the contact portion 57 can be secured.

Further, the insulating film 4 on the end of the drain region 40
Since 3 is thick, the electric field in the vertical direction becomes weak near the edge of the drain region 40. That is, the electric field concentration is alleviated. Therefore, when a channel current flows such as when reading a pixel signal, the generation of hot carriers due to the drain avalanche is greatly reduced, and the generation of dark current can be reduced.

Since the generation of hot carriers due to the drain avalanche can be reduced, the generation of fixed charges and interface states in the gate insulating film 36 due to hot carriers is also reduced, and the deterioration of image quality over time can be suppressed.

Since the gate electrode 37 and the inter-pixel wiring layer 47 are integrally formed of the same polycrystalline silicon thin film, FIG.
The wiring structure is simplified as compared with the wiring structure in which the inter-pixel wiring layer is separately formed as shown in FIG. In addition, the inter-pixel wiring layer 4
7 and the gate electrode 37 are formed of the same electrode material (polycrystalline silicon thin film), the local change of the channel potential under the contact portion 15 due to the work function difference as shown in FIG. 10 is avoided. This leads to uniform characteristics for each pixel and high image quality. Further, as compared with the structure in which the inter-pixel wiring layer 13 of FIG. 10 is provided separately, the light reception utilization rate is increased and the light reception sensitivity is improved.

Next, an example of manufacturing the above-mentioned amplification type solid-state image pickup device 31 will be described.

In this example, as shown in FIG. 3A, p
After sequentially forming an n-type overflow barrier region 33 and a p-type semiconductor well region 34 on the type silicon substrate 32,
On the surface of the p-type semiconductor well region 34, a gate insulating film 36 made of an oxide film such as SiO ₂ and a silicon nitride film 61 thereon are sequentially formed.

Next, as shown in FIG. 3B, the silicon nitride film 6 is formed using the resist layer 62 patterned into the channel shape of the pixel (that is, the shape of the ring-shaped gate electrode) as a mask.
1 is selectively etched to open portions corresponding to the source region and the drain region.

Next, the shallow n-type source region 39 and the drain region 40 are formed by ion implantation of the first impurity 63 with the resist layer 62 as a mask, and the ions of the second impurity 64 are ionized with the same resist layer 62 as a mask. By implantation, n-type impurity regions 44 and 45 are formed at deep positions. As a result, the source region 39 and the drain region 40 and the corresponding impurity regions 44 and 45 are formed in a self-aligning manner.

The ion implantation energies of the deep impurity regions 44 and 45 can be selected quite freely by forming the resist layer 62 having a thickness that does not penetrate, and can be optimized in terms of devices. If the silicon nitride film 61 can be formed thick enough to be applied to an ion implantation mask, it is possible to perform ion implantation without the resist layer 62.

Next, as shown in FIG. 3C, the resist layer 6
2 is peeled off, a thermal oxidation process is performed with the silicon nitride film left, and an insulating film, that is, a thermal oxide film 43 is formed on the source region 39 and the drain region 40 at least the gate insulating film 3
Grows thicker than six. The region covered with the silicon nitride film 61 is not oxidized and becomes a channel region. As a result, L
A shape close to the shape of the OCOS (selective oxidation) step can be obtained.

Here, if heat treatment is often performed, the source region 39 is formed.
The impurities in the drain region 40 and the drain region 40 are laterally diffused to narrow the sensor well region and the channel region of the pixel MOS transistor, which will be described later, and deteriorate the dynamic range and the gate-off characteristic of the pixel. However, if the thickness of the thermal oxide film 43 is several hundreds nm or less by wet oxidation at 900 ° C. or less, the impurities in the source region 39 and the drain region 40 are not diffused so much in the lateral direction, and the impurity diffusion in the lateral direction is not performed. The length of the bird's beak 65 is about 0.2μ
m can be easily controlled. The bird's beak length is equal to that of the silicon nitride film 61 and the gate insulating film (oxide film) 3
6, which is almost determined by the thick oxide film 43.

Next, as shown in FIG. 4D, after the silicon nitride film 61 is peeled off, ions are implanted using the thick oxide film 43 as a mask to form the p-type sensor well region 35.
The ion implantation energy at this time is the same as the gate insulating film 3
6, but the thick oxide film 43 is not penetrated. However, if the ion-implanted impurities penetrate under the thick oxide film 43, the ion-implantation amount may be increased when the source region 39 and the drain region 40 are first formed.

Further, retrospectively, before patterning the silicon nitride film 61 of FIG. 3A or before growing the silicon nitride film 61, a sensor well region 35 is formed on the entire surface of the p-type semiconductor well region 34 by ion implantation. You can leave it as well. In any case, in the process as it is, the channel, the sensor well region 35, and the source region 39 are completely removed.
The drain region 40 and the deep n-type impurity regions 44 and 45 are formed in a self-aligned manner, and the sensor well region 35 of the pixel is uniformly formed in the pixel.

Next, the gate insulating film 36 and the thick oxide film 4 are formed.
3, a polycrystalline silicon thin film, which is a gate electrode material, is formed on the entire surface, and impurities are doped, and patterning is performed through a mask of a resist layer to form a gate electrode 37 and an inter-pixel wiring of the polycrystalline silicon thin film. Layer 47
To form At this time, the gate electrode 37 is formed so as to partially cover the source region 39 and the drain region 40. Thus, the intended amplification type solid-state imaging device shown in FIG. 4E, that is, the pixel MOS transistor 41 thereof is obtained.

According to the above-described manufacturing method, the pixel channel and
The source region 39 and the drain region 40 and the deep n
The type impurity regions 44 and 45 and the sensor well region 35 can be formed in a self-aligned manner, and pixel characteristics with excellent uniformity can be provided.

By using the silicon nitride film 61 formed on the gate insulating film 36 to form the source region 39 and the drain region 40 and then performing a thermal oxidation process, the source region 39 and the silicon nitride film 61 which are not covered are formed. An insulating film thicker than the gate insulating film 36, that is, a thermal oxide film 43 can be formed on the drain region 40. As a result, the insulating film 43 on the end where the drain region 40 and the gate electrode 37 partially overlap becomes thicker, and the electric field in the vertical direction becomes weaker near the end of the drain region.

Further, in the vicinity of the edge of the drain region, the drain diffusion layer which has reached the bird's beak 65 by thermal diffusion itself has a fairly gentle impurity distribution (so-called broad). Since the electric field perpendicular to the channel current flowing direction becomes weak in the vicinity of, the generation of hot carriers due to the drain avalanche when the channel is pinched off can be effectively reduced. Naturally, this can greatly reduce the generation of fixed charges and interface states in the gate insulating film 36 due to hot carriers.

In general, a silicon oxide film doped with a large amount of impurities generally has a lower withstand voltage than an ideal oxide film, but in this embodiment, an insulating film 43 having a sufficiently large thickness is formed on the drain region 40. Since it can be formed, the breakdown voltage between the gate and the drain does not pose any problem.

Further, the inter-pixel wiring layer 47 and the drain region 4
Since the insulating film 43 thicker than the gate insulating film 36 is provided between 0, the width of the inter-pixel wiring layer 47 can be widened in terms of capacitance. For example, if the film thickness of the gate insulating film 36 is 30 nm and the film thickness of the insulating film 43 on the drain region 40 is 150 nm, the inter-pixel wiring layer 47 having a width five times larger than that in the case of FIG. 9 is secured. it can.

5 and 6 show other examples of wiring patterns in the pixel region of the amplification type solid-state image pickup device according to the present invention.

Since the width of the inter-pixel wiring layer 47 can be widened as described above, for example, as shown in FIG. 5, all the gate electrodes 37 of the pixel MOS transistors 41 in the horizontal direction (horizontal direction) are connected to each other. A wide common electrode that covers the entire gate portion, that is, a common electrode 66 that also serves as the gate electrode 37 and the inter-pixel wiring layer 47 can be formed. A signal line 51, a vertical selection line 52, and a drain power supply line 53 similar to those of FIG. In the present invention, the electrode patterning as shown in FIG. 5 can be realized with a smaller gate-drain capacitance than the comparative example. Further, in the configuration having such an electrode pattern, misalignment of the gate electrode 37 in the lateral direction can be avoided.

Further, as shown in FIG. 6, a strip-shaped common electrode having the same width, that is, the gate electrode 37 and the pixel between the pixels, which covers the entire gate portion so as to connect the gate electrodes of the pixel MOS transistors 41 in the horizontal direction (horizontal direction). A common electrode 67 that also serves as the wiring layer 47 is formed, and an effective pixel area 58 of the common electrode 67 is formed.
At the end portion led to the outside of the
Further, the wiring 72 may be connected only at the end of the effective pixel region 58. With this configuration, the wiring structure can be further simplified, and it can be driven at a higher frame rate, and the range of applicable devices is expanded.

In the above example, the inter-pixel wiring layer 47 and the gate electrode 37 are integrally formed of the same electrode material, but in addition, as shown in FIG. 7, the inter-pixel wiring layer 6 is formed.
8 is formed separately from the gate electrode 37, and the inter-pixel wiring layer 68 is formed adjacent to the gate electrode 3 as in FIG.
Pixel MO having a structure connected to the No. 7 via a contact portion 69
It can also be applied to the S transistor 70. The inter-pixel wiring layer 68 can also be formed of, for example, the same polycrystalline silicon as the gate electrode.

Also in this structure, since the insulating film 43 on the end portion of the drain region 40 over the gate electrode 47 is formed thick by selective oxidation, the gate-drain capacitance is reduced and the gate-drain crosstalk is reduced. Reduced,
Power consumption can be reduced. Further, generation of hot carriers due to the drain avalanche can be suppressed, and dark current can be reduced. Further, the same operational effects as in the above example are achieved, such as improvement in the withstand voltage between the gate and the source and between the gate and the drain.

Although not shown, at the position corresponding to the depth where the impurity regions 44 and 45 are formed,
It is also possible to form a potential adjusting region having the same polarity as the sensor well region 35 over the entire region.

As described above, the amplification type solid-state image pickup device according to the present embodiment is provided with the sensor channel which affects the pixel characteristics, the shallow source region and the drain region, the formation of the deep impurity region, and the sensor well region which is the cell surface. The following excellent points can be realized while being formed in a line and having excellent pixel characteristic uniformity.

The gate-drain capacitance is reduced, crosstalk is reduced, and power consumption can be reduced.

The inter-pixel wiring layer can be expanded in area and the contact margin can be expanded. Ultimately, it is possible to contact with another wiring at the end of the effective pixel, and a structure without a horizontal wiring in the pixel area becomes possible.

While the generation of hot carriers due to the drain avalanche is greatly reduced and the dark current is reduced,
Excellent long-term reliability of the pixel MOS transistor. The breakdown voltage between the gate and the source / drain is improved, and the yield is improved.

In the above example, the pixel MOS transistor 4
Although the n-channel type has been described as 1, the same applies to the p-channel type.

[0070]

According to the amplification type solid-state imaging device of the present invention, in the pixel transistor, the gate-drain capacitance is reduced, the gate-drain crosstalk is reduced, and the consumption electrode can be reduced. . Generation of hot carriers due to the drain avanche can be significantly reduced, dark current can be reduced, and long-term reliability of the pixel transistor is excellent.

The withstand voltage between the gate and the drain is improved, and the manufacturing yield is improved. The inter-pixel wiring layer can be expanded in area, and the contact margin between the inter-pixel wiring layer and the vertical selection line can be expanded.

According to the method for manufacturing an amplification type solid-state image pickup device according to the present invention, the channel and the source region and the drain region in the pixel transistor can be formed in a self-aligning manner, and the pixel characteristic is excellent in uniformity. It is possible to manufacture an amplification type solid-state imaging device having the same.

A channel, a source region and a drain region in a pixel transistor, and an impurity region at a deep position can be formed in a full-faline manner, and an amplification type solid-state image pickup device having excellent pixel characteristic uniformity is provided. It can be manufactured.

The channel in the pixel transistor, the source region and the drain region, the impurity region at a deep position, and the charge accumulation well region can be formed in a self-aligning manner, and the pixel characteristic is excellent in uniformity. An amplification type solid-state image sensor can be manufactured.

An insulating film thicker than the gate insulating film can be selectively formed on the source region and the drain region, the gate-drain capacitance is reduced, and the dark current due to the drain avalanche is reduced, which is highly reliable. The amplification type solid-state imaging device can be manufactured with high yield.

[Brief description of drawings]

FIG. 1 is a plan view showing an example of an amplification type solid-state imaging device according to the present invention.

FIG. 2 is a cross section of the pixel MOS transistor of FIG.

FIG. 3A is a manufacturing process diagram illustrating an example of a method of manufacturing an amplification type solid-state imaging device according to the present invention. B is a manufacturing process diagram illustrating an example of a method of manufacturing an amplification type solid-state imaging device according to the present invention. C is a manufacturing process diagram illustrating an example of a method of manufacturing an amplification type solid-state imaging device according to the present invention.

FIG. 4D is a manufacturing process diagram illustrating an example of a method of manufacturing the amplification type solid-state imaging device according to the present invention. E is a manufacturing process diagram illustrating an example of a method of manufacturing an amplification type solid-state imaging device according to the present invention.

FIG. 5 is a plan view showing another example of the amplification type solid-state imaging device according to the present invention.

FIG. 6 is a plan view showing still another example of the amplification type solid-state imaging device according to the present invention.

FIG. 7 is a pixel MOS of an amplification type solid-state imaging device according to the present invention.
It is sectional drawing which shows the other example of a transistor.

FIG. 8 is a plan view of an amplification type solid-state imaging device according to a second comparative example.

9 is a cross-sectional view of the pixel MOS transistor of FIG.

FIG. 10 is a plan view of an amplification type solid-state imaging device according to a first comparative example.

FIG. 11 is a cross-sectional view of a pixel MOS transistor.

[Explanation of symbols]

31 amplification type solid-state imaging device, 36 gate insulating film, 37
Gate electrode, 39 source region, 40 drain region,
41 pixel MOS transistor, 43 thick insulating film, 4
7 inter-pixel wiring layer, 51 signal line, 52 vertical selection line,
53 drain power line, 58 pixel region, 61 silicon nitride film, 62 resist layer

Claims (6)

[Claims] 1. An amplification type solid-state imaging device, wherein an insulating film on a drain region end of a pixel transistor is formed thicker than a gate insulating film. 2. The gate electrodes of adjacent pixel transistors are connected to each other by an inter-pixel wiring layer extending integrally from the gate electrodes onto the insulating film in the drain region. The amplification type solid-state imaging device described. 3. A step of sequentially forming an oxide film to be a gate insulating film and a silicon nitride film in the pixel region, and a step of patterning the silicon nitride film into a channel shape of the pixel to form a source region and a drain region. And a step of forming an oxide film thicker than the gate insulating film on the source region and the drain region by oxidation treatment, and a step of removing the silicon nitride film and forming a gate electrode of a pixel. Manufacturing method of amplification type solid-state imaging device. 4. The amplification type solid-state image pickup device according to claim 3, wherein the source region and the drain region are formed by ion implantation using a resist layer after patterning the silicon nitride film as a mask. Manufacturing method. 5. The source region and the drain region and the impurity region located deeper than the source region and the drain region are ion-implanted by using the resist layer as a mask when the silicon nitride film is patterned to form a self-aligned structure. The amplification type solid-state imaging device according to claim 3, wherein the amplification type solid-state imaging device is formed. 6. The method of manufacturing an amplification type solid-state imaging device according to claim 3, wherein after the silicon nitride film is removed, the charge storage well region is formed by ion implantation using the thick oxide film as a mask. .