JP4147829B2 - Method for manufacturing solid-state imaging device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a solid-state imaging device in which a pixel array unit and a peripheral circuit unit are mounted on a single semiconductor chip such as a CMOS image sensor.
[0002]
[Prior art]
FIG. 3 is a diagram showing an example of a unit pixel in a CMOS image sensor, FIG. 3A is an equivalent circuit diagram in the unit pixel, FIG. 3B is a cross-sectional view showing an element structure, and FIG. The potential diagram of the transfer gate which reads a signal charge from a photodiode is shown.
In FIG. 3A, a photodiode (hereinafter referred to as PD) generates and stores electrons corresponding to the amount of received light by photoelectric conversion, and a transfer transistor Tg converts the photoelectric conversion electrons stored in the PD into floating diffusion. Part (hereinafter referred to as FD part).
[0003]
The transfer selection transistor Ty supplies a row selection pulse from a vertical (V) scanner (not shown) to the transfer transistor Tg.
The amplification transistor Ta detects the potential fluctuation of the FD portion due to the photoelectric conversion electrons read by the transfer transistor Tg and outputs it as an electric signal. The read transistor Tx outputs the mth horizontal (H) read signal. Based on this, the output of the amplification transistor Ta is output as a current signal to an IV (current-voltage) conversion circuit (not shown).
The reset transistor Tr resets the potential of the FD unit to the power supply voltage VDD based on the (m-1) th reset signal.
[0004]
In FIG. 3B, PD is composed of a P + region (hole separation region) 10 on the surface of the semiconductor substrate and an N− region (photoelectron accumulation region) 11 therebelow, and the FD portion is the drain of the transfer transistor Tg. An N + region 12 is formed.
A channel region 13 of the transfer transistor Tg is formed between the PD and the FD portion, and a gate electrode 15 is formed on the upper layer via an insulating film 14.
In such a configuration, the carrier transferred from the PD by the transfer transistor Tg is an electron (e−), the transfer transistor Tg is an N-channel transistor, the gate electrode 15 of the transfer transistor Tg has an N-type polarity, and the channel is It is formed on the substrate surface.
Such a transfer transistor Tg is not limited to the pixel structure shown in the figure, and is common to various CMOS image sensors.
[0005]
If there is an interface state on the substrate surface under the gate of the transfer transistor Tg, dark current is generated from under the gate of the transfer transistor Tg during transfer or accumulation as shown in FIG. This dark current is added to the image signal as a noise signal and degrades the image quality.
Therefore, as shown in FIG. 4, a method of forming a N-type layer 26 on the substrate surface under the gate using a P-type gate electrode 25 for the N-channel transfer transistor Tg, that is, a method of using a buried channel transistor. Has been proposed.
In such a buried channel type transistor, since the channel 27 through which the current passes is formed at a potential minimum slightly inside the semiconductor surface, it is not affected by the interface state of the surface, so that the transfer transistor Tg Noise due to dark current under the gate can be reduced.
[0006]
In forming the N-region 11 of the PD for accumulating photoelectric conversion electrons, it is necessary to mask the transfer gate at the time of ion implantation so that the N-type dopant is not implanted into the transfer gate.
Thus, for example, as shown in FIG. 5A, in order to cover the transfer gate electrode 15 with the newly patterned resist 31 after gate processing and to open the PD region, resist patterning with zero misalignment is required. It becomes an impossible method in reality.
Therefore, for example, as shown in FIG. 5B, it is necessary to use a method of patterning a resist 33 for forming the N-region of the PD so as to overlap the resist 32 for gate processing.
[0007]
[Problems to be solved by the invention]
By the way, in the LSI of the 0.18 μm generation and later, normally, the gate electrode of the N channel transistor is made N-type and the gate electrode of the P channel transistor is made P-type.
In such a configuration, since the polarities of the gate electrode and the diffusion layer are the same, the gate electrode and the diffusion layer are ion-implanted at the same time, and the insufficient amount is additionally injected into the gate electrode, thereby making the gate polarity different. .
However, since the buried channel type transfer transistor described above has different polarities between the diffusion layer and the gate electrode, the P + type gate electrode cannot be formed by the process of simultaneously ion-implanting the diffusion layer and the gate electrode as described above.
In other words, since ions in the N-type diffusion layer are also implanted into the P + type gate electrode, it is necessary to additionally perform ion implantation that cancels the ions, increasing the number of steps (PR + ion implantation).
[0008]
Further, when forming the N-region of the PD, if a so-called double resist technique (without removing the first layer resist and coating and patterning the second layer resist), the second layer is formed. When the resist pattern is regenerated, the first layer resist is also removed, so that the first layer pattern cannot be regenerated, PD cannot be formed effectively, and the risk of manufacturing defects increases.
[0009]
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a solid-state imaging device capable of achieving both a formation process of a buried channel transistor and a formation process of a photoelectric conversion region having excellent pattern reproducibility.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a pixel array unit in which a plurality of unit pixels for imaging a subject by a photoelectric conversion unit that generates a signal charge according to the amount of received light, a control of the pixel array unit, and a peripheral circuit portion which performs signal processing of an image signal, before Symbol peripheral circuit section in the production method of the solid-state imaging device and an N-type gate transistor and the P-type gate transistor,
Each unit pixel of the pixel array section, said photoelectric conversion means, a charge detecting unit for taking out the signal charges of the photoelectric conversion means, transferred from the photoelectric conversion means of the buried channel type for transferring signal charges to said charge detecting section look including a transistor, the transfer transistor of the buried channel type is a polarity opposite the polarity of the polarity and the gate electrode of the channel region, of the pixel array portion and the transistor of the transfer transistor and the peripheral circuit portion of each unit pixel After forming a silicon film to be a gate electrode, N-type or P-type ion implantation is performed on the silicon film, so that the transfer transistor of each unit pixel in the pixel array section and the gate electrode of the transistor in the peripheral circuit section Including a gate electrode ion implantation step in which the polarity is made to be N-type and P-type, and after the gate electrode ion implantation step, Serial to form a film of silicon oxide film on said silicon film to be the gate electrode of the transistor of the transfer transistor and the peripheral circuit portion of the buried channel type, by performing patterning on their silicon film and a silicon oxide film, the surface of silicon oxide It includes a gate electrode forming step of forming a gate electrode covered with a film, after the step of forming a gate electrode, the source of the transistor of the previous SL peripheral circuit portion - drain diffusion layer and the charge of the photoelectric conversion unit of the pixel array unit comprising the step of performing each ion implantation into the storage area, when they ion implantation step, ion implantation into the gate electrode by the silicon oxide film on the surface of the gate electrode is characterized in that so as to be masked.
[0011]
In the method for manufacturing a solid-state imaging device according to the present invention, after forming a silicon film to be a gate electrode of a transistor in a unit pixel of a pixel array unit and a transistor in a peripheral circuit unit, N is formed on the silicon film. By performing type or P type ion implantation, the polarity of the gate electrode is divided into N type and P type. Then, a silicon oxide film is formed on the silicon film to be a gate electrode of the buried channel type transfer transistor of the unit pixel of the pixel array unit and the transistor of the peripheral circuit unit, and the silicon film and the silicon oxide film are patterned. in the surface to form a gate electrode covered with a silicon oxide film, and thereafter, the source of the transistor of the peripheral circuit portion - performing ion implantation into the charge accumulating region of the photoelectric conversion means of the drain diffusion layer and the pixel array unit, In this ion implantation process, the silicon oxide film on the surface of the gate electrode is masked for ion implantation into the gate electrode, so that the formation process of the buried channel type transfer transistor and the photoelectric conversion with excellent pattern reproducibility are possible. It is possible to achieve both the formation process of the conversion region.
Therefore, it is possible to suppress noise on the dark current of the generator and the image in the image element array portion by the transfer transistor of the buried channel type, with obtaining aims to improve the image quality, improvement of efficiency and yield of the manufacturing process, improvement of imaging characteristics Etc. can be achieved.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments according to the present invention will be described below.
In this embodiment, in the transistor formation process of the CMOS image sensor, N-type or P-type ion implantation is performed immediately after the formation of the silicon film to be the gate electrode of the MOS transistor, and the polarity of the gate electrode is made different. Thereafter, an insulating film for masking ion implantation for forming the diffusion layer and the N-region of the PD is formed on the silicon film, and the gate electrode is patterned.
By this process, it is possible to achieve both a process for forming a P-type gate N-type transfer transistor and a process for forming a reproducible PD N-region.
As the configuration of a CMOS image sensor, the image element array arranged unit pixels in a two-dimensional array on a single semiconductor chip, and the peripheral circuit section which performs signal processing of the drive and the imaging signal of the image element array portion As the structure of the unit pixel, for example, the structure shown in FIG. 3 can be applied.
[0013]
1 and 2 are cross-sectional views showing respective steps of a CMOS image sensor manufacturing method according to an embodiment of the present invention, in which the left side shows a manufacturing process of a buried channel type transfer transistor and the right side shows other steps. The manufacturing process of this transistor is shown.
First, after an element isolation region (not shown) is formed on the N-type silicon substrate 40 by a commonly used method, ion implantation necessary for forming a transistor in the pixel region and a transistor in the peripheral circuit portion is performed.
In FIG. 1A, a P− type layer 41 is formed in the deep region (> 0.3 μm) of the silicon substrate 40 in the pixel region, and the silicon substrate and P− are formed below the FD and the transfer transistor Tg. A P-type layer 42 is also formed between the mold layers 41.
In the peripheral circuit region, a P-type well region 51 is provided in the N-type transistor region, and an ion implantation layer 52 for adjusting the threshold voltage Vth is provided on the upper surface thereof.
An N-type well region 53 is provided in the P-type transistor region, and an ion implantation layer 54 for adjusting the threshold voltage Vth is provided on the upper surface thereof.
Further, an N − -type layer 43 having a polarity opposite to that of the channel and gate electrodes is formed in the surface region of the substrate 40 corresponding to the formation region of the transfer transistor Tg.
[0014]
In FIG. 1B, after forming a gate insulating film 61 on the silicon substrate 40, a polysilicon film 62 to be a gate electrode is formed. This is deposited with a film thickness of 200 nm by, for example, CVD (chemical vapor deposition).
Next, in FIG. 1C, boron ions B + as a P-type dopant are ionized on the polysilicon film 62 of the P-type transistor in the FD region and the peripheral circuit section, for example, under the conditions of 5 KeV and 3.00E + 15 / cm 2. Make an injection.
The polysilicon film 62 in the N-type transistor region of the peripheral circuit portion is ion-implanted with phosphorus ions P + as an N-type dopant under conditions of 15 KeV, 4E14 / cm @ 2, for example.
Thereafter, in order to activate these impurities, for example, annealing is performed at 800 DEG C. for 60 minutes in an N2 atmosphere.
[0015]
Next, in FIG. 2D, a silicon oxide film (SiO2) 63 is deposited on the polysilicon film 62 to a thickness of, for example, 250 nm by the CVD method. The silicon oxide film 63 serves as an insulating film for masking ion implantation into the source-drain diffusion layer of the transistor and the charge storage region of the PD.
Thereafter, the polysilicon film 62 and the silicon oxide film 63 are processed into a predetermined pattern shape by patterning the resist 64 and dry etching.
Next, in FIG. 2E, the resist 64 used in the processing of FIG. 2D is removed, a resist pattern having a PD region opened by a new resist 65 is formed, and arsenic ions As are, for example, 300 KeV, Ion implantation is performed under the condition of 2.3E12/cm@2 to form an N-region 71 of PD.
At this time, since the insulating film (silicon oxide film) 63 is present, the transfer gate is masked in a self-aligning manner.
[0016]
Next, in FIG. 2 (F), boron fluoride ions BF2 are ion-implanted on the substrate surface in the region included in the N-region 71 of the PD under the conditions of, for example, 50 KeV and 1E13 / cm @ 2, and the P + Layer 72 is formed. Thereafter, a source-drain diffusion layer 73 and an upper layer structure (not shown) of the transistor are formed by a commonly used method to form a pixel of the CMOS image sensor.
Here, ions implanted into the source - drain diffusion layer 73 remain in the 250 nm insulating film (silicon oxide film 63) and are not implanted into the 200 nm polysilicon film (gate electrode) 62.
[0017]
In the manufacturing method according to the present example as described above, N-type or P-type ion implantation is performed immediately after the formation of the silicon film 62 to be the gate electrode of the transistor, the polarity of the gate electrode is made, and then the diffusion layer is formed. The following effects can be obtained by forming the insulating film 63 masking the ion implantation for forming the N-region of the PD on the silicon film 62 and patterning the gate electrode.
(1) In a pixel structure in which signal charges are transferred from PD to FD, by using a buried channel transistor as a transfer transistor, dark current generated from the lower portion of the transfer transistor can be reduced.
[0018]
(2) Similarly, by using a buried channel type transistor for the transfer transistor, noise added to the image signal can be reduced, and the image quality of the output image can be improved.
(3) In addition, a buried channel type transfer transistor can be formed by using a gate electrode insulating film as a mask for ion implantation of a buried channel type transistor and adding a new process to the conventional logic process. In comparison, it can be realized with fewer steps.
(4) Furthermore, it is not necessary to use a double resist technique for the resist mask for forming the N-region of the PD, and the resist pattern can be easily reproduced.
[0019]
In the above, the case where the present invention is used for a CMOS image sensor having a unit pixel having a five-transistor structure has been described. However, the present invention can be widely applied to solid-state imaging devices having other pixel structures.
Moreover, the ion species and the implantation conditions in the above description are examples, and it goes without saying that various modifications are possible within the scope of achieving the gist of the present invention.
[0020]
【The invention's effect】
As described above, according to the manufacturing method of the solid-state imaging device of the present invention, in the process of forming the transfer transistor of the unit pixel of the pixel array unit and the transistor of the peripheral circuit unit , the silicon film that forms the gate electrode of these transistors is formed. Later, by performing N-type or P-type ion implantation into the silicon film, the polarity of the gate electrode is made different between N-type and P-type. Then, a silicon oxide film is formed on the silicon film to be a gate electrode of the buried channel type transfer transistor of the unit pixel of the pixel array unit and the transistor of the peripheral circuit unit, and the silicon film and the silicon oxide film are patterned. Then, a gate electrode whose surface is covered with a silicon oxide film is formed, and thereafter, ion implantation is performed on the source-drain diffusion layer of the transistor in the peripheral circuit portion and the charge accumulation region of the photoelectric conversion means in the pixel array portion, In this ion implantation process, the silicon oxide film on the surface of the gate electrode is masked for ion implantation into the gate electrode, so that the formation process of the buried channel type transfer transistor and the photoelectric conversion with excellent pattern reproducibility are possible. It is possible to achieve both the formation process of the conversion region.
Therefore, it is possible to suppress noise on the dark current of the generator and the image in the image element array portion by the transfer transistor of the buried channel type, with obtaining aims to improve the image quality, improvement of efficiency and yield of the manufacturing process, improvement of imaging characteristics There is an effect that can be achieved.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing each step of a manufacturing method of a CMOS image sensor according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view showing each step of a method for manufacturing a CMOS image sensor according to an embodiment of the present invention.
3A and 3B are diagrams illustrating an example of a unit pixel in a CMOS image sensor, where FIG. 3A is an equivalent circuit diagram, FIG. 3B is a cross-sectional view, and FIG. 3C is a potential diagram.
4A and 4B are diagrams illustrating an example of a unit pixel in a CMOS image sensor using a buried channel type transfer transistor, where FIG. 4A is a cross-sectional view and FIG. 4B is a potential diagram.
5 is a cross-sectional view showing an example of a resist mask for ion implantation into a PD in the CMOS image sensor shown in FIG. 4;
[Explanation of symbols]
40... N-type silicon substrate, 41 and 42... P-type layer, 43 and 71... N-type layer, 51 and 53... P-type well region, 52 and 54. Gate insulating film, 62... Polysilicon film, 63... Silicon oxide film, 64, 65... Resist, 72.

Claims (3)

A pixel array unit in which a plurality of unit pixels for imaging a subject by a photoelectric conversion unit that generates a signal charge according to the amount of received light, and a peripheral circuit unit for controlling the pixel array unit and performing signal processing of an imaging signal with the door, before Symbol peripheral circuit section in the production method of the solid-state imaging device and an N-type gate transistor and the P-type gate transistor,
Each unit pixel of the pixel array section, said photoelectric conversion means, a charge detecting unit for taking out the signal charges of the photoelectric conversion means, transferred from the photoelectric conversion means of the buried channel type for transferring signal charges to said charge detecting section look including a transistor,
In the buried channel type transfer transistor, the polarity of the channel region and the polarity of the gate electrode are opposite,
By performing N-type or P-type ion implantation on the silicon film after forming a silicon film to be a gate electrode of the transfer transistor of each unit pixel of the pixel array section and the transistor of the peripheral circuit section, the pixel array Including a gate electrode ion implantation step in which the polarity of the gate electrode of the transfer transistor of each unit pixel of the unit and the transistor of the peripheral circuit unit is made to be N-type and P-type,
After the gate electrode ion implantation step, a silicon oxide film is formed on the silicon film to be a gate electrode of the buried channel type transfer transistor and the peripheral circuit transistor, and the silicon film and the silicon oxide film are patterned. Including a gate electrode forming step of forming a gate electrode whose surface is covered with a silicon oxide film,
After the step of forming a gate electrode, the source of the transistor of the previous SL peripheral circuit portion - comprises the step of respectively performing ion implantation into the charge storage region of the photoelectric conversion means with the drain diffusion layer and the pixel array unit, in which the ion implantation step The ion implantation into the gate electrode is masked by the silicon oxide film on the surface of the gate electrode.
A method of manufacturing a solid-state imaging device.   2. The method of manufacturing a solid-state imaging device according to claim 1, wherein, in the gate electrode ion implantation step, an N-type dopant is ion-implanted into the N-type gate region and a P-type dopant is ion-implanted into the P-type gate region.   2. The method of manufacturing a solid-state imaging device according to claim 1, wherein the photoelectric conversion means of the pixel array section includes a photodiode including an upper P + type region and a lower N- type region.

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