JPH09260615A - Semiconductor nonvolatile memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To write data at a high speed by a method, wherein a 2-bit wire voltage is selected correspondingly to data index from a plurality of bit wire voltages and is applied to the selected bit wire connecting with a memory transistor to be recorded. SOLUTION: Data '2,' '1,' '3' and '0' are respectively written into memory transistors MT21 to MT24. Low addresses X1 to Xa are input into a low decoder 2, selected transistors (Tr) ST11 to ST14 are electrically connected, and Trs ST21 to ST24 are electrically non-connected. Column addresses Y1 to Yb etc., are input into a column control part 3, and selection signals ϕ3, ϕ2, ϕ4 and ϕ1 are respectively stored in registers RG1 to RG4. A voltage multiplexer part (MP) 4a selects a bit wire voltage (voltage) V3 according to the input of the signal ϕ3, and the voltage is applied to a bit wire (wire) BL1. Similarly, a voltage V2 is applied to a wire BL2 in MP 4b, a voltage V4 to a wire BL3 in MP 4c, and a voltage V1 to a wire BL4 in MP 4d.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-value type semiconductor non-volatile memory device which records at least ternary data in one memory transistor.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor nonvolatile memory device such as an EPROM or a flash memory, a binary memory cell in which data having two values of "0" and "1" is recorded in one memory transistor. The structure is normal. However, in response to a recent demand for increasing the capacity of a semiconductor nonvolatile memory device, a so-called multi-level semiconductor nonvolatile memory device that records at least three or more values of data in one memory transistor has been proposed. (For example, "A M
multi-Level 32Mb Flash Mem
ory "'95 ISSCC p132-).

FIG. 7 is a diagram showing the relationship between the threshold voltage Vth level and the data contents when two-bit quaternary data is recorded in one memory transistor in a NAND flash memory. .

In FIG. 7, the horizontal axis represents the threshold voltage Vth of the memory transistor, and the vertical axis represents the distribution frequency of the memory transistor. The content of 2-bit data constituting data to be recorded in one memory transistor is represented by [D2, D1], and [D2, D1] =
[1,1], [1,0], [0,1], [0,0]
State exists. That is, there are four states of data “0”, data “1”, data “2”, and data “3”.

In the case of a general NAND flash memory, the erased state (data “0”) to the first program state (data “1”), the second program state (data “2”), the third program state. In order to program the memory transistor to the state (data “3”), the word line voltage (gate voltage) is set to the first and the first, respectively, with the bit line voltage (drain voltage) set to a constant program voltage. 2. The threshold voltage Vth is controlled by setting the program voltage according to the third and third programming states.

Further, FIG. 8 shows a threshold voltage Vt in the case of recording 4-bit data consisting of 2 bits in one memory transistor in a NOR flash memory.
It is a figure which shows the relationship between h level and data content.

In FIG. 8, the horizontal axis represents the threshold voltage Vth of the memory transistor, and the vertical axis represents the distribution frequency of the memory transistor. In addition, the contents of the 2-bit data constituting the data to be recorded in one memory transistor are the same as those of the above-mentioned NAND type [D2, D1].
, [D2, D1] = [0,0], [0,1],
There are four states, [1,0] and [1,1].

In the example shown in FIG. 8, the range of the threshold voltage Vth in the erased state is wider than that in the first, second and third programmed states because it is a general NOR flash. This is because in the case of a memory, the erase operation by FN (Fowler Nordheim) tunneling has a larger variation in the threshold voltage Vth than the program operation by CHE (channel hot electrons).

Also in the case of the NOR flash memory, in order to program the memory transistor from the erased state to the first, second and third programmed states, the bit line voltage (drain voltage) is set to a constant program voltage. In this state, the word line voltage (gate voltage) is set to the first,
It is most preferable from the viewpoint of controlling the threshold voltage Vth to set the program voltage according to the second and third program states.

[0010]

By the way, in the case of a flash memory, data programming to a memory transistor is not performed in sequence for each memory transistor, but in parallel to a plurality of memory transistors. For example, data programming is performed in parallel for 4 to 16 memory transistors.

Therefore, in each memory transistor, it is difficult to simultaneously perform data programming from the erased state to the first, second, and third programmed states, and it is common to perform data programming in three stages in a time division manner. Target.

However, as described above, if the data programming of each memory transistor is time-divided into three stages, the data programming time is basically tripled, and high-speed data writing cannot be performed.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a multi-value type semiconductor nonvolatile memory device capable of writing data at high speed.

[0014]

In order to achieve the above object, the present invention is arranged in a matrix and accumulated in a charge accumulation portion of a memory transistor according to an applied voltage to a connected word line and bit line. And a memory transistor whose threshold voltage changes according to the change in the amount of electric charge, and records at least three or more values of data in one memory transistor according to the threshold voltage of the memory transistor. A semiconductor non-volatile memory device that, when recording data, selects a bit line voltage according to the data content to be recorded from among a plurality of bit line voltages set in advance corresponding to the data content that can be recorded in the memory transistor. And a bit line voltage applying means for applying the selected bit line voltage to the selected bit line to which the memory transistor to be recorded is connected. That.

Further, in the semiconductor nonvolatile memory device of the present invention, the data recording is performed in parallel with respect to a plurality of memory transistors, and the bit line voltage applying means, for each record data of each memory transistor, A predetermined bit line voltage is selected and applied to the corresponding selected bit line.

Further, in the semiconductor nonvolatile memory device of the present invention, the bit line voltage applying means decodes the data content to be recorded and generates a selection signal, and a column control portion.
And a voltage multiplexer unit for selecting an arbitrary bit line voltage from the plurality of bit line voltages by the selection signal and applying the selected bit line voltage to the selected bit line.

According to the semiconductor nonvolatile memory device of the present invention, a plurality of bit line voltages set according to the data content to be recorded in the memory transistor are prepared, and at the time of data recording, an arbitrary bit corresponding to the data content is prepared. A line voltage is selected and applied to the selected bit line to which the memory transistor to be recorded is connected. As a result, it is possible to realize a multi-valued semiconductor nonvolatile memory device that records at least three-valued data in one memory transistor.

With respect to a plurality of memory transistors which record data in parallel, a predetermined bit line voltage is applied to each memory transistor by the bit line voltage application means for each record data of each memory transistor. It is selected and applied to the corresponding selected bit line.
As a result, data can be simultaneously recorded in a plurality of memory transistors in one step, and high-speed programming is possible.

[0019]

1 is a block diagram showing a first embodiment of a semiconductor nonvolatile memory device according to the present invention. FIG. 1 shows a specific embodiment of a NAND flash memory.

As shown in FIG. 1, this NAND type semiconductor nonvolatile memory device comprises a memory array 1, a row decoder 2, a column controller 3, and a voltage multiplexer 4.

In FIG. 1, in the memory array 1, 16 memory transistors MT11 to MT44 are arranged in a matrix of 4 rows and 4 columns, and the memory transistors MT of the same row are arranged.
The gate electrodes of 11 to MT14, MT21 to MT24M, MT31 to MT34 and MT41 to MT44 are the common word line WL1,
It is connected to WL2, WL3 and WL4, respectively. Then, the memory transistors MT11, MT in the same column
21, MT31, MT41, memory transistors MT12, MT
22, MT32, MT42, memory transistors MT13, MT
23, MT33, MT43, memory transistors MT13, MT
23, MT33, MT43 are respectively connected in series.
Further, the drain of the memory transistor MT11 is connected to the bit line BL1 via the selection transistor ST11,
The drain of the memory transistor MT12 is connected to the bit line BL2 via the selection transistor ST12, and the drain of the memory transistor MT13 is selected transistor ST13.
Is connected to the bit line BL3 via the select transistor ST14, and the drain of the memory transistor MT14 is connected to the bit line BL4 via the select transistor ST14.
The sources of 4, MT24, MT34 and MT44 are connected to a common source line SL via select transistors ST21, ST22, ST23 and ST24, respectively.

The row decoder 2 uses the row addresses X1 to X1 in the word lines WL1 to WL4 during data programming.
The selected word line addressed by Xa is set to a predetermined voltage, for example, 12V, the other unselected word lines are set to a low voltage, for example, 3V, and the select gate line SG1 is set to 3V, and the select gate line SG2 is set. Is set to a negative voltage, for example -12V.

The column controller 3 controls the column addresses Y1 ...
Yb and program data DT are received, program data consisting of 2-bit data [D2, D1] is decoded, and each voltage multiplexer unit to which the bit line connected to the addressed memory transistor is connected is 4
A selection signal corresponding to the program data is set to a high level from among the selection signals φ1 to φ4 of various types and held in, for example, the registers RG1 to RG4, and the held selection signal is stored in the corresponding voltage multiplexer units 4a, 4b, 4c, Output at high level to 4d. Specifically, [D2, D1] =
In the case of [0,0], the selection signal φ1 is changed to [D2, D1] =
In the case of [0, 1], the selection signal φ2 is changed to [D2, D1] =
In the case of [1, 0], the selection signal φ3 is changed to [D2, D1] =
In the case of [1, 1], the selection signal φ4 is generated.

The voltage multiplexer unit 4a has selection signals φ1 to φ output from the register RG1 of the column control unit 3.
4 preset according to the data contents by 4
One of the bit line voltages V1 to V4 is selected and supplied to the bit line BL1. Similarly, the voltage multiplexer unit 4b selects one of the four types of word line voltages V1 to V4 according to the data content by the selection signals φ1 to φ4 output from the register RG2 of the column control unit 3, The voltage multiplexer unit 4c supplies one of the four types of word line voltages V1 to V4 according to the data content by the selection signals φ1 to φ4 output from the register RG3 of the column control unit 3. The voltage multiplexer unit 4d selects and supplies it to the bit line BL3, and the voltage multiplexer unit 4d selects one of four types of word line voltages V1 to V4 according to the data content by the selection signals φ1 to φ4 output from the register RG4 of the column control unit 3. 1 is selected and supplied to the bit line BL4.

Specifically, the bit line voltage V1 is selected for the selection signal φ1, the bit line voltage V2 is selected for the selection signal φ2, and the bit line voltage V3 is selected for the selection signal φ3.
In the case of the selection signal φ4, the bit line voltage V4 is selected and supplied to the selected bit lines BL1 to BL4.

In FIG. 2, the voltage multiplexer unit 4a (b,
The structural example of c, d) is shown. As shown in FIG. 2, the voltage multiplexer unit 4a is composed of n-channel MOS (NMOS) transistors NT41 to NT44. N
The MOS transistor NT41 has a bit line BL1 and a voltage V
1 is connected to the supply line and the gate electrode is the selection signal φ.
1 is connected to the input line. Similarly, the NMOS transistor NT42 is connected between the bit line BL1 and the supply line of the voltage V2, the gate electrode is connected to the input line of the selection signal φ2, and the NMOS transistor NT43 is connected to the bit line B.
The gate electrode is connected between L1 and the supply line of the voltage V3, the gate electrode is connected to the input line of the selection signal φ3, the NMOS transistor NT44 is connected between the bit line BL1 and the supply line of the voltage V4, and the gate electrode is connected. It is connected to the input line of the selection signal φ4.

In this embodiment, the bit line voltage V1 is set to 0V, the bit line voltage V2 is set to -5V, and the bit line voltage V3 is -6V based on the characteristics shown in FIG.
In addition, the bit line voltage V4 is set to -7V.

Note that FIG. 3 shows the characteristics of the threshold voltage obtained by performing the write operation in the actual device (single transistor) of the NAND flash memory. In this case, with the source line held open, the drain voltage (bit line voltage) Vd held at -6V, and the substrate voltage (Vb) held at -6V, the gate voltage (word line voltage) Vg was set at 10V, 11V. , 12V, 13
The characteristics of the threshold voltage Vthm when set to V and 14V are shown. This characteristic is the case where the bit line voltage is fixed by changing the word line voltage. However, since writing with the FN tunnel current is determined by the sum of the absolute values of the word line voltage and the bit line voltage, the bit line voltage There is no problem in using V1 to V4 as data for determining.

Hereinafter, the program operation in the circuit of FIG. 1 is performed by setting data "2" in the memory transistor MT21, data "1" in the memory transistor MT22, data "3" in the memory transistor MT23, and data "0" in the memory transistor MT24. The case of writing will be described with reference to FIG.

At the time of data programming, row addresses X1 to Xa are input to the row decoder 2 and the word line WL1 is input.
The selected word line WL2 addressed by the row address X1 to Xa among the word lines WL1 to WL4 is set to, for example, 12V, and the other unselected word lines WL1, WL3 and WL are set.
4 is set to 3V, for example, and the selection gate line S
G1 is set to 3V, and select gate line SG2 is set to -12V, for example. As a result, the selection transistors ST11 to ST14 are held in the conductive state, the selection transistors ST21 to ST24 are held in the non-conductive state, and the source line S
L is held open.

Further, column addresses Y1 to Yb and program data DT are inputted to the column control section 3,
Program data consisting of 2-bit data [D2, D1] is decoded. Then, for each voltage multiplexer unit 4 to which the bit line to which the addressed memory cell is connected is connected, the selection signal corresponding to the program data among the selection signals φ1 to φ4 is set to the high level and the registers RG1 to RG4 are set. Stored in. Specifically, the register RG1 stores the selection signal φ3, and the register RG2
The selection signal φ2 is stored in the register, the selection signal φ4 is stored in the register RG3, and the selection signal φ1 is stored in the register RG4.
Is stored. Then, the selection signals φ3, φ2, φ4, φ1 stored in the registers RG1 to RG4 are output to the voltage multiplexer units 4a, 4b, 4c, 4d at a high level, respectively.

In the voltage multiplexer unit 4a, the bit line voltage V3 (-6V) is selected according to the input of the selection signal φ3 and applied to the bit line BL1. Similarly, in the voltage multiplexer unit 4b, the bit line voltage V2 (-5V) is selected and applied to the bit line BL2 in response to the input of the selection signal φ2, and in the voltage multiplexer unit 4c, the selection signal φ4.
The bit line voltage V4 (-7V) is selected and applied to the bit line BL3 according to the input of
Then, the bit line voltage V1 (0
V) is selected and applied to the bit line BL4.

As a result, the data "2" is written to the memory transistor MT21, the data "1" is written to the memory transistor MT22, the data "3" is written to the memory transistor MT23, and the data "0" is written to the memory transistor MT24.

As described above, in the first embodiment, the NAND for writing using the FN tunnel current is used.
-Type semiconductor non-volatile memory device, prepares a plurality of bit line voltages set according to the data content to be programmed in the memory transistor, and selects and applies an arbitrary bit line voltage according to the data content during data programming. As a result, it is possible to realize a multi-valued semiconductor nonvolatile memory device capable of recording at least three-valued data in one memory transistor, and at the same time, write to a plurality of memory transistors simultaneously in one step. Therefore, high-speed writing is possible.

In the first embodiment, the NAND type semiconductor nonvolatile memory device has been described as an example. However, a DINOR type or AND type in which writing is performed using an FN tunnel current is performed.
It goes without saying that the present invention can be applied to a semiconductor nonvolatile memory device of the type.

Second Embodiment FIG. 5 is a configuration diagram showing a second embodiment of the semiconductor nonvolatile memory device according to the present invention. FIG. 5 shows a specific embodiment of the NOR flash memory.

As shown in FIG. 1, this NAND type semiconductor nonvolatile memory device comprises a memory array 11, a row decoder 12, a column controller 3, and a voltage multiplexer 4.

NOR type memory array 11 in FIG.
16 memory transistors MT11 to MT44 are arranged in a matrix of 4 rows and 4 columns, and memory transistors MT11 to MT14, MT21 to MT24M, MT31 to M in the same row.
Gate electrodes of T34 and MT41 to MT44 are connected to common word lines WL1, WL2, WL3 and WL4, respectively. Then, the memory transistors MT in the same column
11, MT21, MT31, MT41, memory transistor MT
12, MT22, MT32, MT42, memory transistor MT
13, MT23, MT33, MT43, memory transistor MT
Sources of 13, MT23, MT33, and MT43 are connected to common source lines SL1, SL2, SL3, and SL4, respectively, and drains have common bit lines BL1, BL2, B.
It is connected to L3 and BL4, respectively.

The row decoder 12 uses the row addresses X1 to X in the word lines WL1 to WL4 during data programming.
The selected word line addressed by Xa is set to a predetermined voltage, for example, 12V, and the other unselected word lines are set to the ground voltage GND.

The column control section 3 and the voltage multiplexer sections 4a, 4b, 4c and 4d of the second embodiment have substantially the same structure as that shown in FIG. The column controller 3 outputs the selection signal φ1 when [D2, D1] = [0, 0], the selection signal φ2 when [D2, D1] = [0, 1], and [D2, D1] = A selection signal φ3 is generated in the case of [1,0], and a selection signal φ4 is generated in the case of [D2, D1] = [1,1].

Further, in the second embodiment, as shown in FIG.
Based on the characteristics shown in, the voltage multiplexer units 4a, 4a
Bit lines BL1, BL2, selected by b, 4c and 4d
Bit line voltages V11 and V1 supplied to BL3 and BL4
2, V13, V14 are, for example, 4V, 5V, 6V, 7
Respectively set to V.

FIG. 6 shows the characteristics of the threshold voltage obtained by performing the write operation in the actual device (single transistor) of the NOR flash memory. In this case, the gate voltage (word line voltage) V
g is 12 V, the source voltage (source line voltage) and the substrate voltage (Vb) are held at the ground voltage GND, and the bit line voltage (word line voltage) Vg is 4 V, 4.5 V, 5 V,
The characteristics of the threshold voltage Vthn when set to 5.5V, 6V, 6.5V, 7V and 7.5V are shown. Based on this characteristic, the bit line voltages V11, V12, V13,
V14 has been decided.

Next, the operation according to the above configuration is performed by setting the data "2" to the memory transistor MT21 and the memory transistor M.
An example will be described in which data “1” is written in T22, data “3” is written in the memory transistor MT23, and data “0” is written in the memory transistor MT24.

At the time of data programming, the row decoder 12
Row addresses X1 to Xa are input to the word line WL
The selected word line WL2 addressed by the row address X1 to Xa in 1 to WL4 is set to, for example, 12V, and the other unselected word lines WL1, WL3, W
L4 is set to the ground voltage GND. Also, the source line S
L1, SL2, SL3 and SL4 are set to the ground voltage GND.

The column control unit 3 is provided with a column address Y1.
~ Yb and program data DT are input, and program data consisting of 2-bit data [D2, D1] is decoded. Then, for each voltage multiplexer unit 4 to which the bit line to which the addressed memory cell is connected is connected, the selection signal corresponding to the program data is set to the high level from the selection signals φ1 to φ4, and the register R is set.
It is stored in G1 to RG4. Specifically, the register RG
1 stores the selection signal φ3, the register RG2 stores the selection signal φ2, and the register RG3 stores the selection signal φ3.
4 is stored, and the selection signal φ1 is stored in the register RG4. Then, the selection signals φ3, φ2, φ4, φ1 stored in the registers RG1 to RG4 are output to the voltage multiplexer units 4a, 4b, 4c, 4d at a high level, respectively.

In the voltage multiplexer unit 4a, the bit line voltage V13 (6V) is selected according to the input of the selection signal φ3 and applied to the bit line BL1. Similarly, in the voltage multiplexer unit 4b, the bit line voltage V12 (5V) is selected according to the input of the selection signal φ2 and applied to the bit line BL2, and in the voltage multiplexer unit 4c, the selection signal φ4.
The bit line voltage V14 (7V) is selected and applied to the bit line BL3 according to the input of
Then, in response to the input of the selection signal φ1, the bit line voltage V11
(4V) is selected and applied to the bit line BL4.

As a result, the data "2" is written in the memory transistor MT21, the data "1" is written in the memory transistor MT22, the data "3" is written in the memory transistor MT23, and the data "0" is written in the memory transistor MT24.

As described above, in the second embodiment, in the NOR type semiconductor non-volatile memory device for writing by using CHE, a plurality of bits set according to the data content to be programmed in the memory transistor is set. Since a line voltage is prepared and an arbitrary bit line voltage according to the data content is selected and applied at the time of data programming, it is possible to record at least three-valued data in one memory transistor. In addition to realizing a semiconductor non-volatile memory device, it is possible to simultaneously write to a plurality of memory transistors in one step,
High-speed writing is possible.

In the above-described first and second embodiments, the case where the bit line voltage selected for every bit line is applied has been described as an example, but the present invention is not limited to this. In the case where the memory array is divided into a plurality of blocks each having one or a plurality of bit lines as one block, one bit line voltage is selected for each block and the addressed memory transistors are connected. Various modes are possible such as supplying to the bit line.

[0050]

As described above, according to the present invention,
In addition to being able to record at least three-valued data in one memory transistor, it is possible to simultaneously write data in a plurality of memory transistors in one step, and there is an advantage that high-speed writing can be realized.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a first embodiment of a semiconductor nonvolatile memory device according to the present invention, which is a configuration diagram showing a specific embodiment of a NAND flash memory.

FIG. 2 is a circuit diagram showing a configuration example of a voltage multiplexer unit according to the present invention.

FIG. 3 is a diagram showing a characteristic of a threshold voltage obtained by performing a write operation in an actual device (single transistor) of a NAND flash memory.

FIG. 4 is a diagram showing an example of bias conditions of each part during a write operation in the device of FIG.

FIG. 5 is a configuration diagram showing a second embodiment of a semiconductor nonvolatile memory device according to the present invention, which is a configuration diagram showing a specific embodiment of a NOR flash memory.

FIG. 6 is a diagram showing a characteristic of a threshold voltage obtained by performing a write operation in an actual device (single transistor) of a NOR flash memory.

FIG. 7 is a diagram showing a relationship between a threshold voltage Vth level and data content when data of 2 bits and 4 values is recorded in one memory transistor in a NAND flash memory.

FIG. 8 is a diagram showing the relationship between the threshold voltage Vth level and the data content when data consisting of 2 bits and having 4 values is recorded in one memory transistor in the NOR flash memory.

[Explanation of symbols]

MT11 to MT44 ... Memory transistors, 2, 12 ... Row decoder, 3 ... Control section, 4a-4d ... Voltage multiplexer section, V1 to V4, V11 to V14 ... Bit line voltage, WL1 to WL4 ... Word line, BL1 to B4 ... bit lines, SL1 to SL4 ... source lines.

Claims (3)

[Claims] 1. A charge amount stored in a charge storage portion of a memory transistor changes in accordance with a voltage applied to a word line and a bit line connected in a matrix, and a threshold value changes according to the change. What is claimed is: 1. A semiconductor non-volatile memory device, comprising: a memory transistor whose voltage changes; and storing data of at least three values or more in one memory transistor according to a threshold voltage of the memory transistor. A bit line voltage corresponding to the data content to be recorded is selected from among a plurality of bit line voltages set corresponding to the data content recordable in the memory transistor, and the selected bit line voltage is the memory transistor to be recorded. A semiconductor nonvolatile memory device having bit line voltage applying means for applying to a selected bit line connected to. 2. The data recording is performed in parallel with respect to a plurality of memory transistors, and the bit line voltage applying means selects a predetermined bit line voltage for each recording data of each memory transistor. 2. The semiconductor nonvolatile memory device according to claim 1, wherein the voltage is applied to the selected bit line. 3. The bit line voltage applying means decodes the data content to be recorded and generates a selection signal, and a bit line voltage among the plurality of bit line voltages according to the selection signal. 2. The semiconductor non-volatile memory device according to claim 1, further comprising a voltage multiplexer unit for selecting and applying the selected bit line to a selected bit line.