JPH09260396A - High-frequency transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent deterioration of high-frequency characteristics, by forming polycrystalline silicon films and insulating films sandwiched between a field insulating film and metal films. SOLUTION: In this NPN type transistor, an insulating film 11 and polycrystalline silicon films 10a are sandwiched between bonding pads 12b, 12d composed of Al and insulating films 3, 8, so that equivalent capacitors corresponding to the insulating films 3, 8, the polycrystalline silicon films 10a, and the insulating film 11 are formed right under the bonding pads 12b, 12d. Therefore, the MOS capacitance is reduced and high-frequency characteristics are imprecise. When hard metal like a Cu wire is bonded, the improved of bonding is absorbed by the polycrytstalline silicon film 10a right under the bonding pads 12b, 12d. The influence of the impulse upon the insulating films 3, 8 an epitaxial layer 2, etc., is reduced. Therefore, a high-frequency transistor of high reliability can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high frequency transistor, and more particularly to improvement of an overlay structure high frequency transistor.

[0002]

2. Description of the Related Art FIGS. 3 (a) to 3 (c) and FIG. 4 (a) are views showing a manufacturing process of a conventional NPN type high frequency transistor having an overlay structure. FIG. 4B is an equivalent circuit diagram for explaining the transistor of FIG.

As shown in FIG. 3A, an insulating film 3 including a field insulating film is formed on the surface of the N type low concentration epitaxial layer 2 on the N type semiconductor substrate 1 to form a P type graft base layer. The insulating film 3 in the region is selectively removed. Next, the insulating film 5 containing P-type impurities is formed on the entire surface, and the P-type graft base layer 4 is formed at four locations by diffusion of the impurities.

As shown in FIG. 3B, the insulating films 3 and 5 in the area where the base layer is to be formed, including the graft base layer 4 and the areas between them, are selectively removed. Next, the insulating film 7 which is a buffer film at the time of ion implantation is formed, and P-type impurities are ion-implanted to form the P-type base layer 6. Next, the insulating film 8 is formed on the entire surface.

As shown in FIG. 3C, the insulating films 7 and 8 in the region where the N-type emitter layer is to be formed are removed and a polycrystalline silicon film is formed on the entire surface to a thickness of about 450 nm. A portion other than the planned region is removed, and a polycrystalline silicon film 10 which is an emitter electrode is formed. Next, POC
The N-type emitter layer 9 is formed by the l ₃ method. After that, an insulating film 11 having a thickness of about 450 nm for protecting the peripheral portion is formed on the entire surface.

As shown in FIG. 4A, the insulating films 7, 8 and 11 are exposed so that a part of the surface of the graft base layer 4 is exposed.
Is removed and aluminum (hereinafter referred to as Al) is deposited and patterned to form the electrode wiring 12a and the bonding pad 12b connected to the electrode wiring 12a and located on the insulating films 3 and 8. At the same time, the insulating film 11 is removed so that the surface of the polycrystalline silicon film 10 located on the emitter layer 9 is exposed, and the electrode wiring 12c and the bonding pad located on the insulating films 3 and 8 connected to the electrode wiring 12c. (Not shown in FIG. 4A) are formed. That is, the base electrode wirings 12a of each of the four transistor portions are formed so as to extend in parallel with each other and are commonly connected to the bonding pad 12b. Similarly, the respective emitter electrode wirings 12c are also extended so as to be parallel to each other and commonly connected to the bonding pad. At this time, the unnecessary insulating film 11 on the region where the bonding pad 12b is formed and on the base layer 6 is removed.

Next, the collector electrode 13 is formed on the back surface of the N-type semiconductor substrate 1. In addition, wire 1
4 on the bonding pad. Although the formation of the collector region is not particularly described, a part of the epitaxial layer 2 and the semiconductor substrate 1 from the graft base layer 4 and the base layer 6 to the collector electrode 13 becomes the collector region.

As shown in FIG. 4B, an equivalent circuit of the bonding pad 12b is represented by an equivalent capacitor C. That is, the epitaxial layer 2 and the bonding pad 12b correspond to both electrodes of the equivalent capacitor C.
Only the insulating films 3 and 8 are provided between the two electrodes and correspond to the dielectric film of the equivalent capacitor C.

[0009]

However, the above configuration has the following problems. FIG. 4 (a)
In the NPN type high frequency transistor shown in (1), the high frequency characteristics are deteriorated due to the capacitance (hereinafter referred to as MOS capacitance) of the equivalent capacitor C due to the bonding pads of the base electrode wiring 12a and the emitter electrode wiring 12c. . In addition, gold (hereinafter,
When a copper (hereinafter referred to as Cu) wire is used instead of an Au wire, Cu is harder than Au, so that the insulating films 3 and 8 immediately below the Al bonding pad are damaged during bonding. Grows larger. For this reason, there is a problem that reliability is deteriorated and line production is difficult in terms of quality. An object of the present invention is to provide a high frequency transistor in which high frequency characteristics are not deteriorated and reliability is not deteriorated.

[0010]

In order to solve the above problems and achieve the object, the following means were taken in the high frequency transistor of the present invention. (1) The high-frequency transistor according to the first aspect of the present invention includes a semiconductor substrate that acts as a collector and a first insulating film including a field insulating film provided on the semiconductor substrate. The semiconductor device further includes a base region provided in the surface region of the semiconductor substrate other than the region provided with the first insulating film, and an emitter region provided in the surface region of the base region. First and second polycrystalline silicon films formed on the first insulating film, and a second insulating film provided on the first and second polycrystalline silicon films, respectively, the base region and the emitter region being respectively provided. The first and second metal films electrically connected to the first and second metal films, and the first and second bonding wirings respectively connected to the first and second metal films.

In the high frequency transistor of the present invention, since the second insulating film and the polycrystalline silicon film are respectively sandwiched between the first insulating film and the metal films on the first insulating film. , An equivalent capacitor is formed corresponding to each of the first insulating film, each of the polycrystalline silicon films, and the second insulating film between each of the metal films and the semiconductor substrate (hereinafter referred to as a semiconductor substrate). . Therefore, these equivalent capacitors are connected in series and the capacitance thereof is reduced, so that the high frequency characteristics of the high frequency transistor of the present invention are improved. Further, when bonding a hard metal such as a Cu wire, each of the polycrystalline silicon films absorbs a shock at the time of bonding, so that the effect of the shock on the first insulating film, the semiconductor substrate, etc. is reduced. Is possible. Therefore, the quality can be improved without lowering the reliability.

A high frequency transistor according to a second aspect of the present invention is provided with a first conductive type semiconductor substrate, a first conductive type epitaxial layer formed on the semiconductor substrate, and the epitaxial layer. And a field insulating film. The semiconductor device includes a first-conductivity-type first semiconductor region provided in the surface region of the epitaxial layer and a first-conductivity-type second semiconductor region provided in the surface region of the first semiconductor region. The first and second polycrystalline silicon films formed on the field insulating film and the surface of the first semiconductor region are connected, and a part of the first and second polycrystalline silicon films is formed on the first polycrystalline silicon film via the first insulating film. First provided so as to extend
And a metal film. A third polycrystalline silicon film connected to the surface of the second semiconductor region and a surface of the third polycrystalline silicon film, a part of which is on the second polycrystalline silicon film via a second insulating film. And a second metal film provided so as to extend in the direction of. First and second bonding wirings respectively connected to the first and second metal films,
And a third metal film provided on the exposed surface of the semiconductor substrate.

In the high frequency transistor of the present invention, since the polycrystalline silicon film and the insulating film are respectively sandwiched between the field insulating film and the metal film on the field insulating film, the metal is separated from the field insulating film. An equivalent capacitor is formed corresponding to the field insulating film between the film and the epitaxial layer, the polycrystalline silicon films, and the insulating films. Therefore, the equivalent capacitors are connected in series and the capacitance thereof is reduced, so that the high frequency characteristics are improved.
Further, when bonding a hard metal, each of the polycrystalline silicon films absorbs a shock during bonding, so that the field insulating film, the epitaxial layer, etc. are not damaged and the reliability is not deteriorated. , Can improve the quality. Moreover, since the first to third polycrystalline silicon films are formed at the same time, the number of manufacturing steps does not increase. Further, a manufacturing process for forming the insulating film thicker than in the past is not necessary, and the manufacturing cost does not increase.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. 1A is a plan view showing a configuration of an NPN high-frequency transistor according to an embodiment of the present invention, and FIG. 1B is a line 1b-1 of FIG. 1A.
It is sectional drawing along b. In FIG. 1, the same parts as those of the conventional transistor shown in FIGS. 3 and 4 described above are designated by the same reference numerals, and only different parts will be described.

As shown in FIG. 1A, the bonding pad 12d connected to the electrode wiring 12c by Al is formed on the insulating films 3 and 8 including the field insulating film other than the transistor portion (FIG. 1B). Has been formed. Similar to the case of the bonding pad 12b described later, the patterned polycrystalline silicon film 10a is provided below the bonding pad 12d via the insulating film 11 (FIG. 1B), and the polycrystalline silicon film is also formed. Insulating films 3 and 8, an N-type low concentration epitaxial layer 2, a semiconductor substrate 1, and an electrode 13 (FIG. 1B) are sequentially provided under 10a. Similarly, as shown in FIG. 1B, the insulating film 1 is formed under the bonding pad 12b made of Al.
1, a polycrystalline silicon film 10a, insulating films 3 and 8, an epitaxial layer 2, a semiconductor substrate 1, and an electrode 13 are sequentially provided.

Next, a manufacturing process of the high frequency transistor according to the embodiment of the present invention will be described. 2A is a diagram for explaining a manufacturing process of the transistor of FIG.
FIG. 2B is an equivalent circuit diagram for explaining the transistor. FIG. 2C is a plan view for explaining the embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals.

During the manufacturing process of the transistor shown in FIG. 1B, the processes corresponding to the above-mentioned FIGS. 3A and 3B are the same as the conventional process. The process different from the conventional one is the process corresponding to FIG. 3C, and the process is shown in FIG.

That is, as in the conventional case, the N-type semiconductor substrate 1
An insulating film 3 is formed on the surface of the upper epitaxial layer 2, and P
The insulating film 3 in the region where the mold graft base layer is to be formed is selectively removed. Next, the insulating film 5 containing P-type impurities is formed on the entire surface, and the P-type graft base layer 4 is formed at four locations by diffusion of the impurities.

Next, the insulating films 3 and 5 in the region where the P-type base layer is to be formed, including the graft base layer 4 and the space between them, are selectively removed. Next, the insulating film 7 which is a buffer film at the time of ion implantation is formed, and P-type impurities are ion-implanted to form P.
The mold base layer 6 is formed. Next, the insulating film 8 is formed on the entire surface.

Next, as shown in FIG. 2A, the insulating films 7 and 8 in the portion where the N-type emitter layer 9 is formed are removed, and a polycrystalline silicon film which will be described later as an emitter electrode or the like is formed to have a thickness of, for example, 450 nm. Form on the entire surface. A region where the emitter layer 9 is to be formed, and the bonding pad 12b, FIG.
The polycrystalline silicon film in the region where the bonding pad 12d is to be formed is removed leaving the polycrystalline silicon films 10 and 1
0a is formed. Next, at least the polycrystalline silicon film 1
0a is masked and impurities are introduced by the POCl ₃ method to form the N-type emitter layer 9. Therefore, the conductivity of the polycrystalline silicon film 10a is low, and the conductivity of the polycrystalline silicon film 10 is high. After that, an insulating film 11 having a thickness of, for example, about 450 nm for protecting the peripheral portion is formed on the entire surface.

As shown in FIG. 1B, the insulating films 7, 8 and 11 are exposed so that a part of the surface of the graft base layer 4 is exposed.
Are removed, and, for example, Al is deposited and patterned to form the electrode wiring 12a and the bonding pad 12b connected to the electrode wiring 12a and located on the insulating films 3 and 8.
And are formed. At the same time, the insulating film 11 is removed so that the surface of the polycrystalline silicon film 10 located on the emitter layer 9 is exposed, and the electrode wiring 12c and the bonding pad located on the insulating films 3 and 8 connected to the electrode wiring 12c. 12d
(FIG. 1A) is formed. That is, the base electrode wiring 12a of each of the four transistor portions is extended and formed so as to be parallel to each other, and the bonding pad 12b is formed.
Commonly connected to. Similarly, the respective emitter electrode wirings 12c are extended so as to be parallel to each other and are commonly connected to the bonding pad 12d. At this time, the insulating film 11 in the regions where the bonding pads 12b and 12d are to be formed is left without being removed.

Next, the collector electrode 13 is formed on the back surface of the N-type semiconductor substrate 1. In addition, wire 1
4 is connected to the bonding pads 12b and 12d.
Although not particularly described, in the collector region, a part of the epitaxial layer 2 and the semiconductor substrate 1 from the graft base layer 4 and the base layer 6 to the collector electrode 13 becomes the collector region as in the conventional case.

As shown in FIG. 2B, the equivalent circuit of the bonding pads 12b and 12d is represented by equivalent capacitors C1, C2 and C3 connected in series. FIG.
The insulating films 3 and 8 in (b) are the dielectric film of the equivalent capacitor C1, the polycrystalline silicon film 10a is the dielectric film of the equivalent capacitor C2, and the insulating film 11 is the dielectric film of the equivalent capacitor C3. Therefore, since the equivalent capacitors C1 to C3 are connected in series, the value of the MOS capacitance obtained by combining these capacitors C1 to C3 becomes smaller than the conventional value.

When the N-type emitter layer 9 is formed, the polycrystalline silicon film 10a in the bonding pad formation region is to be formed.
Impurities may be introduced into. In this case, the insulating films 3, 8,
Reference numerals 11 correspond to the dielectric films of the equivalent capacitors C1 and C3, respectively. Therefore, the equivalent capacitors C1 and C3 are connected in series, and the combined value of the MOS capacitances from the electrode 13 on the back surface of the semiconductor substrate 1 to the bonding pad 12b or the bonding pad 12d becomes smaller than the conventional value.

The number of the graft base layers 4 is not limited to 4 and may be any number. As shown in FIG. 2 (c), the polycrystalline silicon film 10b extends from under the electrode wirings 12a and 12c near the base layer 6 and the emitter layer 9 to directly below the bonding pads 12c and 12d, respectively. You may form.

In the embodiment of the present invention, the insulating film 11 and the polycrystalline silicon films 10a and 10b are sandwiched between the bonding pads 12b and 12d made of Al and the insulating films 3 and 8, respectively. Equivalent capacitors C1 to C3 corresponding to the insulating films 3 and 8, the polycrystalline silicon film 10a or 10b, and the insulating film 11 are formed immediately below the bonding pads 12b and 12d. Therefore, the MOS capacitance is reduced and the high frequency characteristics are improved. Further, when a hard metal such as a Cu wire is bonded, the polycrystalline silicon film 10a or 10b immediately below the bonding pads 12b and 12d made of Al absorbs the impact of bonding, and therefore the insulating films 3 and 8 and the epitaxial layer 2 The impact of that shock is reduced. Therefore, the insulating films 3 and 8, the epitaxial layer 2 and the like are not damaged, the reliability is not lowered, and the quality is improved. In addition, the polycrystalline silicon film 1
Since 0, 10a, and 10b are formed at the same time, the number of manufacturing steps does not increase. Further, the step of forming the insulating film thicker than in the past is unnecessary. Therefore, the manufacturing cost does not increase.

[0027]

EXAMPLE A calculation example of the MOS capacitance values C1 to C3 according to the above-described embodiment of the present invention will be described. For comparison, the model number 2SC3544 NPN, which has almost the same conditions, is used.
The value C of the MOS capacitance for the type transistor is also shown. The area of the bonding pad 12b is 0.0385 × 10 ^-2
(Cm2), dielectric constant ε0 in vacuum is 8.84 × 10
^-14 , the relative permittivity εs of the insulating film is 3.9, and the relative permittivity εs of the polycrystalline silicon film 10a is 12. The pad radius R in this case is 0.011 (cm).

The thickness of the insulating films 3 and 8 of the embodiment of the present invention is 1
The polycrystalline silicon film 10a having a low conductivity of 680 nm has a thickness of 450 nm, and the insulating film 11 has a thickness of 450 nm. Each MOS capacitance C of the bonding pad 12b
1 to C3 and their combined capacity are as follows.

C 1 = 0.0385 × 10 ⁻² × 3.9 × 8.84 × 10 ⁻¹⁴ /1.68×10 ⁻⁴ = 0.79 (pF) C 2 = 0.0385 × 10 ⁻² × 12 × 8.84 × 10 ^-14 /0.45×10 ^-4 = 9.1 (pF) C 3 = 0.0385 × 10 ^-2 × 3.9 × 8.84 × 10 ^-14 /0.45×10 ^-4 = 2.9 (pF) C = 1 / (1 / 0.79 + 1 / 9.1 + 1 / 2.9) = 0.58 (pF) In the conventional case, the insulating film 3 having a thickness of 1680 nm, The MOS capacitance C1 of 8 alone gives 0.79 pF. Therefore,
The combined value of the MOS capacitors C1 to C3 of the embodiment of the present invention is smaller than the conventional value by 0.21 pF. Therefore, high frequency characteristics do not deteriorate

[0030]

As described above, according to the present invention, it is possible to provide a high frequency transistor in which high frequency characteristics are not deteriorated and reliability is not deteriorated.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a high frequency transistor according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a high frequency transistor according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating an example of a conventional high frequency transistor.

FIG. 4 is a diagram illustrating an example of a conventional high frequency transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... N-type semiconductor substrate (base), 2 ... N-type epitaxial layer, 3 ... Insulating film including field insulating film, 4 ... Graft base layer, 6 ... Base layer, 7, 8, 11 ... Insulating film, 9 ... Emitter Layer, 10, 10a, 10b ... Polycrystalline silicon film, 12a, 12c ... Electrode wiring, 12b, 12d ... Bonding pad, 13 ... Collector electrode, 14 ... Wire.

Claims (2)

[Claims] 1. A semiconductor substrate acting as a collector, a first insulating film including a field insulating film provided on the semiconductor substrate, and a surface region of the semiconductor substrate other than a region where the first insulating film is provided. A base region provided on the first insulating film, an emitter region provided on a surface region of the base region, first and second polycrystalline silicon films formed on the first insulating film, and the first and second poly-silicon films. First and second metal films provided on the crystalline silicon film via a second insulating film and electrically connected to the base region and the emitter region, respectively, and connected to the first and second metal films, respectively. High-frequency transistor comprising: a first bonding wire and a second bonding wire. 2. A first conductivity type semiconductor substrate, a first conductivity type epitaxial layer formed on the semiconductor substrate, a field insulating film provided on the epitaxial layer, and a surface region of the epitaxial layer. A second semiconductor region of the first conductivity type, a second semiconductor region of the first conductivity type provided in a surface region of the first semiconductor region, a first semiconductor film formed on the field insulating film, A first metal film that is connected to the second polycrystalline silicon film and the surface of the first semiconductor region, and is provided so as to partially extend over the first polycrystalline silicon film through the first insulating film. A third polycrystalline silicon film connected to the surface of the second semiconductor region, and a second polycrystalline silicon film connected to the surface of the third polycrystalline silicon film, a part of which is interposed by a second insulating film. Provided to extend over the membrane A second metal film, first and second bonding wirings respectively connected to the first and second metal films, and a third metal film provided on the exposed surface of the semiconductor substrate. Characteristic high-frequency transistor.