JPH09260290A - Iii group nitride semiconductor and manufacture of p-n junction diode - Google Patents

Iii group nitride semiconductor and manufacture of p-n junction diode

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Publication number
JPH09260290A
JPH09260290A JP6412496A JP6412496A JPH09260290A JP H09260290 A JPH09260290 A JP H09260290A JP 6412496 A JP6412496 A JP 6412496A JP 6412496 A JP6412496 A JP 6412496A JP H09260290 A JPH09260290 A JP H09260290A
Authority
JP
Japan
Prior art keywords
film
group iii
iii nitride
nitride semiconductor
plane
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6412496A
Other languages
Japanese (ja)
Inventor
Hideaki Matsuyama
秀昭 松山
Toshiyuki Matsui
俊之 松井
Takeshi Suzuki
健 鈴木
Shoji Kitamura
祥司 北村
Hiroshi Kamijo
洋 上條
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP6412496A priority Critical patent/JPH09260290A/en
Publication of JPH09260290A publication Critical patent/JPH09260290A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To obtain a P-conductivity type III group nitride semiconductor film which is easily cleaved and high in carrier density by a method wherein a ZnO film is eqitaxially grown on the surface of a GaAs single crystal substrate, and furthermore a III group nitride semiconductor film is epitaxially grown thereon, where the GaAs single crystalline substrate and the ZnO film are possessed of surfaces prescribed in plane orientation respectively. SOLUTION: An ZnO film 2 whose surface is of (0001) plane is selectively and epitaxially formed on the surface of a GaAs single crystalline substrate 1 whose surface is of (111) plane, and a P-type III group nitride semiconductor film 3 whose surface is of (0001) plane is epitaxially grown the surface of the ZnO film 2. At this point, the ZnO film 2 is formed by an RF magnetron sputtering method to serve as buffer layer. The P-type GaN, GaAlN, or GaInN film 3 is formed on the ZnO buffer layer 2 through an MBE device. The MBE device is composed of two vacuum chambers which communicate with each other, wherein three Knudsen cells are provided in the lower part of one of the vacuum chambers, and a radical beam device is provided in the other vacuum chamber.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、紫外線、青色、緑
色の発光ダイオードやレーザなどの発光素子に用いられ
るIII族窒化物半導体材料およびpn接合ダイオードの
製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a group III nitride semiconductor material used for light emitting devices such as ultraviolet light, blue light, green light emitting diodes and lasers, and a method for manufacturing a pn junction diode.

【0002】[0002]

【従来の技術】紫外線、青色、緑色などの短波長の光を
発する素子用の材料として、II−VI族半導体とIII族窒
化物半導体とが研究されてきた。BN以外のIII族窒化
物半導体のA1N、GaN、InNはウルツ鉱構造をと
り、A1GaNやInGaNなどの混晶系が得られる。
バンド構造が直接遷移型であり、バンド・ギャップがI
nNの1.9eV からAINの6.2eV と広い範囲にわたるた
め、有望な短波長発光素子用の材料とされてきた。
2. Description of the Related Art II-VI group semiconductors and III group nitride semiconductors have been studied as materials for devices that emit light of short wavelength such as ultraviolet rays, blue rays and green rays. Group III nitride semiconductors A1N, GaN, and InN other than BN have a wurtzite structure, and a mixed crystal system such as A1GaN and InGaN can be obtained.
The band structure is a direct transition type, and the band gap is I
Since it has a wide range from 1.9 eV for nN to 6.2 eV for AIN, it has been regarded as a promising material for short wavelength light emitting devices.

【0003】これらのIII族窒化物半導体の合成は、有
機金属とアンモニアガスを原料、水素をキャリアガスと
して有機金属気相エピタキシャル成長法(MOVPE)
がで行われている。基板としてはサファイア、基板面と
しては(0001)面が一般的に使用され、成膜時の基
板温度は約1100℃と高温である。合成した膜はn型伝導
を示すが、これは窒素欠損のためと考えられている。n
型伝導制御は、合成の際にSiやGe原子を膜中に添加
することによって行われる。p型伝導制御は、同様に合
成の際にMg原子を添加し、さらに活性化処理をするこ
とによって行っている。また、これらの膜を積層するこ
とによってpn接合が得られている。AIGaNやIn
GaNの混晶によりバンド・ギャップを制御することに
よってダブルヘテロ構造、量子井戸構造なども製作でき
るようになっている。
The synthesis of these group III nitride semiconductors is carried out by metalorganic vapor phase epitaxy (MOVPE) using organic metal and ammonia gas as raw materials and hydrogen as carrier gas.
Is being done in. Sapphire is generally used as the substrate, and the (0001) plane is generally used as the substrate surface, and the substrate temperature during film formation is as high as about 1100 ° C. The synthesized film shows n-type conduction, which is thought to be due to nitrogen deficiency. n
The type conduction control is performed by adding Si or Ge atoms into the film during synthesis. Similarly, the p-type conduction control is performed by adding Mg atoms during the synthesis and further performing activation treatment. A pn junction is obtained by stacking these films. AIGaN and In
By controlling the band gap with a mixed crystal of GaN, a double hetero structure, a quantum well structure, etc. can be manufactured.

【0004】III族窒化物半導体を用いた短波長発光素
子としては紫外線、青色、緑色などLEDが作製されて
いる。一方、レーザ・ダイオード(LD)は、光の共振
面の形成が難しく、III族窒化物半導体を用いた短波長
発光のLDの実用化には到っていない。赤外線LDは、
共振面を劈開面で形成している。これに使用している基
板はGaAsであり、その(111)面は劈開が非常に
強い。この劈開面は、原子オーダの平坦性と平行度があ
るため共振面に適している。
As a short-wavelength light emitting device using a group III nitride semiconductor, LEDs of ultraviolet, blue, green, etc. have been manufactured. On the other hand, in the laser diode (LD), it is difficult to form a light resonance surface, and a short wavelength light emitting LD using a group III nitride semiconductor has not been put to practical use. Infrared LD is
The resonance surface is formed by a cleavage plane. The substrate used for this is GaAs, and its (111) plane has very strong cleavage. This cleavage plane is suitable as a resonance plane because it has flatness of atomic order and parallelism.

【0005】[0005]

【発明が解決しようとする課題】III族窒化物半導体は
六方晶形のウルツァイト構造の結晶であり、その合成に
用いられる基板も六方晶形のサファイアが使われる。そ
して、III族窒化物半導体は(0001)面が成長しや
すいので、基板も(0001)面が使用される。しか
し、六方晶形の結晶は一般的に劈開性が弱く、特に(0
001)面以外の面は劈開が難しい。サファイアも同様
に劈開性が弱い。このため、LDに必要な光の共振面を
劈開面で形成することが困難である。
The group III nitride semiconductor is a crystal having a hexagonal wurtzite structure, and a hexagonal sapphire is also used as a substrate for its synthesis. Since the (0001) plane easily grows in the group III nitride semiconductor, the substrate also uses the (0001) plane. However, a hexagonal crystal generally has a weak cleavage property, and in particular (0
It is difficult to cleave the surfaces other than the (001) surface. Sapphire is also less cleavable. Therefore, it is difficult to form the light resonance surface necessary for the LD by the cleavage surface.

【0006】また、p型伝導のIII族窒化物半導体の合
成には、合成する際にp型不純物であるMgを添加する
方法が広く用いられている。しかし、合成に使用した有
機金属の分解により発生した水素やキャリアガスに用い
た水素が膜中に入り、Mgアクセプタを不活性にする。
このため、成長後に低加速電子線を照射するか、窒素雰
囲気中で熱処理をすることにより、Mgの活性化処理を
行わなければならない。この場合、得られるキャリア密
度は1018cm-3以下であり、必要な高キャリア密度に達
しない。
In addition, a method of adding Mg which is a p-type impurity during synthesis is widely used for synthesizing a p-type conductive group III nitride semiconductor. However, hydrogen generated by the decomposition of the organic metal used for synthesis and hydrogen used as a carrier gas enter the film to inactivate the Mg acceptor.
Therefore, the Mg activation process must be performed by irradiating with a low-acceleration electron beam after the growth or by performing heat treatment in a nitrogen atmosphere. In this case, the obtained carrier density is 10 18 cm −3 or less, which does not reach the required high carrier density.

【0007】本発明の目的は、上記の問題を解決し、短
波長発光のLD素子の基板に用いることのできる、劈開
が容易で高キャリア密度のp型伝導が得られるIII族窒
化物半導体の製造方法を提供することにある。また、そ
のような半導体を用いたpn接合ダイオードの製造方法
を提供することにある。
It is an object of the present invention to solve the above problems and to provide a group III nitride semiconductor which can be used as a substrate of an LD device emitting short wavelength light and which can be easily cleaved to obtain p-type conduction with high carrier density. It is to provide a manufacturing method. Another object of the present invention is to provide a method for manufacturing a pn junction diode using such a semiconductor.

【0008】[0008]

【課題を解決するための手段】上記の目的を達成するた
めに、本発明のIII族窒化物半導体材料の製造方法は、
(111)面を表面とするGaAs単結晶基板表面上に
(0001)面を表面とするZn0膜をエピタキシャル
成長させ、このZn0膜上に(0001)面を表面とす
るIII族窒化物膜をエピタキシャル成長させるものとす
る。劈開が非常に強い基板としてGaAsがあげられ
る。その(111)面は三角格子であり、六方晶形ウル
ツァイト構造のIII族窒化物半導体の(0001)面と
同じである。しかし、格子不整合がGaNに対して-20.
2%と大きく、エピタキシャルに成長させることは難し
い。この格子不整合を緩和する目的で、基板の上にバッ
ファ層を挿入する。バッファ層として、GaNに対する
格子不整合が-1.9% と小さく、エピタキシャル成長しや
すいZn0を用いる。Zn0膜を不活性ガスとZn0タ
ーゲットとを用いたマグネトロンスパッタ法により形成
することがよい。不活性ガスとZn0ターゲットを用い
たマグネトロンスパッタ法によってZn0エピタキシャ
ル膜が形成できるのは以下の理由によると考えられる。
スッパタ法ではArイオンをターゲットに衝突させ、弾
き出される原子団や分子団によって膜が作られる。Zn
0ターゲットを使用しているのでZn0分子団によって
膜が作られ、GaAs基板表面を酸化することがほとん
どない。Ar・酸素混合ガスを用いたスパッタ法や酸素
ラジカルを用いた分子線エピタキシャル法ではZn0の
エピタキシャル膜が得られない。これより、GaAs基
板表面の酸化がエピタキシャル成長を阻害するものと考
えられる。スパッタ時の基板温度を350℃以下とする
ことがよい。基板温度が400℃になるとZn0膜のX
線回折ピーク強度が低下するので350℃以下に抑え
る。
In order to achieve the above object, the method for producing a group III nitride semiconductor material according to the present invention comprises:
A Zn0 film having a (0001) plane as a surface is epitaxially grown on the surface of a GaAs single crystal substrate having a (111) plane as a surface, and a group III nitride film having a (0001) plane as a surface is epitaxially grown on this Zn0 film. I shall. GaAs is an example of a substrate having a very strong cleavage. The (111) plane is a triangular lattice, which is the same as the (0001) plane of the group III nitride semiconductor having a hexagonal wurtzite structure. However, the lattice mismatch is -20 with respect to GaN.
As large as 2%, it is difficult to grow epitaxially. A buffer layer is inserted on the substrate for the purpose of mitigating this lattice mismatch. As the buffer layer, Zn0, which has a small lattice mismatch with GaN of -1.9% and is easily epitaxially grown, is used. The Zn0 film is preferably formed by a magnetron sputtering method using an inert gas and a Zn0 target. The reason why the Zn0 epitaxial film can be formed by the magnetron sputtering method using the inert gas and the Zn0 target is considered to be as follows.
In the Sputterer method, Ar ions collide with a target, and a film is formed by the ejected atomic groups and molecular groups. Zn
Since the 0 target is used, a film is formed by the Zn0 molecular group and the surface of the GaAs substrate is hardly oxidized. An epitaxial film of Zn0 cannot be obtained by a sputtering method using Ar / oxygen mixed gas or a molecular beam epitaxial method using oxygen radicals. From this, it is considered that the oxidation of the GaAs substrate surface hinders the epitaxial growth. The substrate temperature during sputtering is preferably 350 ° C. or lower. When the substrate temperature reaches 400 ° C, X of Zn0 film
Since the line diffraction peak intensity decreases, the temperature is kept at 350 ° C or lower.

【0009】III族窒化物膜を水素を含まない材料を原
料とした分子線エピタキシャル法(以下MBEと記す)
で形成することがよい。MBEは水素を用いていないこ
とやMOVPEに比較して基板温度が低いことから、II
I族窒化物半導体を形成する際にGaAs基板やZn0
バッファ層に与える損傷が小さい。III族窒化物半導体
とZn0の格子不整合は上記のように小さく、Zn0エ
ピタキシャル膜の上にIII族窒化物半導体をエピタキシ
ャル成長することは比較的容易である。この方法でp型
伝導を示すIII族窒化物膜を形成することができる。こ
のように作製したIII族窒化物半導体が高キャリア密度
のp型伝導を示す理由については明らかではないが、ア
クセプタを不活性にする水素を使用していないため活性
化処理をおこなうことなくp型伝導体が形成できる。M
BE実施時の基板温度を625℃以下とすることがよ
い。成膜されたIII族窒化物膜のX線回折ピーク強度
は、基板温度が600℃のときに最も大きく、650℃
になると約60%に小さくなる。従って基板強度を62
5℃以下に抑える。III族窒化物がGaNであることが
よい。また、GaAlNあるいはGaInNであること
がよい。
Molecular beam epitaxy using a group III nitride film made of a material containing no hydrogen (hereinafter referred to as MBE)
It is better to form. Since MBE does not use hydrogen and the substrate temperature is lower than that of MOVPE, II
When forming a group I nitride semiconductor, a GaAs substrate or ZnO
Less damage to the buffer layer. The lattice mismatch between the group III nitride semiconductor and Zn0 is small as described above, and it is relatively easy to epitaxially grow the group III nitride semiconductor on the Zn0 epitaxial film. By this method, a group III nitride film exhibiting p-type conduction can be formed. It is not clear why the thus-produced Group III nitride semiconductor exhibits p-type conduction with high carrier density, but since hydrogen is not used to inactivate the acceptor, the p-type conductivity can be obtained without performing activation treatment. Conductors can be formed. M
The substrate temperature during BE is preferably 625 ° C. or lower. The X-ray diffraction peak intensity of the formed Group III nitride film is the highest at a substrate temperature of 600 ° C and is 650 ° C.
Becomes about 60%. Therefore, the substrate strength is 62
Keep below 5 ° C. The group III nitride is preferably GaN. Further, it is preferably GaAlN or GaInN.

【0010】本発明のpn接合ダイオードの製造方法
は、(111)面を表面とするGaAs単結晶基板の表
面上に選択的に(0001)面を表面とするZn0膜を
エピタキシャル成長させ、このZn0膜上に(000
1)面を表面とするp型III族窒化物半導体膜をエピタ
キシャル成長させ、GaAs露出面上に(0001)面
を表面とするn型III族窒化物半導体膜をエピタキシャ
ル成長させるものとする。上記のIII族窒化物半導体お
よびpn接合ダイオードの製造方法によりZn0バッフ
ァ層の上にp型III族窒化物半導体膜が成膜されること
を利用し、Zn0バッファ層を形成しないGaAs単結
晶基板面上に直接エピタキシャル成長させるn型III族
窒化物膜と隣接させることにより、基板面に垂直なpn
接合面を有するダイオードが容易に製造できる。
According to the method of manufacturing a pn junction diode of the present invention, a Zn0 film having a (0001) plane as a surface is selectively epitaxially grown on a surface of a GaAs single crystal substrate having a (111) plane as a surface, and this Zn0 film is grown. Above (000
1) A p-type group III nitride semiconductor film whose surface is the surface is epitaxially grown, and an n-type group III nitride semiconductor film whose surface is the (0001) surface is epitaxially grown on the exposed GaAs surface. A GaAs single crystal substrate surface on which a Zn0 buffer layer is not formed by utilizing the fact that the p-type Group III nitride semiconductor film is formed on the Zn0 buffer layer by the method for manufacturing a Group III nitride semiconductor and a pn junction diode described above. Adjacent to the n-type group III nitride film directly epitaxially grown on the pn perpendicular to the substrate surface
A diode having a junction surface can be easily manufactured.

【0011】[0011]

【発明の実施の形態】バッファ層としてのZn0膜の成
膜にはRFマグネトロン・スパッタリング法を用いる。
Zn0バッファ層上へのp型GaN、GaAlN、Ga
InN膜の成膜には、図2に示すMBE装置を用いる。
この装置は連通した二つの真空室21、22よりなり、
真空室21の下部に三つのクヌーセンセル31、32、
33を備えている。真空室22の下部にはラジカルビー
ム装置34を備えている。クヌーセンセル31ではGa
41を、クヌーセンセル32ではAl51を、クヌーセ
ンセル33ではIn61をそれぞれ加熱、蒸発させ、G
a原子ビーム42、Al原子ビーム52、In原子ビー
ム62を作る。ラジカルビーム装置34では、RFコイ
ル35により形成されるプラズマ内で外部から導入され
る窒素ガス71を活性化して窒素ラジカルビーム72を
作る。このようにして作られた原子ビーム42、52、
62のいくつかと窒素ラジカルビーム72とを原料とし
て、ヒータ81によって加熱される基板8の上にGaN
膜を成膜することができる。成膜されたGaNの結晶性
の確認のため、電子銃91より発する電子ビーム92を
基板8に照射して蛍光板93上に回折パターンを結像さ
せることによる反射高速電+回折法(RHEEDを)行
うことができる。
BEST MODE FOR CARRYING OUT THE INVENTION An RF magnetron sputtering method is used for forming a Zn0 film as a buffer layer.
P-type GaN, GaAlN, Ga on the Zn0 buffer layer
The MBE apparatus shown in FIG. 2 is used for forming the InN film.
This device consists of two vacuum chambers 21 and 22 in communication with each other.
At the bottom of the vacuum chamber 21, three Knudsen cells 31, 32,
33 is provided. A radical beam device 34 is provided below the vacuum chamber 22. Ga in Knudsen cell 31
41, Al51 in the Knudsen cell 32 and In61 in the Knudsen cell 33 are heated and evaporated, respectively.
An a atomic beam 42, an Al atomic beam 52, and an In atomic beam 62 are created. In the radical beam device 34, the nitrogen gas 71 introduced from the outside is activated in the plasma formed by the RF coil 35 to generate a nitrogen radical beam 72. The atomic beams 42, 52 made in this way,
Using some of 62 and the nitrogen radical beam 72 as raw materials, GaN is formed on the substrate 8 heated by the heater 81.
A film can be deposited. In order to confirm the crystallinity of the deposited GaN, a high-speed reflection + diffraction method (RHEED) by irradiating the substrate 8 with an electron beam 92 emitted from an electron gun 91 to form a diffraction pattern on the fluorescent plate 93. It can be carried out.

【0012】実施例:単結晶基板には、比抵抗が1×1
7 Ωcm以上で(111)面を表面とするGaAsを用
いた。RFマグネトロン・スパッタ法によるZn0バッ
ファ層の代表的な成膜条件は下記の通りである。 ターゲット: Zn0(直径150mm) 原料ガス : Ar ガス圧力 : 1Pa 基板温度 : 300℃ 高周波出力: 50W Zn0は約100nmの厚さに成膜した。X線回折法によ
る測定により、GaAsの(111)面とZn0の(0
001)面からの回折ピークのみが観測された。Zn0
の(0002)面間隔は0.259nm であり、Zn0のc軸
方向の格子定数の1/2 となっていた。これより、形成し
た膜はZn0であり、その(0001)面がGaAs基
板の(111)面と平行であることがわかった。また、
RHEEDによる測定により、Zn0膜は6回対称の単
結晶であり、その電子線回折パターン間隔はZn0のa
軸方向の格子定数と対応していた。GaAs基板との結
晶方位関係は、GaAs基板の〔1−10〕方向とZn
0の〔11−20〕方向が平行であり、GaAs基板上
にZn0膜がエピタキシャルに成長していることがわか
る。同一条件でGaAs(100)基板、GaAs(1
10)基板にZn0膜を形成したが、Zn0膜は多結晶
質であった。
Example: A single crystal substrate has a specific resistance of 1 × 1.
GaAs having a (111) surface as the surface and having a resistance of 0 7 Ωcm or more was used. Typical film forming conditions of the Zn0 buffer layer by the RF magnetron sputtering method are as follows. Target: Zn0 (diameter 150 mm) Raw material gas: Ar gas pressure: 1 Pa Substrate temperature: 300 ° C. High frequency output: 50 W Zn0 was deposited to a thickness of about 100 nm. As measured by the X-ray diffraction method, the (111) plane of GaAs and the (0) of Zn0
Only the diffraction peak from the (001) plane was observed. Zn0
The (0002) plane spacing was 0.259 nm, which was half the lattice constant of Zn0 in the c-axis direction. From this, it was found that the formed film was Zn0 and its (0001) plane was parallel to the (111) plane of the GaAs substrate. Also,
According to RHEED measurement, the Zn0 film was a single crystal with 6-fold symmetry, and its electron beam diffraction pattern interval was a.
It corresponded to the lattice constant in the axial direction. The crystal orientation relationship with the GaAs substrate is [1-10] direction of the GaAs substrate and Zn
It can be seen that the [11-20] direction of 0 is parallel and the Zn0 film is epitaxially grown on the GaAs substrate. GaAs (100) substrate, GaAs (1
10) A Zn0 film was formed on the substrate, but the Zn0 film was polycrystalline.

【0013】比較のために、ZnターゲットとAr・酸
素混合ガスを用い、同様の条件でスパッタ法により成膜
した。しかし、この膜は(0001)配向しているが、
多結晶質であった。また、酸素ラジカルを用いたMBE
法で形成した膜も、同様であった。図3は、Zn0膜成
膜時の基板温度のX線回折ピーク強度との関係を示す。
このように基板温度が400℃に上がると強度が急激に
減少し、基板温度を300℃にしたことが適当であるこ
とがわかる。
For comparison, a Zn target and an Ar / oxygen mixed gas were used to form a film by the sputtering method under the same conditions. However, although this film is (0001) oriented,
It was polycrystalline. MBE using oxygen radicals
The same applies to the film formed by the method. FIG. 3 shows the relationship between the substrate temperature and the X-ray diffraction peak intensity at the time of forming the Zn0 film.
As described above, when the substrate temperature rises to 400 ° C., the strength sharply decreases, and it is appropriate to set the substrate temperature to 300 ° C.

【0014】次いで、図2のMBE装置を用いてZn0
バッファ層を形成したGaAs基板8上にp型GaN膜
を形成した。クヌーセンセルはGaクヌーセンセル41
のみを用いた。代表的な成膜条件は次の通りである。 圧力 : 1×10-3Pa 基板温度 : 600℃ 原料金属 : Ga クターセンセル温度 : 930℃ N2 ガス流量 : 1sccm RF出力 : 500W GaNは約500nmの厚さに成膜した。GaNの成膜の
際、MgやSiなどの不純物は添加しなかった。X線回
折法による測定により、GaAsの(111)面とGa
Nの(0001)面からの回折ピークのみ観測された。
Zn0の(0001)面からの回折ピークはGaNの
(0001)面からの回折ピークと重なるため観測でき
なかった。GaNの(0002)面間隔は0.259nm であ
り、GaNのc軸方向の格子定数の1/2 となっていた。
これより、形成した膜はGaNであり、その(000
1)面がGaAs基板の(111)面やZn0の(00
01)面と平行であることがわかった。また、電子銃9
1と蛍光板92を用いるRHEEDによる測定により、
GaN膜は6回対称の単結晶であり、その電子線回折パ
ターン間隔はGaNのa軸方向の格子定数と対応してい
た。結晶方位関係は、Zn0バッファー層の〔11−2
0〕方向とGaN膜の〔11−20〕方向が平行であ
り、Zn0バッファー層上にGaN膜がエピタキシャル
に成長していることがわかる。図4は、この膜のフォト
ルミネッセンスのスペクトルを示す。GaNのバンドギ
ャップ3.4eV 近傍の約367nmに発光ピークが観測でき
た。ホール測定の結果、p型伝導でキャリア密度が2×
1020cm-3、移動度が18cm2/Vs であった。伝導型に
ついてはゼーベック効果を利用して確認した。これらの
測定をする前に、熱処理や低速電子線処理などは行わな
かった。図4のスペクトルにはZn不純物にともなうピ
ークは観測されなかった。オージェ分析により厚さ方向
の元素分析を行ったが、ZnはGaN膜中に拡散してい
なかった。以上によりアクセプタはZnでないと考えら
れる。p型伝導を示す理由は明らかでない。また、サフ
ァイア基板やGaAs基板を用いた場合、成長したGa
N膜はn型伝導を示した。
Next, using the MBE apparatus shown in FIG.
A p-type GaN film was formed on the GaAs substrate 8 on which the buffer layer was formed. Knudsen cell is Ga Knudsen cell 41
Only was used. Typical film forming conditions are as follows. Pressure: 1 × 10 −3 Pa Substrate temperature: 600 ° C. Raw metal: Ga tractor cell temperature: 930 ° C. N 2 gas flow rate: 1 sccm RF output: 500 W GaN was deposited to a thickness of about 500 nm. Impurities such as Mg and Si were not added during the GaN film formation. As measured by X-ray diffraction, the (111) plane of GaAs and Ga
Only the diffraction peak from the (0001) plane of N was observed.
The diffraction peak from the (0001) plane of Zn0 could not be observed because it overlaps with the diffraction peak from the (0001) plane of GaN. The (0002) plane spacing of GaN was 0.259 nm, which was half the lattice constant of GaN in the c-axis direction.
From this, the formed film is GaN and its (000
The (1) plane is the (111) plane of the GaAs substrate or the (00) plane of Zn0.
It was found to be parallel to the (01) plane. Also, the electron gun 9
1 and the RHEED measurement using the fluorescent plate 92,
The GaN film was a 6-fold symmetric single crystal, and its electron beam diffraction pattern interval corresponded to the lattice constant of GaN in the a-axis direction. The crystal orientation is [11-2 of the Zn0 buffer layer].
It can be seen that the [0] direction and the [11-20] direction of the GaN film are parallel, and the GaN film is epitaxially grown on the Zn0 buffer layer. FIG. 4 shows the photoluminescence spectrum of this film. An emission peak was observed at about 367 nm near the band gap of 3.4 eV of GaN. As a result of hole measurement, p-type conduction and carrier density of 2 ×
The mobility was 10 20 cm -3 and the mobility was 18 cm 2 / Vs. The conductivity type was confirmed using the Seebeck effect. Prior to these measurements, no heat treatment or low-speed electron beam treatment was performed. No peak due to Zn impurities was observed in the spectrum of FIG. Elemental analysis in the thickness direction was performed by Auger analysis, but Zn was not diffused in the GaN film. From the above, it is considered that the acceptor is not Zn. The reason for showing p-type conduction is not clear. When a sapphire substrate or GaAs substrate is used, the grown Ga
The N film showed n-type conduction.

【0015】なお、Al0. 05Ga0. 95NおよびIn
0. 05Ga0. 95Nの混晶膜のために、図2の装置のクヌ
ーセンセル32あるいは33も用い、上記成膜条件で作
製した試料についてもエピタキシャル成長することを確
認した。図5は、成膜されたGaNの(0002)面の
X線回折ピーク強度と成膜時の基板温度との関係を示
す。図のように、基板温度が650℃に上がると強度が
非常に小さくなる。さらに、基板温度800℃で基板と
Zn0バッファ層の間の制離が発生した。それ故、上記
の成膜条件の600℃の基板温度が適当であることが分
かる。
Al 0.05 Ga 0.95 N and In
It was confirmed that, for the mixed crystal film of 0.05 Ga 0.95 N, the Knudsen cell 32 or 33 of the apparatus shown in FIG. FIG. 5 shows the relationship between the X-ray diffraction peak intensity of the (0002) plane of deposited GaN and the substrate temperature during deposition. As shown in the figure, when the substrate temperature rises to 650 ° C., the strength becomes very small. Further, at a substrate temperature of 800 ° C., separation between the substrate and the Zn0 buffer layer occurred. Therefore, it can be seen that the substrate temperature of 600 ° C. under the above film forming conditions is appropriate.

【0016】図1は、このようにして成膜したGaN単
結晶膜を用いたpn接合ダイオードの断面構造を示す。
図に示すようにGaAs基板1の(111)面の一部を
マスクしてZn0バッファ層2を形成した。MBEでG
aN単結晶を成膜すると、Zn0バッファ層の上では上
記のようにp型GaN膜3が形成され、Zn0バッファ
層のないGaAs基板1の表面上にはn型GaN膜4が
形成された。p型GaN膜3上にはAu膜、n型GaN
膜4上にはAl膜をそれぞれ真空蒸着法でいずれを約2
00nmの厚さに形成し、トリミングしてAu電極5、A
L電極6を形成した。このようにして、基板1の面に垂
直なpn接合を有するダイオードが作製され、その電圧
・電流特性が整流性を示した。
FIG. 1 shows a sectional structure of a pn junction diode using the GaN single crystal film thus formed.
As shown in the figure, a Zn0 buffer layer 2 was formed by masking a part of the (111) plane of the GaAs substrate 1. G in MBE
When the aN single crystal was formed, the p-type GaN film 3 was formed on the Zn0 buffer layer as described above, and the n-type GaN film 4 was formed on the surface of the GaAs substrate 1 without the Zn0 buffer layer. An Au film and n-type GaN are formed on the p-type GaN film 3.
An Al film is formed on the film 4 by a vacuum vapor deposition method, each of which is about 2
Formed to a thickness of 00 nm and trimmed to Au electrode 5, A
The L electrode 6 was formed. In this way, a diode having a pn junction perpendicular to the surface of the substrate 1 was produced, and the voltage / current characteristics thereof showed rectification.

【0017】上記の実施例ではIII族窒化物半導体とし
てのGaNを製造したが、Alクヌーセンセル32、あ
るいはInクヌーセンセル33を併せ用いることによ
り、Al0. 05Ga0. 95NあるいはIn0. 05Ga0. 95
Nの混晶膜を上記の成膜条件でエピタキシャル成長する
ことを確認した。
Although GaN as a group III nitride semiconductor is manufactured in the above-mentioned embodiment, Al 0.05 Ga 0.95 N or In 0.90 is obtained by using Al Knudsen cell 32 or In Knudsen cell 33 together . 05 Ga 0.95
It was confirmed that the mixed crystal film of N was epitaxially grown under the above film forming conditions.

【0018】[0018]

【発明の効果】本発明によれば、劈開が強い(111)
面を表面とするGaAs単結晶基板を用い、格子不整合
を緩和するZn0よりなるバッファ層を介在させること
により、特別な活性処理を必要としないでIII族窒化物
の劈開性の強い(0001)面を表面とする半導体膜を
エピタキシャル成長させることができた。この膜面は短
波長発生のLD素子の共振面として有効に使用できる。
また、Zn0バッファ層ではp型III族窒化物膜がエピ
タキシャル成長するが、GaAs基板面直接の場合はn
型III族窒化物膜がエピタキシャル成長することを利用
してpn接合ダイオードの製造も極めて簡単にできるよ
うになった。
According to the present invention, the cleavage is strong (111).
By using a GaAs single crystal substrate whose surface is the surface and interposing a buffer layer made of Zn0 that relaxes the lattice mismatch, the cleavage of the group III nitride is strong (0001) without requiring special activation treatment. It was possible to epitaxially grow the semiconductor film having the surface as the surface. This film surface can be effectively used as a resonance surface of an LD element generating a short wavelength.
In addition, a p-type group III nitride film is epitaxially grown on the Zn0 buffer layer, but n is formed directly on the GaAs substrate surface.
The epitaxial growth of the type III nitride film makes it possible to manufacture the pn junction diode very easily.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例により製造されたpn接合ダ
イオードの断面図
FIG. 1 is a sectional view of a pn junction diode manufactured according to an embodiment of the present invention.

【図2】本発明の一実施例に用いたMBE装置の断面図FIG. 2 is a sectional view of an MBE device used in an embodiment of the present invention.

【図3】本発明の一実施例におけるZn0膜のX線回折
強度と基板温度との関係線図
FIG. 3 is a diagram showing the relationship between the X-ray diffraction intensity and the substrate temperature of a Zn0 film in one example of the present invention.

【図4】本発明の一実施例により得られたGaN膜のフ
ォトルミネッセンス・スペクトル図
FIG. 4 is a photoluminescence spectrum diagram of a GaN film obtained according to an example of the present invention.

【図5】本発明の一実施例により得られたGaN膜のX
線回折強度と基板温度との関係線図
FIG. 5: X of a GaN film obtained according to an embodiment of the present invention
Diagram of the relationship between line diffraction intensity and substrate temperature

【符号の説明】[Explanation of symbols]

1 GaAs基板 2 Zn0バッファ層 3 p−GaN膜 4 n−GaN膜 5 Au電極 6 Al電極 21、22 真空室 31、32、33 クヌーセンセル 34 ラジカルビーム装置 41 Ga 51 Al 61 In 71 N2 8 基板1 GaAs substrate 2 Zn0 buffer layer 3 p-GaN film 4 n-GaN film 5 Au electrode 6 Al electrode 21, 22 vacuum chamber 31, 32, 33 Knudsen cell 34 radical beam device 41 Ga 51 Al 61 In 71 N 2 8 substrate

───────────────────────────────────────────────────── フロントページの続き (72)発明者 北村 祥司 神奈川県川崎市川崎区田辺新田1番1号 富士電機株式会社内 (72)発明者 上條 洋 神奈川県川崎市川崎区田辺新田1番1号 富士電機株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Shoji Kitamura Shoji Kitamura 1-1, Tanabe Nitta, Kawasaki-ku, Kawasaki-shi, Kanagawa Fuji Electric Co., Ltd. No. 1 inside Fuji Electric Co., Ltd.

Claims (9)

【特許請求の範囲】[Claims] 【請求項1】(111)面を表面とするGaAs単結晶
基板表面上に(0001)面を表面とするZn0膜をエ
ピタキシャル成長させ、このZn0膜上に(0001)
面を表面とするIII族窒化物膜をエピタキシャル成長さ
せることを特徴とするIII族窒化物半導体材料の製造方
法。
1. A Zn0 film having a (0001) plane as a surface is epitaxially grown on a surface of a GaAs single crystal substrate having a (111) plane as a surface, and a (0001) plane is formed on this Zn0 film.
A method for producing a group III nitride semiconductor material, which comprises epitaxially growing a group III nitride film having a surface as a surface.
【請求項2】Zn0膜を不活性ガスとZn0ターゲット
とを用いたマグネトロンスパッタ法により形成する請求
項1記載のIII族窒化物半導体材料の製造方法。
2. The method for producing a group III nitride semiconductor material according to claim 1, wherein the Zn0 film is formed by a magnetron sputtering method using an inert gas and a Zn0 target.
【請求項3】スパッタ時の基板温度を350℃以下とす
る請求項2記載のIII族窒化物半導体材料の製造方法。
3. The method for producing a Group III nitride semiconductor material according to claim 2, wherein the substrate temperature during sputtering is 350 ° C. or lower.
【請求項4】III族窒化物膜を水素を含まない材料を原
料とした分子線エピタキシャル法で形成する請求項1な
いし3のいずれかに記載のIII族窒化物半導体材料の製
造方法。
4. The method for producing a group III nitride semiconductor material according to claim 1, wherein the group III nitride film is formed by a molecular beam epitaxial method using a material containing no hydrogen as a raw material.
【請求項5】p型伝導を示すIII族窒化物膜を形成する
請求項1ないし4のいずれかに記載のIII族窒化物半導
体材料の製造方法。
5. The method for producing a Group III nitride semiconductor material according to claim 1, wherein a Group III nitride film exhibiting p-type conduction is formed.
【請求項6】分子線エピタキシャル法実施時の基板温度
を625℃以下とする請求項4あるいは5記載のIII族
窒化物半導体材料の製造方法。
6. The method for producing a group III nitride semiconductor material according to claim 4, wherein the substrate temperature during the molecular beam epitaxial method is 625 ° C. or lower.
【請求項7】III族窒化物がGaNである請求項1ない
し6のいずれかに記載のIII族窒化物半導体材料の製造
方法。
7. The method for producing a Group III nitride semiconductor material according to claim 1, wherein the Group III nitride is GaN.
【請求項8】III族窒化物がGaAlNあるいはGaI
nNである請求項1ないし6のいずれかに記載のIII族
窒化物半導体材料の製造方法。
8. A group III nitride is GaAlN or GaI.
7. The method for producing a group III nitride semiconductor material according to claim 1, wherein the group III nitride semiconductor material is nN.
【請求項9】(111)面を表面とするGaAs単結晶
基板の表面上に選択的に(0001)面を表面とするZ
n0膜をエピタキシャル成長させ、このZn0膜上(0
001)面を表面とするp型III族窒化物半導体膜をエ
ピタキシャル成長させ、GaAs露出面上に(000
1)面を表面とするn型III族窒化物半導体膜をエピタ
キシャル成長させることを特徴とするpn接合ダイオー
ドの製造方法。
9. A Z having a (0001) plane as a surface selectively on a surface of a GaAs single crystal substrate having a (111) plane as a surface.
The n0 film is epitaxially grown, and the Zn0 film (0
A p-type group III nitride semiconductor film having a (001) surface as a surface is epitaxially grown, and (000) is formed on the exposed GaAs surface.
1) A method for manufacturing a pn junction diode, which comprises epitaxially growing an n-type group III nitride semiconductor film having a surface as a surface.
JP6412496A 1996-03-21 1996-03-21 Iii group nitride semiconductor and manufacture of p-n junction diode Pending JPH09260290A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
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Publications (1)

Publication Number Publication Date
JPH09260290A true JPH09260290A (en) 1997-10-03

Family

ID=13249018

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6355945B1 (en) * 1998-07-06 2002-03-12 Murata Manufacturing Co., Ltd. Semiconductor optical device and optoelectronic integrated circuit device including a ZnO buffer layer
US6437363B1 (en) 1998-09-25 2002-08-20 Murata Manufacturing Co. Ltd. Semiconductor photonic device
JP2009084074A (en) * 2007-09-27 2009-04-23 Kyocera Corp Substrate, method for growing gallium nitride-based compound semiconductor using the same, and gallium nitride-based compound semiconductor
JP2013051453A (en) * 2006-03-30 2013-03-14 Ngk Insulators Ltd Semiconductor device
JP2020145428A (en) * 2019-03-04 2020-09-10 3−5 パワー エレクトロニクス ゲゼルシャフト ミット ベシュレンクテル ハフツング3−5 Power Electronics GmbH Stack-type high breakdown voltage iii-v group power semiconductor diode

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6355945B1 (en) * 1998-07-06 2002-03-12 Murata Manufacturing Co., Ltd. Semiconductor optical device and optoelectronic integrated circuit device including a ZnO buffer layer
US6437363B1 (en) 1998-09-25 2002-08-20 Murata Manufacturing Co. Ltd. Semiconductor photonic device
JP2013051453A (en) * 2006-03-30 2013-03-14 Ngk Insulators Ltd Semiconductor device
JP2009084074A (en) * 2007-09-27 2009-04-23 Kyocera Corp Substrate, method for growing gallium nitride-based compound semiconductor using the same, and gallium nitride-based compound semiconductor
JP2020145428A (en) * 2019-03-04 2020-09-10 3−5 パワー エレクトロニクス ゲゼルシャフト ミット ベシュレンクテル ハフツング3−5 Power Electronics GmbH Stack-type high breakdown voltage iii-v group power semiconductor diode
US11271117B2 (en) 2019-03-04 2022-03-08 3-5 Power Electronics GmbH Stacked high-blocking III-V power semiconductor diode

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