JPH09252033A - Semiconductor measuring apparatus - Google Patents
Semiconductor measuring apparatusInfo
- Publication number
- JPH09252033A JPH09252033A JP15198796A JP15198796A JPH09252033A JP H09252033 A JPH09252033 A JP H09252033A JP 15198796 A JP15198796 A JP 15198796A JP 15198796 A JP15198796 A JP 15198796A JP H09252033 A JPH09252033 A JP H09252033A
- Authority
- JP
- Japan
- Prior art keywords
- electrode jig
- sense
- force
- measuring device
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、縦型半導体素子の
特性測定、特に組立前のウェハ状態またはチップ状態で
の測定に用いられる半導体測定装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor measuring apparatus used for measuring the characteristics of a vertical semiconductor device, and particularly for measuring in a wafer state or a chip state before assembly.
【0002】[0002]
【従来の技術】半導体基板の上下面に電極を有し、上下
方向に電流が流れるいわゆる縦型半導体素子は、特に大
電流用途に適した構造であり、大容量半導体素子として
多用されている。縦型半導体素子は、組立前にウェハ状
態またはチップ状態での特性測定を行い選別等をした
後、組立を行う。図9(a)は、従来のチップ状態での
測定装置の断面図、同図(b)はウェハ裏面と接触する
電極治具の平面図である。2. Description of the Related Art A so-called vertical semiconductor element having electrodes on the upper and lower surfaces of a semiconductor substrate and allowing a current to flow in the vertical direction is a structure particularly suitable for large current applications and is widely used as a large capacity semiconductor element. Before assembling the vertical semiconductor device, the characteristics are measured in a wafer state or a chip state to be selected and then assembled. FIG. 9A is a cross-sectional view of a conventional measuring device in a chip state, and FIG. 9B is a plan view of an electrode jig that contacts the back surface of the wafer.
【0003】図9(a)において、チップ4は電極治具
1の上に置かれ、電極治具1の真空引き口5から吸引さ
れて固定されている。チップ4の上面には、電極7が設
けられており、電圧検知用のセンス針8と電流検知用の
フォース針9が接触している。図9(b)においては、
電極治具1がやはり電圧検知用のセンス部2と電流検知
用のフォース部3とに分けられているのが見られる。チ
ップ4は双方に接触するように置かれる。このようにセ
ンス部2とフォース部3とに分け、いわゆるケルビン接
続をするのは、チップ4の裏面と電極治具1とのコンタ
クト抵抗を避けるためである。In FIG. 9A, the chip 4 is placed on the electrode jig 1 and is sucked and fixed from the vacuum outlet 5 of the electrode jig 1. An electrode 7 is provided on the upper surface of the chip 4, and a sense needle 8 for voltage detection and a force needle 9 for current detection are in contact with each other. In FIG. 9 (b),
It can be seen that the electrode jig 1 is also divided into a voltage sensing section 2 and a current sensing force section 3. The chips 4 are placed so as to contact both sides. The reason why the sense portion 2 and the force portion 3 are divided and the so-called Kelvin connection is performed is to avoid contact resistance between the back surface of the chip 4 and the electrode jig 1.
【0004】[0004]
【発明が解決しようとする課題】ウェハにはチップが沢
山(20〜1500ヶ)作り込まれており、従来のウェ
ハ状態またはチップ状態での特性チェックは、チップ毎
の裏面へのコンタクト条件に関して次のような不安定要
因を含んでいる。 1)チップ裏面と電極治具とのコンタクト抵抗のばらつ
き 2)電極治具への真空吸着力のばらつき 3)チップ裏面とフォース部、センス部電極治具との接
触面積のばらつき 4)フォース部接触点からの距離のばらつき(電極治具
の比抵抗が大きい場合) 図9のような従来の方法においては、フォース部とセン
ス部とがそれぞれ一ヶ所しかなく、一部分でしか接触し
ていないため、接触抵抗が大きく、正確な測定ができな
かった。A large number of chips (20 to 1500) are formed on a wafer, and the conventional characteristic check in the wafer state or the chip state is as follows regarding contact conditions to the back surface of each chip. It includes instability factors such as. 1) Variation in contact resistance between chip back surface and electrode jig 2) Variation in vacuum suction force on electrode jig 3) Variation in contact area between chip back surface and force part, sense part electrode jig 4) Contact at force part Variation in distance from a point (when the specific resistance of the electrode jig is large) In the conventional method as shown in FIG. 9, since the force portion and the sense portion have only one place and are in contact with each other only partially, The contact resistance was too high to measure accurately.
【0005】図5は、バイポーラトランジスタの組立前
後の飽和電圧の関係図である。図9の従来の方法で測定
した例を□で示した。横軸は組立前チップ状態での飽和
電圧、縦軸は組立後のそれである。組立後の方が飽和電
圧が小さい。すなわち、チップ状態での測定値は本当の
値を示していないことになる。また、ばらつきが大き
い。FIG. 5 is a relationship diagram of the saturation voltage before and after the assembly of the bipolar transistor. An example measured by the conventional method of FIG. 9 is shown by □. The horizontal axis is the saturation voltage in the chip state before assembly, and the vertical axis is that after assembly. The saturation voltage is lower after assembly. That is, the measured value in the chip state does not show a true value. Also, the variation is large.
【0006】このように、縦型半導体素子の静特性測定
(飽和電圧、電圧降下)の場合、これらコンタクト抵抗
がばらつくために正確に測定できず、その結果正確な判
断は組立後にしかできなかった。以上の問題に鑑みて本
発明の目的は、ウェハ状態またはチップ状態で正確な測
定の行える測定装置を提供することにある。As described above, in the static characteristic measurement (saturation voltage, voltage drop) of the vertical semiconductor device, the contact resistances cannot be accurately measured because of variations in contact resistance, and as a result, accurate determination can be made only after assembly. . In view of the above problems, an object of the present invention is to provide a measuring device that can perform accurate measurement in a wafer state or a chip state.
【0007】[0007]
【課題を解決するための手段】上記課題解決のため本発
明の半導体測定装置は、半導体素子裏面と接触する電極
治具がフォース部とセンス部とに分けられ、それらが互
いに入り組んで配置されているものとする。特に、フォ
ース部とセンス部との電極治具がかみ合った櫛歯状であ
るものとする。In order to solve the above problems, in the semiconductor measuring device of the present invention, the electrode jig which is in contact with the back surface of the semiconductor element is divided into a force part and a sense part, which are arranged intricately. Be present. In particular, it is assumed that the electrode jigs of the force portion and the sense portion are in the shape of comb teeth which are engaged with each other.
【0008】そのようにすれば、半導体素子裏面でのコ
ンタクト抵抗を低減できる。更に、少なくともフォース
部の電極治具の表面が、例えば溝状の凹凸を有するもの
とする。そのようにすれば、凹部で真空引き、凸部電極
コンタクトを持たせることにより、理想的なコンタクト
を実現できる。By doing so, the contact resistance on the back surface of the semiconductor element can be reduced. Further, at least the surface of the electrode jig in the force portion has, for example, groove-shaped irregularities. By doing so, an ideal contact can be realized by vacuuming the concave portion and providing a convex electrode contact.
【0009】電極治具のフォース部の面積がセンス部の
それより大なるものとする。そのようにして接触面積を
広くすれば、大電流を流したとき電流密度が過大になる
のを防止できる。また、電極治具のセンス部に真空引き
口が設けられているとよい。そのようにすれば、コンタ
クト抵抗を低減する必要のあるセンス部とのコンタクト
が良好になる。The area of the force portion of the electrode jig is larger than that of the sense portion. By thus widening the contact area, it is possible to prevent the current density from becoming excessive when a large current is passed. Also, a vacuum outlet may be provided in the sensing portion of the electrode jig. By doing so, good contact with the sense portion, which requires a reduction in contact resistance, becomes good.
【0010】電極治具のフォース部とセンス部とが互い
に入り組んだ同心円状に配置されており、また真空引き
口が同心円状に配置されているものとする。そのように
すれば、円形のウェハ状態での測定に適し、ウェハ内の
どの部分のチップにおいてもコンタクト抵抗が抑えられ
る。It is assumed that the force part and the sense part of the electrode jig are arranged in concentric circles intricately interdigitated with each other, and the vacuum outlets are arranged in concentric circles. By doing so, it is suitable for measurement in a circular wafer state, and the contact resistance can be suppressed at any part of the chip in the wafer.
【0011】[0011]
【発明の実施の形態】以下、図7と共通の部分に同一の
符号を付した図面を引用しながら、本発明の実施例につ
いて説明する。 [実施例1]図4は本発明第一の実施例の半導体測定装
置の電極治具の平面図である。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings in which the same parts as those in FIG. [Embodiment 1] FIG. 4 is a plan view of an electrode jig of a semiconductor measuring apparatus according to the first embodiment of the present invention.
【0012】図4において、センス部2とフォース部3
とが互いに入り組んだ櫛歯状に加工されている。大きさ
は約50×50mm2 である。電極治具のほぼ中央部の
センス部2に真空引き口5が開けられている。このた
め、電圧検知用のセンス部2とチップ4の裏面とが多く
の点で接触することになり、大幅にコンタクト抵抗が低
減できる。In FIG. 4, the sense unit 2 and the force unit 3
And are processed into a comb-like shape that is intricate with each other. The size is about 50 × 50 mm 2 . A vacuum outlet 5 is opened in the sensing portion 2 in the central portion of the electrode jig. Therefore, the sense portion 2 for voltage detection and the back surface of the chip 4 come into contact with each other at many points, and the contact resistance can be significantly reduced.
【0013】電極治具のフォース部3の面積がセンス部
2のそれより大きく、接触面積が広いので、大電流を流
したとき電流密度が過大になるのを防止できる。更に、
電極治具の表面に金メッキを施せば、より安定的に測定
できる。櫛歯の形状は、フォース部3を太く、センス部
2を細くすることもできる。また、根元を太く、先端を
細くしてもよい。Since the area of the force part 3 of the electrode jig is larger than that of the sense part 2 and the contact area is large, it is possible to prevent the current density from becoming excessive when a large current is passed. Furthermore,
Gold plating on the surface of the electrode jig enables more stable measurement. The shape of the comb teeth may be such that the force portion 3 is thick and the sense portion 2 is thin. The root may be thick and the tip may be thin.
【0014】また、櫛歯の形状は、島状に配置し、相互
に立体的に交差させてもよい。 [実施例2]図1は本発明第二の実施例の半導体測定装
置の電極治具の平面図であり、第一の実施例の変形例と
いえる。電極治具1は、センス部2とフォース部3とか
らなっている。センス部2の表面にハッチングがほどこ
されているのは、表面上に溝6が形成されていることを
表している。フォース部3の表面上にも溝6が形成され
ているが、図が煩雑になるのを避けて、センス部2のみ
にハッチングした。Further, the comb teeth may be arranged in an island shape and three-dimensionally cross each other. [Embodiment 2] FIG. 1 is a plan view of an electrode jig of a semiconductor measuring apparatus according to a second embodiment of the present invention, which can be said to be a modification of the first embodiment. The electrode jig 1 includes a sense section 2 and a force section 3. Hatching on the surface of the sense part 2 means that the groove 6 is formed on the surface. Although the groove 6 is formed on the surface of the force portion 3, only the sense portion 2 is hatched in order to avoid making the drawing complicated.
【0015】図2は図1の中央部の拡大図である。セン
ス部2の両側はフォース部3であり、両部分の表面には
幅0.2mm、深さ0.3mmの溝6が縦横に掘られて
いる。センス部1には、真空引き口5の開口が見られ
る。この例では、図1の第一の実施例と同様にセンス部
2とフォース部3とが互いに入り組んで加工されている
上、更に、センス部2とフォース部3の表面に、凹凸を
つけることにより、接触点が増すだけでなく、真空引き
がよくなり、更にコンタクト抵抗の低減ができる。FIG. 2 is an enlarged view of the central portion of FIG. Both sides of the sense part 2 are force parts 3, and grooves 6 having a width of 0.2 mm and a depth of 0.3 mm are dug vertically and horizontally on the surfaces of both parts. An opening of the vacuum suction port 5 can be seen in the sense unit 1. In this example, the sense portion 2 and the force portion 3 are intricately processed in the same manner as in the first embodiment of FIG. 1, and further, the surface of the sense portion 2 and the force portion 3 is made uneven. As a result, not only the number of contact points is increased, but also vacuuming is improved and the contact resistance can be further reduced.
【0016】図3は図1の電極治具を用いた半導体測定
装置のA−A’線に沿った断面図である。電極治具1の
センス部2、フォース部3の表面の溝6が良く分かる。
溝6があるため、チップ4と電極治具1とが多点で接触
するようになっている。7はチップ4に設けられた上部
電極、8はセンス針、9はフォース針である。図5に、
図4の半導体測定装置で測定したバイポーラトランジス
タの飽和電圧と、組立後のそれとの関係も示した。この
例を●で示す。この場合、組立後の飽和電圧は、チップ
状態での測定値より約0.5V大きい。また、ばらつき
が小さい。調査の結果、この0.5Vの増加は、ワイヤ
ボンディングによるものであることがわかった。従っ
て、チツプ状態での測定値は、信頼できるものであり、
図1の半導体測定装置を使用すれば、大幅に測定精度が
向上することになる。FIG. 3 is a sectional view taken along the line AA 'of the semiconductor measuring device using the electrode jig shown in FIG. The grooves 6 on the surface of the sense portion 2 and the force portion 3 of the electrode jig 1 can be clearly seen.
Because of the groove 6, the chip 4 and the electrode jig 1 are in contact with each other at multiple points. Reference numeral 7 is an upper electrode provided on the chip 4, 8 is a sense needle, and 9 is a force needle. In FIG.
The relationship between the saturation voltage of the bipolar transistor measured by the semiconductor measuring device of FIG. 4 and that after assembly is also shown. This example is shown by ●. In this case, the saturation voltage after assembly is about 0.5 V higher than the measured value in the chip state. Also, the variation is small. As a result of investigation, it was found that the increase of 0.5V was due to wire bonding. Therefore, the measured values in the chip state are reliable,
If the semiconductor measuring device of FIG. 1 is used, the measurement accuracy will be greatly improved.
【0017】このように、チップ状態またはウェハ状態
で正確な測定が行えるので、正確な選別ができ、組立工
数等の削減によりコストの低下につながる。また、特性
改善へのフィードバックが速くなる。 [実施例3]図6は、本発明第三の実施例の半導体測定
装置の電極治具の平面図である。真空引き口5が2個設
けられている。このように真空引き口5を多数設けれ
ば、チップ4と電極治具1との接触点が増加し、コンタ
クト抵抗は小さくできる。 [実施例4]図7は、本発明第四の実施例の半導体測定
装置の電極治具の平面図であり、ウェハ状態での測定に
適するものである。As described above, since accurate measurement can be performed in a chip state or a wafer state, accurate selection can be performed, and the number of assembling steps can be reduced, leading to cost reduction. In addition, feedback to improve the characteristics becomes faster. [Embodiment 3] FIG. 6 is a plan view of an electrode jig of a semiconductor measuring apparatus according to a third embodiment of the present invention. Two vacuum outlets 5 are provided. By providing a large number of vacuum outlets 5 in this manner, the number of contact points between the chip 4 and the electrode jig 1 increases, and the contact resistance can be reduced. [Embodiment 4] FIG. 7 is a plan view of an electrode jig of a semiconductor measuring apparatus according to a fourth embodiment of the present invention, which is suitable for measurement in a wafer state.
【0018】この第四の実施例では、ウェハ直径に応じ
て、例えば6インチウェハ用には約170mmの直径の
電極治具1が用いられる。同心円状に分けられたセンス
部2とフォース部3とが入り組んでチップ4の裏面と接
する電極治具1を構成している。11はセンス部2とフ
ォース部3との間に埋め込まれた絶縁物である。真空引
き口5は中心に設けられている。ウェハと電極治具1間
の吸着をよくするため、電極治具1の表面に幅1mm、
深さ0.5mmの真空溝10が形成されている。これに
より、ウェハ全体に真空状態がよくなり、正確な測定が
できる。 [実施例5]図8は、本発明第五の実施例の半導体測定
装置の電極治具の平面図であり、これもウェハ状態での
測定に適するものである。In the fourth embodiment, the electrode jig 1 having a diameter of about 170 mm is used for a 6-inch wafer, depending on the diameter of the wafer. The electrode jig 1 that is in contact with the back surface of the chip 4 is configured by convolving the sense portion 2 and the force portion 3 that are concentrically divided. Reference numeral 11 is an insulator embedded between the sense portion 2 and the force portion 3. The vacuum outlet 5 is provided at the center. In order to improve the adsorption between the wafer and the electrode jig 1, a width of 1 mm on the surface of the electrode jig 1,
The vacuum groove 10 having a depth of 0.5 mm is formed. This improves the vacuum state on the entire wafer and enables accurate measurement. [Embodiment 5] FIG. 8 is a plan view of an electrode jig of a semiconductor measuring apparatus according to a fifth embodiment of the present invention, which is also suitable for measurement in a wafer state.
【0019】この第五の実施例では、同心円状に分けら
れたセンス部2とフォース部3とが入り組んでチップ4
の裏面と接する電極治具1を構成している。センス部2
とフォース部3との表面には溝6が刻まれている。但
し、実施例4と違ってセンス部2に直径1mmの真空引
き口5が多数設けられている。これにより、ウェハ上の
どの部分でもチップ4と電極治具1との接触点が増加す
る。特に、反りを生じたウェハでもコンタクト抵抗は小
さくでき、正確な測定ができる。In the fifth embodiment, the chip 4 is composed of the sense portion 2 and the force portion 3 which are concentrically divided.
The electrode jig 1 is in contact with the back surface of the. Sense part 2
Grooves 6 are engraved on the surfaces of the and force portions 3. However, unlike the fourth embodiment, the sense portion 2 is provided with a large number of vacuum outlets 5 having a diameter of 1 mm. As a result, the number of contact points between the chip 4 and the electrode jig 1 increases at any part on the wafer. In particular, even in the case of a warped wafer, the contact resistance can be reduced and accurate measurement can be performed.
【0020】[0020]
【発明の効果】以上説明したように本発明は、大容量半
導体として用いられる縦型半導体素子の測定装置におい
て、電極治具の電圧検知用のセンス部と、電流検知用の
フォース部とを入り組んだ形に構成することによって、
コンタクト抵抗のばらつきを防止し、ウェハ状態または
チップ状態で正確な測定の行える測定装置を可能にし
た。As described above, according to the present invention, in a measuring apparatus for a vertical semiconductor element used as a large-capacity semiconductor, a voltage detecting sense section of an electrode jig and a current detecting force section are combined. By arranging in an elliptical
We have made possible a measuring device that can prevent the contact resistance from fluctuating and perform accurate measurement in the wafer state or the chip state.
【0021】ウェハ状態またはチップ状態で正確な測定
が行えるので、正確な選別ができ、組立工数等の削減に
よりコストの低下につながる。Since accurate measurement can be performed in a wafer state or a chip state, accurate selection can be performed, and the number of assembling steps can be reduced, leading to cost reduction.
【図1】本発明第二の実施例の測定装置の電極治具の平
面図FIG. 1 is a plan view of an electrode jig of a measuring device according to a second embodiment of the present invention.
【図2】図1の部分拡大図FIG. 2 is a partially enlarged view of FIG. 1;
【図3】本発明第二の実施例の測定装置の断面図FIG. 3 is a sectional view of a measuring apparatus according to a second embodiment of the present invention.
【図4】本発明第一の実施例の測定装置の電極治具の平
面図FIG. 4 is a plan view of an electrode jig of the measuring apparatus according to the first embodiment of the present invention.
【図5】バイポーラトランジスタの組立前後の飽和電圧
の比較図FIG. 5: Comparison diagram of saturation voltage before and after assembly of bipolar transistor
【図6】本発明第三の実施例の測定装置の断面図FIG. 6 is a sectional view of a measuring apparatus according to a third embodiment of the present invention.
【図7】本発明第四の実施例の測定装置の電極治具の平
面図FIG. 7 is a plan view of an electrode jig of a measuring device according to a fourth embodiment of the present invention.
【図8】本発明第五の実施例の測定装置の電極治具の平
面図FIG. 8 is a plan view of an electrode jig of a measuring device according to a fifth embodiment of the present invention.
【図9】(a)は従来の測定装置の断面図、(b)は電
極治具の平面図9A is a sectional view of a conventional measuring device, and FIG. 9B is a plan view of an electrode jig.
1 電極治具 2 センス部 3 フォース部 4 半導体チップ 5 真空引き口 6 溝 7 上部電極 8 センス針 9 フォース針 10 真空溝 11 絶縁物 1 Electrode jig 2 Sense part 3 Force part 4 Semiconductor chip 5 Vacuum suction port 6 Groove 7 Upper electrode 8 Sense needle 9 Force needle 10 Vacuum groove 11 Insulator
Claims (7)
いて、半導体素子裏面でのコンタクト抵抗を低減するた
めに、半導体素子裏面と接触する電極治具がフォース部
とセンス部とに分けられ、それらが互いに入り組んで配
置されていることを特徴とする半導体測定装置。1. An apparatus for measuring characteristics of a vertical semiconductor element, wherein an electrode jig contacting the rear surface of the semiconductor element is divided into a force portion and a sense portion in order to reduce contact resistance on the rear surface of the semiconductor element. A semiconductor measuring device characterized in that they are arranged intricately with each other.
合った櫛歯状であることを特徴とする請求項1に記載の
半導体測定装置。2. The semiconductor measuring device according to claim 1, wherein the electrode jigs of the force portion and the sense portion are in the shape of comb teeth which are engaged with each other.
凸を有することを特徴とする請求項1または2に記載の
半導体測定装置。3. The semiconductor measuring device according to claim 1, wherein at least the surface of the electrode jig of the sensing portion has irregularities.
それより大なることを特徴とする請求項1ないし3のい
ずれかに記載の半導体測定装置。4. The semiconductor measuring device according to claim 1, wherein the area of the force portion of the electrode jig is larger than that of the sense portion.
れていることを特徴とする請求項1ないし4のいずれか
に記載の半導体測定装置。5. The semiconductor measuring device according to claim 1, wherein a vacuum outlet is provided in the sensing portion of the electrode jig.
に入り組んだ同心円状に配置されていることを特徴とす
る請求項1ないし5のいずれかに記載の半導体測定装
置。6. The semiconductor measuring device according to claim 1, wherein the force part and the sense part of the electrode jig are arranged in a concentric circle shape intricately interdigitated with each other.
とを特徴とする請求項6に記載の半導体測定装置。7. The semiconductor measuring device according to claim 6, wherein the vacuum outlets are arranged concentrically.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15198796A JPH09252033A (en) | 1996-01-12 | 1996-06-13 | Semiconductor measuring apparatus |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8-3525 | 1996-01-12 | ||
JP352596 | 1996-01-12 | ||
JP15198796A JPH09252033A (en) | 1996-01-12 | 1996-06-13 | Semiconductor measuring apparatus |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH09252033A true JPH09252033A (en) | 1997-09-22 |
Family
ID=26337126
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15198796A Withdrawn JPH09252033A (en) | 1996-01-12 | 1996-06-13 | Semiconductor measuring apparatus |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH09252033A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004072108A (en) * | 2002-08-02 | 2004-03-04 | Suss Microtec Lithography Gmbh | Equipment securing thin and flexible substrate |
-
1996
- 1996-06-13 JP JP15198796A patent/JPH09252033A/en not_active Withdrawn
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004072108A (en) * | 2002-08-02 | 2004-03-04 | Suss Microtec Lithography Gmbh | Equipment securing thin and flexible substrate |
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