JPH09251789A - Non-volatile semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a storage device suitable for high integration by minimizing a circuit scale of a column system circuit. SOLUTION: This device is provided with flip-flop circuits 14-1, 14-2 of which the number is set to (m), a writing and verifying circuit 16 verifying written data after writing control voltage is selected in accordance with multi-value data when data is written in a memory cell, selected writing control voltage is given to a bit line, and data is written in a memory cell, when the number of data of multi-values by which writing data for a memory cell is latched and writing data from a memory cell is sense-latched is assumed to 2<m> =n (m is natural number of 2 or more). And the writing and verifying circuit 16 is controlled by writing data of (n) pieces latched by the flip-flop circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable non-volatile semiconductor memory device (EEPROM), and more particularly to a multi-value memory EEPROM.

[0002]

2. Description of the Related Art As one of the methods for increasing the capacity of an EEPROM, a multi-value storage EEPROM is known in which one memory cell stores n (n ≧ 3) value information. For example, in the four-value storage type, each cell has one of four kinds of threshold voltages, which is (0, 0),
It corresponds to 2-bit information represented by (0,1), (1,0), and (1,1).

In order to read the data of the memory cell storing the n value, the data read from the cell is compared with (n-1) reference voltages. Therefore, conventionally, (n-1) sense amplifiers have been required (for example, Japanese Patent Laid-Open No. 61-11).
7796).

In the 4-value storage type EEPROM, the storage density of the memory cells is doubled and the area occupied by the memory cells is halved as compared with the binary storage type EEPROM, whereas the sense amplifier is The area occupied is tripled, and the effect of high density is reduced. In particular, an E type that has a sense amplifier for each bit line to perform page read
In the EPROM, an increase in the number of sense amplifiers hinders an increase in capacity.

On the other hand, in Japanese Unexamined Patent Publication No. 62-54896, the number of sense amplifiers is reduced by controlling the reference voltage of other sense amplifiers by the output of the sense amplifier which discriminates the cell data. A read-only memory characterized by is disclosed.

On the other hand, in a multi-value storage EEPROM which stores n (n ≧ 3) kinds of threshold voltages in memory cells, when the stored data is written, the respective threshold voltages are
It needs to be distributed in a narrower range. For this reason, writing is done in small increments, and it is checked whether each memory cell has been written to the target threshold range between writing, and if there is a cell with insufficient writing, only that cell is written. The additional write is performed, and the bit-by-bit verify that controls so that the optimum write is performed for each memory cell is effective. The verification for each bit is disclosed in Japanese Patent Laid-Open No. 3-295098.

Further, bit-by-bit verification for a multi-value storage EEPROM is disclosed in Japanese Patent Laid-Open No. 7-93979. However, the device disclosed in Japanese Patent Laid-Open No. 7-93979 requires (n-1) sense amplifiers and (verify) circuits. Therefore,
A memory cell can store a large amount of data in a chip having the same area by storing a larger amount of data, but a circuit for controlling read / write of data becomes large in scale and highly integrated. There was a difficulty in converting.

[0008]

As described above, in the conventional multi-value storage EEPROM having a verify function, when the number of multi-valued data is "n (n is a natural number of 3 or more)", (n -1) The verification circuits were required.
For this reason, (n-1) sense amplifiers / data latch circuits are also required depending on the verify circuit.

Due to the above circumstances, the circuit scale of the circuit connected to the bit line, that is, the column system circuit, particularly the sense amplifier / data latch circuit and the verify circuit becomes enormous, which is a bottleneck for high integration. It has become.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to reduce the circuit scale of a column system circuit, in particular, by reducing the number of sense amplifiers / data latch circuits and verify circuits. A non-volatile semiconductor memory device suitable for integration is provided.

[0011]

In order to achieve the above object, in a nonvolatile semiconductor memory device according to the present invention, a memory cell array in which memory cells for storing multi-valued data are arranged in a matrix. A latch function that latches write data to the memory cell when writing data to the memory cell, and a sense latch function that senses and latches read data from the memory cell when reading data from the memory cell And the number of the multi-valued data is n, the number of the latch function and the sense / latch function is m (m is 2 ^(m-1)
<N ≦ 2 ^m (m is an integer of 2 or more)), the bit line control circuit and the memory cell are electrically connected to each other, and data is written to the memory cell. At this time, when the write data is guided from the latch function to the memory cell and the data is read from the memory cell, a bit line that guides the read data from the memory cell to the sense latch function and data to the memory cell. When writing, a write control voltage corresponding to the multi-valued data is selected according to the write data latched by the latch function, and a write circuit that applies the selected write control voltage to a bit line and data to the memory cell And a verify circuit for verifying the written data after the writing of The write circuit, characterized by being configured to be controlled by the n write data latched in the latch function.

The latch function changes the data of the memory cell when the write data latched by the latch function is written to the memory cell when the result of the verify read operation is good. The feature is that the data is updated to the data when there was not.

Further, during the verify read operation, input data to the latch function is provided by the verify circuit and the write circuit according to the latched write data so that the write data once updated is not changed. It is characterized by controlling.

Further, a memory cell array composed of a plurality of memories having a charge storage unit capable of storing N-value (N ≧ 3) data, a plurality of bit lines, a plurality of word lines, and a plurality of program control circuits. , With multiple data circuits,
The program control circuit 1) selects the memory cell, 2) applies a write voltage to the selected memory cell, and the data circuit sets ^M to a natural number satisfying 2 ^M-1 <N ≦ 2 ^M. Sometimes composed of M latch circuits, 1)
Holding write control data of first, second, ..., Nth logic levels for controlling write control voltages applied to the respective corresponding memory cells selected by the program control circuit, 2) the write control A voltage is applied to each of the corresponding memory cells, and 3) only the write state of the memory cell corresponding to the data circuit holding the write control data of a logic level other than the first is selectively detected. ) Changing the logic level of the write control data of the data circuit corresponding to the memory cell that has reached a predetermined write state to the first logic level, and 5) a memory that has not reached the predetermined write state. Holding the logic level of the write control data of the data circuit corresponding to the cell, and 6) writing of the first logic level. A nonvolatile semiconductor memory device for holding a logic level of write control data of the data circuit holding control data at the first logic level, wherein the write is performed by a combination of states of the M latch circuits. The feature is that data is updated.

Further, the verify circuit for updating the write data is characterized by generating a write control voltage.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a configuration diagram showing a configuration of a multi-value storage NAND type EEPROM according to the first embodiment of the present invention.

As shown in FIG. 1, the multi-value storage NAND type EEPROM according to the first embodiment has a configuration called an open bit type. The open bit type multi-value storage NAND type EEPROM is a memory cell array 1A configured by arranging memory cells in a matrix,
Row related circuits 2A, 2B provided for each 1B
And a column system circuit 3 ^** commonly used in each of the memory cell arrays 1A and 1B.

The row related circuits 2A and 2B receive the address signal output from the address input circuit (address buffer) 4 and select a row of the memory cell array based on the received address signal. A word line drive circuit for driving the word line of the memory cell array based on the output of the. NAND type EEPR
In the case of OM, the word line is a select gate SG (SGA, S
GB) and control gate CG (CGA, CGB). The word line drive circuit can be read as a control gate / select gate drive circuit.

Further, the column system circuit 3 ^** commonly used in each of the memory cell arrays 1A and 1B receives the address signal output from the address buffer 4 and, based on the received address signal, the column of the memory cell array. And a column select line drive circuit that drives a column select line that selects a column of the memory cell array based on the output of the column decoder.

Further, the column system circuit 3 ^** includes a data circuit (bit line control circuit) for temporarily holding the write data to the memory cell and reading the data of the memory cell. There is.

The bit line control circuit uses the data input / output line IO.
Through the data input / output circuit (data input / output buffer)
5 is connected. In addition, the bit line control circuit causes the memory cell of the memory cell array 1A via the bit line BLa and the memory cell array 1B via the bit line BLb.
Of memory cells.

When writing data, the bit line control circuit receives the write data from the data input / output buffer 5 and inputs the received write data to the memory cell. When reading data, the bit line control circuit receives the read data from the memory cell and outputs the received read data to the data input / output buffer 5.

The data input / output buffer 5 performs data input / output control and guides write data input from the outside of the EEPROM to the memory core, or reads read data from the memory core to the outside of the EEPROM. To output.

The write end detection circuit 18 detects whether or not the data write is completed based on the output of the bit line control circuit.

FIG. 2 is a configuration diagram showing the configurations of the memory cell array and the column system circuit shown in FIG. FIG.
2 is a diagram showing the memory cell shown in FIG. 2, in which FIG.
FIG. 3B is a sectional view of the memory cell transistor shown in FIG.

As shown in FIG. 2, the memory cell array 1
Memory cells MC are arranged in a matrix in each of A and 1B.

Further, the column system circuit 3 ^** includes m data circuits (bit line control circuits) 6 ^** . The bit line control circuit 6 ^** includes one bit line BLa and one bit line BLa.
It is connected to the book bit line BLb.

Further, as shown in FIG.
In the EEPROM, one cell MC has a plurality of memory cell transistors M1 to M4 connected in series.
Are included to form a NAND cell MC. One end of the cell MC is connected to the bit line BL via the selection transistor S1, and the other end is connected to the source line VS via the selection transistor S2. The group of memory cell transistors M sharing the control gate CG form a unit called a "page". Data writing and reading are performed simultaneously in "pages". Also,
A group of memory cell transistors M connected to the four control gates CG1 to CG4 form a unit called a “block”. The "page" and the "block" are selected by the control gate / select gate driving circuit.

Further, as shown in FIG. 3B, one memory cell transistor M has a floating gate (charge storage layer) and a control gate CG which are stacked, and the amount of electrons stored in the floating gate. Then, the data is stored. The stored amount of electrons can be read as the threshold value of the memory cell transistor.

Data is erased by selecting transistor S1,
This is performed for all of the memory cell transistors M connected in series during S2. Memory cell transistor M
When erasing data from the memory cell transistor M, the control gate CG of the memory cell transistor M is grounded and a high positive potential is applied to the p-type well or the p-type substrate. As a result, the electrons accumulated in the floating gate are not stored in the p-type well or p-type well.
Emitted to the mold substrate. Data writing is performed on all the memory cell transistors connected to one control gate CG. When writing data to the memory cell transistor M, electrons are injected into the floating gate, as opposed to erasing data. The amount of electrons injected into the floating gate is the threshold voltage of the memory cell transistor M,
Can be read.

FIG. 4 is a diagram showing the threshold distribution of the memory cell transistors in multi-value storage.

FIG. 4 shows a case where four values of data "1", data "2", data "3", and data "4" are stored in one memory cell transistor.

As shown in FIG. 4, when the data is erased, the threshold value of the memory cell transistor M is, for example, negative. The data “1” corresponds to the case where the threshold value is negative. The data “2” corresponds to when the threshold value is 0.5 V or more and 0.8 V or less. The data “3” corresponds to when the threshold value is 1.5 V or more and 1.8 V or less.
Data “4” corresponds to a threshold value of 2.5 V or more and 2.8 V or less.

FIG. 5 is a circuit diagram of the bit line control circuit shown in FIG.

Incidentally, FIG. 2 shows the bit line control circuit 6
^{Although the configuration in which **} is connected to one bit line has been illustrated, in FIG. 5, the configuration in which the bit line control circuit 6 ^** is connected to four bit lines is illustrated and described.

As shown in FIG. 5, the bit line control circuit 6 ^**
Includes two flip-flop circuits 14-1 and 14-2. The flip-flop circuits 14-1 and 14-2 are connected to the left and right four bit lines, respectively. During operation, one bit line is selected from the four bit lines on the left and one on the right, and the selected bit line is connected to the flip-flop circuits 14-1 and 14-2. Both the flip-flop circuits 14-1 and 14-2, when reading data,
It functions as a sense amplifier that amplifies and latches read data, and functions as a data latch that latches write data when writing data. In other words, the flip-flop circuits 14-1 and 14-2 are sense amplifier / data latch circuits. Further, the flip-flop circuits 14-1 and 14-2 are connected to a write / verify circuit 16 which also serves as a data write circuit and a verify circuit.

The write / verify circuit 16 writes the data into the flip-flop circuits 14-1 and 14-2.
Depending on the combination of the latched data
One of the write control voltages VA1, VA2, VB1 and VB2 is output to the bit line. Further, when reading data or reading data for verification, the voltage of the bit line is controlled according to the combination of the latch data latched by the flip-flop circuits 14-1 and 14-2.

Next, the operation of the bit line control circuit shown in FIG. 5 will be described.

FIG. 6, FIG. 7 and FIG. 8 are operation waveform diagrams showing normal read operation and verify operation, respectively. In the operation waveform diagrams of FIGS. 6, 7, and 8, the normal read operation is shown by a solid line, and the verify operation is shown by a broken line only where it differs from the normal read operation.

Further, FIGS. 9, 10 and 11 respectively show
FIG. 6 is an operation waveform diagram showing a write operation.

First, a normal read operation will be described.

As shown in FIGS. 6, 7 and 8, first, the selected bit line BLa is set to 1.2V and the reference bit line B is set to 1.2V.
Lb is charged to 1.0 V and then floated. Two select gates S of the selected row
The potentials of G1 and SG2 and the potential of the non-selected control gate CG are set to 4V, respectively. The potentials of the selected control gates CG are sequentially set to 0V, 1V and 2V.

The memory cell transistor M has data "1".
, The memory cell transistor M becomes conductive when the potential of the selected control gate CG is 0V. Therefore, the bit line is discharged (that is, the source line V
(Current flows toward S) and the voltage of the bit line becomes 0V. At this time, when the memory cell transistor M stores other data, no current flows through the bit line, and the voltage of the bit line remains 1.2V.

After that, the voltage of the selected bit line BLa and the voltage of the reference bit line BLb (1.0 V) are simultaneously applied to the two flip-flop circuits 14-1 and 14-2, respectively. When the data is "1", both the node D1A of the flip-flop circuit 14-1 and the node D2A of the flip-flop circuit 14-2 are "L", and when the data is other data, the nodes D1A and D2A are both "H". become.

Then, the potential of the selected control gate CG is raised from 0V to 1V, and it is checked whether or not a current flows through the bit line. Set the potential of the selected control gate CG to 1
When the memory cell transistor M stores the data “1” or the data “2” when it is raised to V, the voltage of the bit line becomes 0V. When the memory cell transistor M stores the data “3” or the data “4”, the voltage of the bit line remains 1.2V.

Thereafter, the voltage of the selected bit line BLa and the voltage of the reference bit line BLb are connected to the first flip-flop circuit 14-1. And the data “1”
, Both nodes D1A and D2A remain "L", when data "2", nodes D1A and D2A are "L and H" respectively, and when other data, node D1
Both 1A and D2A become "H" level.

Then, the potential of the selected control gate CG is raised from 1V to 2V, and it is checked whether or not a current flows through the bit line. Set the potential of the selected control gate CG to 2
When the memory cell transistor M stores the data “1”, the data “2”, or the data “3” when it is raised to V, the voltage of the bit line becomes 0V. When the memory cell transistor M stores the data "4", the voltage of the bit line remains 1.2V.

When the memory cell transistor M stores data "2", that is, the node D1A,
When D2A is "L, H", respectively, the voltage V
By setting B2 to "H", the voltage of the bit line is corrected to "H".

Thereafter, the voltage of the selected bit line BLa and the voltage of the reference bit line BLb are respectively connected to the second flip-flop circuit 14-2. When the data is "1", the nodes D1A and D2A both remain "L", and when the data is "2", the node D1 is
A and D2A are "L and H", respectively. (In the case of the data "2", the node D2A is supposed to be "L" by nature, but the potential of the bit line BLa is corrected to "H" level by using the "L" of the node D1A. When the data is "3", the node D1A,
When D2A is "H, L" and data "4", both nodes D1A, D2A are "H". In this way, the four types of threshold levels read from the memory cell transistor M are supplied to the flip-flop circuit 1
It is possible to make a one-to-one correspondence with each of the four types of latch data 4-1 and 14-2.

FIG. 12 is a diagram showing a correspondence relationship between the threshold level of the memory cell transistor and the latch data (read data).

Next, the write operation will be described.

For the selected bit line, the voltage VA1 = VM8 (about 8V) and the voltage VA2 are supplied from the bit line control circuit.
= 2V, voltage VB1 = 1V, or voltage VB2 = 0V is supplied. Voltage VA1, VA2, VB1, VB2
Is selected according to write data, that is, four types of latch data latched by the two flip-flop circuits 14-1 and 14-2.

FIG. 13 is a diagram showing a correspondence relationship between latch data (write data) and threshold values of memory cell transistors.

The voltages VA1, VA2, VB1 and VB2 are
Writing of data “1”, ..., Writing of data “4” are respectively supported. Potential value VM8 of voltage VA1
Is the potential VPP of the control gate CG and the substrate (channel)
When the potential difference from the potential of (VPP-VM8) is set to a value such that electrons are not injected into the floating gate.

In order to write data to the memory cell transistor M belonging to the selected row, the potential of the selected control gate CG is set to the high voltage VPP (20V).
To the potential) of the unselected control gate CG,
To transfer the potential value VM8, the voltage VM10CG (1
The potential of the select gate SG1 is set to 0 V) so that the direct current from the bit line does not flow,
In order to transfer the potential value of VM2, the voltage of VM2
Each is set to 10 SG (about 10 V). Further, the potential value VM8 is applied to the non-selected bit line in order not to change the threshold voltage of the memory cell transistor M belonging to the non-selected column. This is the voltage V
In order to transfer the potential value VM8 to the BLA and the potential value VM8, the transfer gate circuit drive signal BLC2D-BL
This is performed by setting C4D and the signal DTCBB to the voltage VM10BL (about 10V). Similarly, the voltage VA1
= NVM well voltage VBITH in which a P-channel transistor forming a flip-flop circuit is formed to transfer VM8, and a signal BLC1 and a signal VRF
Y1A and signal VRFYA are applied to voltage VM10BL, respectively.
To

The self-boost writing method (KDSu
h et al., 1995 ISSCC Digest of Technical Papers, p
p.128-129), the potential value VM8, voltage VM10SG, and voltage VM10BL are 3V and 3V, respectively.
It may be V or 5V.

Next, the verify read operation will be described.

The selected bit line BLa and the reference bit line BLb are respectively 1.2 as in the case of reading.
It is charged to V, 1.0V and then floated. Two select gates SG1 and SG of the selected row
The potential of 2 and the potential of the non-selected control gate CG are set to 4V. The potentials of the selected control gates CG are 0.
It is set to 5V, 1.5V and 2.5V. These potentials are
It corresponds to verification of data "2", verification of data "3", and verification of data "4".

The write data shown in FIG.
From the correspondence with the threshold level of the memory cell transistor, if the writing of the data “2” is sufficient, the latch data of the second flip-flop circuit 14-2 is inverted to be the writing data of the data “1”. If it is changed and the writing of the data “2” is insufficient, the latch data of the flip-flop circuit 14-2 may be left as it is.

Similarly, if the writing of the data "3" is sufficient, the latch data of the first flip-flop circuit 14-1 is inverted and changed to the write data of the data "1", and the data "3" of the data "3" is written. If the writing is insufficient, the latch data of the flip-flop circuit 14-1 is left as it is.

If the writing of the data "4" is sufficient, the first and second flip-flop circuits 14-1 and 14-1
Invert the latch data of -2 and change it to the write data of the data "1". If the write of the data "4" is insufficient, two flip-flop circuits 14-1 and 14-1 are provided.
Leave the latch data of 4-2 as it is.

First, the potential of the selected control gate CG is set to 0.5 V to verify the data "2".
When the read threshold value of the memory cell transistor M corresponds to the data "1", a current flows through the bit line, and the voltage of the bit line becomes 0V. When the read threshold values of the memory cell transistor M correspond to data "2", "3", and "4", respectively, no current flows through the bit line and the voltage of the bit line is reduced. Remains at 1.2V.

In order not to change the latch state of the flip-flop circuit which is going to write the data "1", the data "3" or the data "4", the voltage of each bit line is changed to "H", "H". , “L”, and then the voltage of the selected bit line BLa and the reference bit line BLb
Voltage of the second flip-flop circuit 14-2
Give to. At this time, for the flip-flop circuit in which the writing of the data “2” is not latched, the latch state is not changed, and for the flip-flop circuit in which the writing of the data “2” is latched, If the data "2" is sufficiently written, the latch state is changed to the latch state in which the data "1" is written, and conversely, if the data "2" is not sufficiently written,
The latched state remains.

Then, the potential of the selected control gate CG is set to 1.5 V to verify the data "3". When the read threshold value of the memory cell transistor M corresponds to data "1" or data "2", a current flows through the bit line, and the voltage of the bit line becomes 0V. When the read threshold value of the memory cell transistor M corresponds to data "3" or data "4", no current flows in the bit line and the voltage of the bit line is 1. It remains at 2V.

In order not to change the latched state of the flip-flop circuit which is going to write data "1", data "2" or data "4", the voltage of each bit line is changed to "H", "H". , “L”, and then the voltage of the selected bit line BLa and the reference bit line BLb
Of the first flip-flop circuit 14-1
Give to. At this time, for the flip-flop circuit in which the writing of the data “3” is not latched, the latched state is not changed, and for the flip-flop circuit in which the writing of the data “3” is latched, If the data "3" is sufficiently written, the latch state is changed to the latch state of writing the data "1", and conversely, if the data "3" is not sufficiently written,
The latched state remains.

Finally, the potential of the selected control gate CG is set to 2.5 V to verify the data "4". When the read threshold value of the memory cell transistor M corresponds to the data “1”, the data “2”, or the data “3”, a current flows through the bit line. The voltage becomes 0V. When the read threshold value of the memory cell transistor M corresponds to data "4", no current flows through the bit line and the voltage of the bit line remains 1.2V.

In order not to change the latch state of the second flip-flop circuit 14-2 which is going to write the data "1", the data "2", or the data "3", each bit line voltage is set to "H". Then, the voltage of the selected bit line BLa and the voltage of the reference bit line BLb are applied to the second flip-flop circuit 14-2. At this time, for the flip-flop circuit in which the writing of the data “4” is not latched, the latched state is not changed, and for the flip-flop circuit in which the writing of the data “4” is latched, If the data “4” has been sufficiently written, the latch state is changed to the latch state for writing the data “3”, and conversely, if the data “4” has not been sufficiently written, the latch state remains unchanged. Becomes

After that, in order not to change the state of the flip-flop circuit 14-1 which is going to write data "1", data "2" or "3", the voltage of each bit line is changed to "H", The voltage of the selected bit line BLa and the reference bit line BL are set to “H” and “L”.
The voltage of b is connected to the flip-flop circuit 14-1.
At this time, the latch state is not changed for the flip-flop circuit in which the writing of the data “4” is not latched, and the flip-flop circuit in which the writing of the data “4” is latched is not changed. If "4" has been sufficiently written, the latch state is data "1".
If the data “4” is not sufficiently written, on the contrary, the latch state remains unchanged.

After these operations, when all the latch states of the flip-flop circuits 14-1 and 14-2 are in the latch state of the data "1" write, the write end detection signal charged and floated. PENDA holds the "H" level, whereby the write operation can be completed.

On the other hand, the flip-flop circuits 14-1, 14
If at least one of -2 is in the latched state for writing data "2" to "4", the write end detection signal PE
NDA becomes "L" level and the write operation is started again.

Next, a second embodiment of the present invention will be described.

FIG. 14 is a configuration diagram showing a configuration of a multi-value storage NAND type EEPROM according to the second embodiment of the present invention.

Multi-valued storage NA according to the second embodiment
The ND type EEPROM has a typical configuration, which is different from the open bit type configuration of the first embodiment.

As shown in FIG. 14, the multi-value storage NAND type EEPROM according to the second embodiment is a row system circuit provided for a memory cell array 1 configured by arranging memory cells in a matrix. 2 and column system circuit 3
And

The row system circuit 2 receives an address signal output from the address buffer 4, selects a row of the memory cell array based on the received address signal, and a memory based on the output of the row decoder. A word line drive circuit for driving the word lines of the cell array is included. In the case of NAND type EEPROM, word lines refer to select gates and control gates. The word line drive circuit can be read as a control gate / select gate drive circuit.

The column system circuit 3 receives the address signal output from the address buffer 4, selects a column of the memory cell array based on the received address signal, and outputs the column decoder based on the output. ,
A column selection line driving circuit that drives a column selection line that selects a column of the memory cell array is included.

Further, the column system circuit 3 includes a data circuit (bit line control circuit) for temporarily holding the write data to the memory cell and reading the data of the memory cell.

The bit line control circuit uses the data input / output line IO.
Through the data input / output circuit (data input / output buffer)
5 is connected. The bit line control circuit is connected to the memory cells of the memory cell array 1 via the bit line BL.

When writing data, the bit line control circuit receives the write data from the data input / output buffer 5 and inputs the received write data to the memory cell. When reading data, the bit line control circuit receives the read data from the memory cell and outputs the received read data to the data input / output buffer 5.

The data input / output buffer 5 performs data input / output control and guides write data input from the outside of the EEPROM to the memory core, or reads read data from the memory core to the outside of the EEPROM. To output.

The write end detection circuit 18 detects whether or not the data write is completed based on the output of the bit line control circuit.

FIG. 15 is a configuration diagram showing the configurations of the memory cell array and column related circuit shown in FIG.

As shown in FIG. 15, the memory cell array 1
, The memory cells MC are arranged in a matrix.

The column system circuit 3 includes m data circuits (bit line control circuits) 6. The bit line control circuit 6 is connected to one bit line BL.

As shown in FIG. 15, the circuit of the cell MC is
It is similar to the circuit shown in FIG. In addition, a group of memory cell transistors M sharing the control gate CG forms a unit called "page", data writing and reading are simultaneously performed in "page", and four control gates CG1 to CG1 to Similarly, a group of memory cell transistors M connected to CG4 forms a unit called a "block", and further, a "page" and a "block" are selected by a control gate / select gate driving circuit. . The structure of the memory cell transistor M is similar to that shown in FIG. Also, one memory cell transistor M
Also, the setting of the threshold level when storing four-valued data may be as shown in FIG.

FIG. 16 is a circuit diagram of the bit line control circuit shown in FIG.

Incidentally, FIG. 14 shows the bit line control circuit 6
In the example shown in FIG.
6 illustrates a configuration in which the bit line control circuit 6 is connected to four bit lines, and the description thereof will be given.

As shown in FIG. 16, the bit line control circuit 6
Includes two flip-flop circuits 14 ^* -1, 14 ^* -2. Flip-flop circuit 14 ^* -1, 14 ^* -2
Are connected to four bit lines. Then, during operation, one bit line is selected from the four bit lines, and the selected bit line is flip-flop circuit 14 ^* -.
Connected to 1, 14 ^* -2. Flip-flop circuit 14
^* -1,14 ^* -2 together, when reading the data,
It functions as a sense amplifier that amplifies and latches read data, and functions as a data latch that latches write data when writing data. In other words, the flip-flop circuit 14 ^* -1,14 ^* -2, a sense amplifier and the data latch circuit.

Further, the flip-flop circuit 14 ^* -1, 1
4 ^* -2 has a configuration of a forced inversion type sense amplifier, which is different from that of the first embodiment. The forced inversion type sense amplifier is described in the following document, for example.

KDSuh et al., 1995 ISSCC Digest of Te
chnical Papers, pp.128-129. Furthermore, the flip-flop circuits 14 ^* -1, 14 ^* -2 are
It is connected to a write / verify circuit 16 ^* , which also serves as a data write circuit and a verify circuit. The write / verify circuit 16 ^* , when writing data,
Depending on the combination of the latch data flip-flop circuit 14 ^* -1,14 ^* -2 are latched, one of the write control voltage V1, V2, V1, V2, and outputs to the bit line. Further, when reading data or reading data for verification, the voltage of the bit line is controlled according to the combination of the latched data latched by the flip-flop circuits 14 ^* -1, 14 ^* -2.

Next, the operation of the bit line control circuit shown in FIG. 16 will be described.

FIG. 17 is an operation waveform diagram showing normal read operation and verify operation. In the operation waveform diagram of FIG. 17, a normal read operation is shown by a solid line, and a verify operation is shown by a broken line only at a portion different from the normal read operation.

FIG. 18 is an operation waveform diagram showing a write operation.

First, a normal read operation will be described.

As shown in FIG. 17, first, the selected bit line BL is precharged, and then made floating. At the same time, the node D1A of the flip-flop circuit 14 ^* -1 and the node D2A of the flip-flop circuit 14 ^* -2 are reset to "L". The potentials of the two select gates SG1 and SG2 of the selected row and the potential of the non-selected control gate CG are set to 4V, respectively. The potentials of the selected control gates CG are 2V, 1V,
It is set to 0V.

When the selected memory cell transistor M stores the data "4", the memory cell transistor M does not conduct when the potential of the selected control gate CG is 2V, and the current flows through the bit line. It does not flow and the voltage of the bit line remains "H". On the other hand, the selected memory cell transistor M has data "1", "2", "3".
When the potential of the selected control gate CG is 2V, the control gate CG becomes conductive, a current flows through the bit line, and the voltage of the bit line becomes 0V. After that, the voltage of the selected bit line is changed to two flip-flop circuits 14 ^* -1, 14 ^{* .}
Input to -2. When the data is "4", the nodes D1A and D2A are both "H", and when the data is other data, the nodes D1A and D2A are both "L".

Then, the bit line is precharged again. Then, the potential of the selected control gate is set to 1V. If the selected memory transistor M has data “1”,
Alternatively, when the data “2” is stored, the potential of the bit line is 0V, and when the selected memory transistor M stores the data “3” or the data “4”, the potential of the bit line is 0V. Remains "H". Then, the voltage of the selected bit line is input to the flip-flop circuit 14 ^* -1. When the data is "4", both the nodes D1A and D2A remain "H". When the data is "3", when the nodes D1A and D2A are "H, L", the data "2", or the data "1", respectively. , Nodes D1A and D2A both remain "L".

Then, the bit line is precharged again. Then, the selected control gate is set to 0V. Data "2" or data "3" or data "4"
, The bit line remains "H" and data "1"
, The bit line becomes "L". When the data stored in the memory cell transistor M is "3", that is, the nodes D1A and D2A are "H",
If it is L ”, the voltage of the bit line is corrected to“ L ”by transferring the voltage V2 = 0V.
The voltage of the selected bit line is applied to the flip-flop circuit 1
Enter in 4 ^* -2. When data is "4", node D
When 1A and D2A are both "H" and when the data is "3", the nodes D1A and D2A are respectively "H and L", and when they are "2", the nodes D1A and D2 are
A is “L, H” respectively, and when the data is “1”,
Both the nodes D1A and D2A remain "L".

In this way, as in the case of the first embodiment shown in FIG. 12, the four types of threshold levels read from the memory cell transistor M are set to the flip-flop circuit 14 ^* -1, It is possible to make a one-to-one correspondence with each of the four types of latch data of 14 ^* -2.

As shown in FIG. 18, the write operation is the same as the write operation of the first embodiment described with reference to FIGS. 9 to 11, and therefore its description is omitted. Next, the verify read operation will be described.

The selected bit line BL is charged in the same manner as at the time of reading, and then made floating. The potentials of the two select gates SG1 and SG2 of the selected row and the potential of the non-selected control gate CG are set to 4V. The potentials of the selected control gates CG are 2.5V in sequence,
It is set to 1.5V and 0.5V. These potentials correspond to data "4" verify, data "3" verify, and data "2" verify, respectively.

First, the data "4" is verified by setting the potential of the selected control gate CG to 2.5V.
When the read threshold value of the memory cell transistor M corresponds to the data "4", no current flows in the bit line, and the voltage of the bit line remains precharged. Further, when the read threshold value of the memory cell transistor M is data “1”, data “2”, or data “3”, a current flows through the bit line, so that the voltage of the bit line is 0V. become.

In order not to change the latch state of the flip-flop circuit which is going to write data "1", data "2" or data "3", the voltage of the bit line is set to "L" and then selected. the voltage of the bit line, and inputs to the flip-flop circuit 14 ^* -1,14 ^* -2. At this time, for the flip-flop circuit in which the writing of the data “4” is not latched, the latched state is not changed, and for the flip-flop circuit in which the writing of the data “4” is latched, If the data “4” is sufficiently written, the latch state is changed to the latch state for writing the data “1”, and conversely, if the data “4” is not sufficiently written, the latch state remains unchanged. Becomes

Then, the potential of the selected control gate CG is set to 1.5 V to verify the data "3". When the read threshold value of the memory cell transistor M corresponds to data "1" or data "2", a current flows through the bit line, and the voltage of the bit line becomes 0V. When the read threshold value of the memory cell transistor M corresponds to data "3" or data "4", no current flows in the bit line and the voltage of the bit line is precharged. Remain at the level.

In order not to change the latched state of the flip-flop circuit which is going to write data "1", data "2" or data "4", each bit line voltage is set to "L" and then selected. The bit line voltage is input to the flip-flop circuit 14 ^* -1. At this time, for the flip-flop circuit in which the writing of the data “3” is not latched, if the latched state is not changed and the data “3” is sufficiently written,
The latched state is changed to the latched state in which the data “1” is written. On the contrary, if the data “3” is not sufficiently written, the latched state remains.

Finally, the potential of the selected control gate CG is set to 0.5 V to verify the data "2".
When the read threshold value state of the memory cell transistor M corresponds to data “2”, data “3”, or data “4”, no current flows in the bit line, so that the bit line The voltage remains at the precharge level. In addition, the read memory cell transistor M
When the state of the threshold value of 1 corresponds to the data “1”, no current flows in the bit line and the voltage of the bit line is 0V.
become.

In order to not change the latched state of the flip-flop circuit 14 ^* -2 in which the writing of the data "1", the data "3", or the data "4" is latched, the voltage of each bit line is changed to "L". Then, the voltage of the selected bit line is connected to the flip-flop circuit 14 ^* -2. At this time, for the flip-flop circuit in which the writing of the data “2” is not latched, the latch state is not changed, and for the flip-flop circuit in which the writing of the data “2” is latched, Data “2”
Is written sufficiently, the latched state is changed to a latched state in which data "1" is written, and conversely, when data "2" is not sufficiently written, the latched state remains.

[0109] After these operations, all the latched state of the flip-flop circuit 14 ^* -1,14 ^* -2, data "1" when it is latched in the write, is charged,
Floating write end detection signal PEND
Holds the "H" level, whereby the write operation can be completed.

On the other hand, the flip-flop circuit 14 ^* -1, 1
If at least one of 4 ^* -2 has a latched state for writing the data "2" to "4", the write end detection signal PEND becomes "L" and the write operation starts again. .

In the four-value storage NAND type EEPROM according to the first and second embodiments, the verify circuit and the write circuit are n write circuits latched by the flip-flop (data latch / sense amplifier) circuit. Controlled by data. Thus, when the number of multivalued data is 2 ^m (m is a natural number of 2 or more) = n value, the number of circuits of the data latch / sense amplifier can be m. Specifically, in the case of four values, only two flip-flop circuits as a data latch and a sense amplifier are used.
A bit line control circuit having a verify function can be constructed. Therefore, the circuit scale of the column system circuit, particularly the number of sense amplifiers / data latch circuits and verify circuits can be reduced, and a nonvolatile semiconductor memory device suitable for high integration can be obtained.

Further, the flip-flop circuit, when the result of the verify read operation is good, changes the latched write data to the write data when the data of the memory cell transistor M is not changed, specifically, four-valued data. Each time a "sufficient write" result is obtained, the four-valued data of the flip-flop circuit is sequentially updated so as to become the write data "1" in accordance with each threshold level.
As a result, the verify circuit and the write circuit are controlled in the same manner as when the data "1" is written.

Further, during the verify read operation, when the number of multi-valued data is set to 2 ^m , in a device in which the number of flip-flop circuits is set to m, the once updated write data may be changed. However, in the verify circuit and the write circuit described in the above embodiment, another data is transferred to the flip-flop circuit in accordance with the write data latched in the flip-flop circuit so that the updated write data is not changed. I am trying to enter.

As described above, the n-valued data latched by the flip-flop circuit is sequentially updated to the write data "1" each time the "write sufficient" result is obtained, and the write data once updated is not changed. Can be As a result, all the n-valued data latched by the flip-flop circuit is updated to the write data “1”, so that it is possible to automatically know that the writing is completed.

Also during the read operation, the read data once detected by the flip-flop circuit may be changed. In the above-described embodiment, the verify circuit and the write circuit use the flip-flop circuit for a part of the read data that has already been latched, and use the flip-flop circuit for data that does not change the read data once detected. I am trying to enter.
This configuration is also the case where the number of multi-valued data is 2 ^m ,
One configuration is given in which the number of flip-flop circuits can be m.

As described above, the present invention is applied to the four-value storage NAND type E.
Although the EPROM is taken as an example and described by the first and second embodiments, the present invention is a four-value storage NAND type EEPR.
It is not limited to OM. For example, the number of data to be stored in one memory cell transistor may be three values or more, and is not fixed to four values.

The memory cells integrated in the memory cell array 1 are not limited to NAND type cells.
The present invention can also be implemented in cells described below.

FIG. 19 is a diagram showing a memory cell array in which NOR type cells are integrated. The NOR type cell shown in FIG. 19 is connected to the bit line BL via a select gate.

FIG. 20 shows a memory cell array in which other NOR type cells are integrated. NO shown in FIG.
The R-type cell is directly connected to the bit line BL.

FIG. 21 is a diagram showing a memory cell array in which ground array type cells are integrated. As shown in FIG. 21, the ground array type cell has bit lines BL and source lines VS arranged in parallel. The ground array type cell is one of NOR type memories.

FIG. 22 is a diagram showing a memory cell array in which other ground array type cells are integrated. The ground array type cell shown in FIG. 22 has an erase gate EG used when erasing data. Further, a part of the control gate CG is of a so-called split channel type in which the channel of the memory cell transistor is overlapped.

FIG. 23 is a diagram showing a memory cell array in which alternating ground array type cells are integrated. As shown in FIG. 23, the alternate ground array type cell coincides with the ground array type cell in that the bit line BL and the source line VS are arranged in parallel, but the bit line BL and the source line V are different from each other.
The difference is that S and S can be switched alternately.

FIG. 24 is a diagram showing a memory cell array in which other alternate ground array type cells are integrated. FIG.
The alternating ground array type cell shown in FIG. 4 has the same structure as the ground array type cell shown in FIG.

FIG. 25 is a diagram showing a memory cell array in which DINOR (DIvided NOR) type cells are integrated.
As shown in FIG. 25, the DINOR type cell is configured by connecting, for example, four memory cell transistors in parallel between the bit line BL and the source line VS via a bit line side selection transistor.

FIG. 26 is a diagram showing a memory cell array in which AND type cells are integrated. As shown in FIG. 39,
The AND-type cell is configured by connecting, for example, four memory cell transistors in parallel between the bit line BL and the source line VS via the bit line side selection transistor and the source line side selection transistor.

[0126]

As described above, according to the present invention, the circuit scale of the column system circuit is reduced particularly by reducing the number of sense amplifiers / data latch circuits.
A non-volatile semiconductor memory device suitable for high integration can be provided.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a configuration of a multi-value storage NAND type EEPROM according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing a configuration of a memory cell array and a column system circuit shown in FIG.

3 is a cross-sectional view of the memory cell transistor shown in FIG.

FIG. 4 is a diagram showing a threshold distribution of memory cell transistors in multi-value storage.

5 is a circuit diagram of the bit line control circuit shown in FIG.

FIG. 6 is an operation waveform diagram showing normal read operation and verify operation.

FIG. 7 is an operation waveform diagram showing normal read operation and verify operation.

FIG. 8 is an operation waveform diagram showing a normal read operation and a verify operation.

FIG. 9 is an operation waveform diagram showing a write operation.

FIG. 10 is an operation waveform diagram showing a write operation.

FIG. 11 is an operation waveform diagram showing a write operation.

FIG. 12 is a diagram showing a correspondence relationship between a threshold level of a memory cell transistor and latch data.

FIG. 13 is a diagram showing a correspondence relationship between latch data and threshold values of memory cell transistors.

FIG. 14 is a configuration diagram showing a configuration of a multi-value storage NAND type EEPROM according to a second embodiment of the present invention.

15 is a configuration diagram showing a configuration of a memory cell array and a column system circuit shown in FIG.

16 is a circuit diagram of the bit line control circuit shown in FIG.

FIG. 17 is an operation waveform diagram showing normal read operation and verify operation.

FIG. 18 is an operation waveform diagram showing a write operation.

FIG. 19 is a diagram showing a memory cell array in which NOR type cells are integrated.

FIG. 20 is a diagram showing a memory cell array in which other NOR type cells are integrated.

FIG. 21 is a diagram showing a memory cell array in which ground array type cells are integrated.

FIG. 22 is a diagram showing a memory cell array in which other ground array type cells are integrated.

FIG. 23 is a diagram showing a memory cell array in which alternating ground array type cells are integrated.

FIG. 24 is a diagram showing a memory cell array in which other alternate ground array type cells are integrated.

FIG. 25 is a diagram showing a memory cell array in which DINOR type cells are integrated.

FIG. 26 is a diagram showing a memory cell array in which AND cells are integrated.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2 ... Row related circuit, 3 ... Column related circuit, 4 ... Address buffer, 5 ... Data input / output circuit 6 ... Data circuit, 7 ... Transfer gate circuit, 10 ... Bit line control circuit, 14 ... Flip-flop Circuit, 16 ... Write and verify circuit, MC ... Memory cell, M ... Memory cell transistor, S ... Select transistor, SG ... Select gate, CG ... Control gate, BL ... Bit line.

Claims (5)

[Claims] 1. A memory cell array configured by arranging memory cells for storing multivalued data in a matrix, and a latch function for latching write data to the memory cells when writing data to the memory cells. A sense latch function of sensing and latching read data from the memory cell when reading data from the memory cell, and the latch function and sense latch when the number of the multi-valued data is n The number of functions is m
(M is 2 ^(m-1) <n ≤ 2 ^m (m is an integer of 2 or more)), and the bit line control circuit and the memory cell are electrically connected to each other. When connecting and writing data to the memory cell,
When guiding the write data to the memory cell from the latch function and reading the data from the memory cell,
A bit line that guides the read data from the memory cell to the sense / latch function, and a write corresponding to the multi-valued data according to the write data latched by the latch function when writing data to the memory cell A write circuit for selecting a control voltage and applying a selected write control voltage to a bit line; and a verify circuit for verifying the written data after writing data in the memory cell, the verify circuit and the verify circuit A nonvolatile semiconductor memory device, wherein a write circuit is configured to be controlled by n write data latched by the latch function. 2. The latch function, when the result of the verify read operation is good, changes the data of the memory cell when the write data latched by the latch function is written to the memory cell. The non-volatile semiconductor memory device according to claim 1, wherein the data is updated to the data when there is no such data. 3. The input data to the latch function by the verify circuit and the write circuit according to the latched write data so that the write data once updated is not changed during the verify read operation. 1. The method according to claim 1, wherein
The nonvolatile semiconductor memory device according to claim 2. 4. A memory cell array composed of a plurality of memories having a charge storage section capable of storing N-value (N ≧ 3) data, a plurality of bit lines, a plurality of word lines, and a plurality of program control circuits. , A plurality of data circuits, the program control circuit 1) selects the memory cell, 2) applies a write voltage to the selected memory cell, and the data circuit sets M to 2 ^M-1 <N When it is a natural number satisfying ≦ 2 ^M , it is composed of M latch circuits, and 1) a first and a second for controlling a write control voltage applied to the respective corresponding memory cells selected by the program control circuit. ..., holding write control data of the Nth logic level, 2) applying the write control voltage to the corresponding memory cells, and 3) writing of a logic level other than the first logic level. Selectively detect only the write state of the memory cell corresponding to the data circuit holding the embedded control data, and 4) the write control of the data circuit corresponding to the memory cell that has reached a predetermined write state. 5) changing the logic level of data to the first logic level, 5) holding the logic level of the write control data of the data circuit corresponding to a memory cell that has not reached a predetermined write state, 6) the A nonvolatile semiconductor memory device for holding a logic level of write control data of the data circuit, which holds write control data of a first logic level, at the first logic level, comprising: A nonvolatile semiconductor memory device characterized in that the write data is updated according to a combination of states. 5. The non-volatile semiconductor memory device according to claim 1, wherein the verify circuit for updating the write data generates a write control voltage.