JPH09251785A - Non-volatile semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory device suitable for high integration by minimizing a circuit scale of a column system circuit. SOLUTION: This device is provided with flip-flop circuits FF1, FF2 of which the number is set to (m), a verifying circuit verifying written data after data is written in a memory cell, and a transistor Qn 5 for detecting en block finish of writing judging whether writing is performed again or not during verifying, when the number of data of multi-values by which writing data for a memory cell is latched and writing data from a memory cell is sense-latched is assumed to 2<m> =n (m is natural number of 2 or more). And the transistor Qn 5 for detecting en bloc is controlled by updated writing data in accordance with the writing result of verifying of the flip-flop circuit FF1 during verifying.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable non-volatile semiconductor memory device (EEPROM), and more particularly to a multi-value memory EEPROM for storing information of more than 1 bit in one memory cell.

[0002]

2. Description of the Related Art As one of the methods for increasing the capacity of an EEPROM, a multi-value storage EEPROM is known in which one memory cell stores n (n ≧ 3) value information. For example, in the four-value storage type, each cell has one of four kinds of threshold voltages, which is (0, 0),
It corresponds to 2-bit information represented by (0,1), (1,0), and (1,1).

In order to read the data of the memory cell storing the n value, the data read from the cell is compared with (n-1) reference voltages. Therefore, conventionally, (n-1) sense amplifiers have been required (for example, Japanese Patent Laid-Open No. 61-11).
7796).

In the 4-value storage type EEPROM, the storage density of the memory cells is doubled and the area occupied by the memory cells is halved as compared with the binary storage type EEPROM, whereas the sense amplifier is The area occupied is tripled, and the effect of high density is reduced. In particular, an E type that has a sense amplifier for each bit line to perform page read
In the EPROM, an increase in the number of sense amplifiers hinders an increase in capacity.

On the other hand, in Japanese Unexamined Patent Publication No. 62-54896, the number of sense amplifiers is reduced by controlling the reference voltage of other sense amplifiers by the output of the sense amplifier which discriminates the cell data. A read-only memory characterized by is disclosed.

On the other hand, in a multi-value storage EEPROM which stores n (n ≧ 3) kinds of threshold voltages in memory cells, when the stored data is written, the respective threshold voltages are
It needs to be distributed in a narrower range. For this reason, writing is done in small increments, and it is checked whether each memory cell has been written to the target threshold range between writing, and if there is a cell with insufficient writing, only that cell is written. The additional write is performed, and the bit-by-bit verify that controls so that the optimum write is performed for each memory cell is effective. The verification for each bit is disclosed in Japanese Patent Laid-Open No. 3-295098.

Further, bit-by-bit verification for a multi-value storage EEPROM is disclosed in Japanese Patent Laid-Open No. 7-93979. However, the device disclosed in Japanese Patent Laid-Open No. 7-93979 requires (n-1) sense amplifiers and (verify) circuits. Therefore,
A memory cell can store a large amount of data in a chip having the same area by storing a larger amount of data, but a circuit for controlling read / write of data becomes large in scale and highly integrated. There was a difficulty in converting.

[0008]

As described above, in the conventional multi-value storage EEPROM having a verify function, when the number of multi-valued data is "n≥3", (n-1) verifications are performed. I needed a circuit. Therefore, the sense amplifier / data latch circuit also depends on the verify circuit.
(N-1) pieces are required.

Due to the above circumstances, the circuit scale of the circuit connected to the bit line, that is, the column system circuit, particularly the number of sense amplifier circuits, data latch circuits, and verify circuits becomes enormous, resulting in high integration. Has become the neck of.

The present invention has been made in view of the above circumstances, and an object thereof is to reduce the circuit scale of a column system circuit, in particular, by reducing the number of sense amplifier circuits, data latch circuits, and verify circuits. A non-volatile semiconductor memory device suitable for high integration is provided.

[0011]

In order to achieve the above object, in a nonvolatile semiconductor memory device according to the present invention, a memory cell array in which memory cells for storing multi-valued data are arranged in a matrix. When writing data to the memory cell, the write data to the memory cell is latched, and when the data is read from the memory cell, the read data from the memory cell is sensed.
When the number of multi-valued data to be latched is 2 ^m (m is a natural number of 2 or more) = n value, a bit line control circuit including a data latch / sense amplifier circuit whose number is set to m When the data latch / sense amplifier circuit and the memory cell are connected to each other and the data is written to the memory cell, the write data is guided from the data latch / sense amplifier circuit to the memory cell, and the data is written from the memory cell. According to the write data latched in the data latch / sense amplifier circuit when writing data to the memory cell and the bit line that leads the read data from the memory cell to the data latch / sense amplifier circuit. , Select a write control voltage according to the multi-valued data, and set the selected write control voltage to the bit line After writing the write circuit, the data to the memory cell to provide, characterized by comprising a verification circuit for the written data is confirmed whether or not it is in the storage state of the desired data.

A memory cell array in which memory cells for storing electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, and bit lines connected to the memory cells are connected to the memory cells. Threshold value detecting means for charging via the bit line and outputting the multi-valued data of the memory cell as a multi-valued level potential to the bit line, and the multi-valued bit line potential charged by the threshold value detecting means. , A first, second, ..., Mth data circuit for holding data to be written in the memory cell, and whether or not the state after the write operation of the memory cell is a desired data storage state. Write verifying means using the threshold value detecting means for confirming the above, and a memo of insufficient writing from the contents of the data circuit and the state after the write operation of the memory cell. And a data circuit content batch updating unit that collectively updates the contents of the data circuit so that the data is rewritten only to the cell, and the data updating circuit refers to the contents of one data circuit. Is characterized by.

A memory cell array in which memory cells that store electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, and bit lines connected to the memory cells are connected to the memory cells. Refer to the threshold value detecting means for charging via the bit line and the multi-valued data of the memory cell as the potential of the multi-valued level to the bit line, and the bit line potential of the multi-valued level charged by the threshold value detecting means. A sense amplifier that senses a bit line potential by comparing voltages, first, second, ..., Mth data circuits that retain data to be written in a memory cell, and a state after the write operation of the memory cell are desired. Write verify means for using the threshold value detecting means for confirming whether or not the data storage state of the data circuit is stored, and the contents of the data circuit and the writing of the memory cell. A data circuit content batch updating unit including a data updating circuit that collectively updates the contents of the data circuit so as to rewrite only the memory cells in which writing is insufficient from the state after the operation, and the data updating circuit includes With reference to the content of one data circuit, the data circuit content batch updating means outputs a state after a write operation of a memory cell so that the bit line potential is sensed and stored as rewrite data, and The reference potential is modified according to the contents of the data circuit, the data storage state of the data circuit is held until the bit line potential is modified, and the data circuit operates as a sense amplifier while holding the modified bit line potential. , The contents of the data circuit are collectively updated, and the write operation and the contents of the data circuit are collectively updated based on the contents of the data circuit. Wherein the electrical to perform data writing by performing repeatedly until a predetermined write state.

The memory cell is a NAND type cell in which a plurality of memory cell transistors are connected in series, and one end of the NAND type cell is connected to a bit line through a first select gate, and the NAND cell is connected. The other end of the type cell is connected to the source line via a second select gate, and the threshold value detecting means supplies the source line voltage to the NAND line.
To transfer to the bit line through the type cell to charge the bit line, and the non-selected control gate voltage and the first and second selection gate voltages are determined by the bit line voltage at the threshold value of the selected memory cell. In this way, the voltage transfer capability of the non-selected memory cell and the first and second selection transistors is controlled sufficiently.

A memory cell array in which memory cells for storing electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, and first, second, ... , M-th (m is 2 ^(m-1) <n ≤
A data circuit for a natural number) that satisfies 2 ^m, characterized in that the state after the write operation of the memory cell and a write verify means for checking whether or not it is the storage state of the desired data.

A memory cell array in which memory cells for storing electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, and first, second, ... , M-th (m is 2 ^(m-1) <n ≤
A data circuit having a natural number satisfying 2 ^m, and a write verify unit for confirming whether or not the state after the write operation of the memory cell is a desired data storage state,
Data circuit contents batch updating means for updating the contents of the data circuit so that the contents of the data circuit and the state after the writing operation of the memory cell are rewritten only to the insufficiently written memory cells. And the data update circuit refers to the contents of one data circuit.

A memory cell array in which memory cells storing electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, and a threshold detecting means for detecting the threshold voltage of the memory cells. , Holding the data to be written in the memory cell, the first, second, ..., Mth (m is 2 ^(m-1) <
(a natural number satisfying n ≦ 2 ^m ) and write verify means for confirming whether or not the state of the memory cell after the write operation is a desired data storage state, and the threshold detection Is in the “1” state, or in the “2” or “3” or ... “n” state by applying the first threshold voltage to the gate electrode of the memory cell. Whether or not the memory cell is in the “1” or “2” state, or “3”, ..., By applying the second threshold detection voltage to the gate electrode of the memory cell, It is characterized in that the first, second, ..., (n-1) th threshold detection voltage is applied to the gate electrode of the memory cell so as to determine whether it is in the "n" state.

A memory cell array in which memory cells for storing electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, a data circuit for holding data to be written in the memory cells, and the memory cells. And a write verify unit that confirms whether or not the state after the write operation is the storage state of desired data, and in the write operation for writing in n kinds of write states,
First at almost the same time with respect to the memory cells to be written in k (k is a natural number satisfying 2 ≦ k ≦ n) kinds of write states.
Writing is performed, and before or after the first writing operation, writing is performed in a memory cell in which writing is performed in nk kinds of writing states.

An electrically rewritable n value (n is 3 or more) such that the "1" state is the erased state and the "2" state, the "3" state, ..., The "n" state is the written state. Memory cell array for storing memory cells), a data circuit for holding data to be written in the memory cells, and a state after the write operation of the memory cells becomes a desired data storage state. A write verifying means for confirming whether or not there is a write verifying means, and at the time of writing, a first write operation is performed almost at the same time in a memory cell to be written in “3” state, ... And writing to the “2” state before or after the second writing operation.

In the write state of n values, the "1" state,
It is characterized in that the write threshold voltage increases in the order of the “2” state, the “3”, ...

"1" state, "2" state, "3" state,
..., a memory cell array in which memory cells that store electrically rewritable n values are arranged in a matrix such that the "n" state (n is a natural number of 3 or more) is stored.
A signal line for exchanging data with the memory cell and a read data holding circuit for holding information read from the memory cell are provided, and when the threshold value of the memory cell is almost the same as the "i" state or more than "i" state. There is an i-th read operation for checking whether or not the read data is in the “i” state, the read data is held in the data holding circuit, and thereafter, the threshold value of the memory cell is almost the same as that in the “j” state. j "
At the j-th read operation for checking whether it is equal to or more than the state or smaller than the “j” state, the potential of the signal line output from the data of the memory cell is changed with reference to the data held in the data holding circuit. After that, the potential of the signal line is sensed.

A memory cell array in which memory cells storing electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, a signal line for exchanging data with the memory cells, and a memory cell. A signal that outputs the write data of the memory cell, including a data circuit that holds the write data, and a write verify unit that confirms whether or not the state after the write operation of the memory cell is a storage state of desired data By referring to the potential of the line twice or more, the contents of the data circuit are updated so that the contents of the data circuit and the state after the writing operation of the memory cell are rewritten only to the insufficiently written memory cells. To do.

A memory cell array in which memory cells storing electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, and a threshold detecting means for detecting the threshold voltage of the memory cells. A data circuit for holding data to be written in the memory cell, and write verify means for confirming whether or not the state of the memory cell after the write operation is a desired data storage state, The detection is performed by applying a first threshold detection voltage to the gate electrode of the memory cell so that the memory cell is in the "1" state, or the "2" or "3" or ..., "n" state. Whether or not the memory cell is in the "1" or "2" state, or "3" by applying the second threshold voltage to the gate electrode of the memory cell. , To determine whether the "n" state, first the gate electrode of the memory cell, second, ...,
By applying the (n-1) th threshold detection voltage and referring to the potential of the signal line that outputs the write data of the memory cell more than once, the contents of the data circuit and the memory cell write operation after the write operation are performed. It is characterized in that the contents of the data circuit are updated so that rewriting is performed only from a state where the memory cells in which writing is insufficient are performed.

N is 4 or more.

A memory cell array in which memory cells for storing electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, and m data circuits for holding data to be written in the memory cells, Write verifying means for confirming whether or not the state of the memory cell after the write operation is a desired data storage state, and the content of the data circuit and the state of the memory cell where the write operation is insufficient from the state after the write operation of the memory cell And a data circuit content batch updating unit configured to update the content of the data circuit so as to rewrite only the cell, and the data updating circuit refers to the content of one data circuit. Characterize.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

<First Embodiment> FIG. 1 shows a first embodiment of the present invention.
3 is a configuration diagram showing a configuration of a multi-value storage NAND EEPROM according to the embodiment of FIG.

As shown in FIG. 1, the multi-value storage NAND type EEPROM according to the first embodiment has a structure called an open bit type. The open bit type multi-value storage NAND type EEPROM is a memory cell array 1A configured by arranging memory cells in a matrix,
Row related circuits 2A, 2B provided for each 1B
And a column system circuit 3 ^** commonly used in each of the memory cell arrays 1A and 1B.

The row related circuits 2A and 2B receive the address signal output from the address input circuit (address buffer) 4, select a row of the memory cell array based on the received address signal, and a row decoder. A word line drive circuit for driving the word line of the memory cell array based on the output of the. NAND type EEPR
In the case of OM, the word line is a select gate SG (SGA, S
GB) and control gate CG (CGA, CGB). The word line drive circuit can be read as a control gate / select gate drive circuit.

Further, the column system circuit 3 ^** commonly used in each of the memory cell arrays 1A and 1B receives the address signal output from the address buffer 4 and, based on the received address signal, the column of the memory cell array. And a column select line drive circuit that drives a column select line that selects a column of the memory cell array based on the output of the column decoder.

Further, the column system circuit 3 ^** includes a data circuit (bit line control circuit) for temporarily holding the write data to the memory cell and reading the data of the memory cell. There is.

The bit line control circuit uses the data input / output line IO.
Through the data input / output circuit (data input / output buffer)
5 is connected. In addition, the bit line control circuit causes the memory cell of the memory cell array 1A via the bit line BLa and the memory cell array 1B via the bit line BLb.
Of memory cells.

When writing data, the bit line control circuit receives the write data from the data input / output buffer 5 and inputs the received write data to the memory cell. When reading data, the bit line control circuit receives the read data from the memory cell and outputs the received read data to the data input / output buffer 5.

The data input / output buffer 5 performs data input / output control and guides write data input from the outside of the EEPROM to the memory core, or reads read data from the memory core to the outside of the EEPROM. To output.

The write end detection circuit 18 detects whether or not the data write is completed based on the output of the bit line control circuit.

FIG. 2 is a configuration diagram showing the configurations of the memory cell array and column system circuit shown in FIG. FIG.
2A and 2B are diagrams showing a case where data is read from the memory cell shown in FIG. 2, wherein FIG. 7A is a diagram showing a voltage input state, and FIG. 4B is a diagram showing a voltage input waveform and an output waveform appearing on a bit line. Is.

As shown in FIG. 2, the memory cell array 1
Memory cells MC are arranged in a matrix in each of A and 1B.

The column circuit 3 ^** includes m data circuits (bit line control circuits) 6 ^** . The bit line control circuit 6 ^** includes one bit line BLa and one bit line BLa.
It is connected to the book bit line BLb.

Further, as shown in FIG.
In the EEPROM, one cell MC has a plurality of memory cell transistors M1 to M4 connected in series.
Are included to form a NAND cell MC. One end of the cell MC is connected to the bit line BL via the selection transistor S1, and the other end is connected to the source line VS via the selection transistor S2. The group of memory cell transistors M sharing the control gate CG form a unit called a "page". Data writing and reading are performed simultaneously in "pages". Also,
A group of memory cell transistors M connected to the four control gates CG1 to CG4 form a unit called a “block”. The "page" and the "block" are selected by the control gate / select gate driving circuit.

The memory cell transistor M stores multivalued data according to the threshold level. Then, in the device according to the present invention, the threshold level is set as shown in FIG.
And as shown in (b). Here, a memory cell transistor M2 having a control gate CG2
Is selected. As shown in FIG. 3A, a voltage is applied to each part and the bit line BL is made floating.
If the bit line BL is reset to 0V in advance, the bit line BL is charged by the common source line Vs through the NAND cell. Each select gate and control gate voltage is controlled so that the charged potential of the bit line BL is determined by the threshold value of the selected memory cell M2.

In this example, the selection gates SG1 and SG2, the control gates CG1 and CG3 to CG4 are set to 6V, the selected control gate CG2 is set to 2V, and the common source line Vs is set to 6V.
The voltage waveform of each part is shown in FIG. For example, if the potential of the bit line BL is 0V, the threshold value is 2V or more,
If the bit line potential is 3.5V, the threshold is -1.5V
It is as follows. However, in the following embodiments, in order to simplify the description, the expression "threshold value" takes into consideration the back bias.

After the electrons are emitted from the floating gate of the memory cell by the erase operation, the electrons are injected into the floating gate by the write operation according to the write data.

FIG. 4 is a diagram showing the relationship between the output voltage appearing on the bit line and the number of memory cells.

There are three states (data) in one memory cell.
0 "," 1 "," 2 "), for example, the bit line output voltage at the time of reading is 3.5 to 4.5V as shown in FIG.
When the threshold voltage is about -2.5V to -1.5V, the data is "0" (erased state) and the bit line output voltage is 1.5.
.About.2.5 V (a threshold value of about -0.5 V to 0.
5V) is data "1", bit line output voltage is 0 to 0.5
The state of V (a threshold value of about 1.5 V to 2.5 V) may be set as the data “2”.

FIG. 5 is a circuit diagram of the data circuit shown in FIG. The data circuit shown in FIG. 5 is configured by taking ternary storage as an example.

As shown in FIG. 5, n-channel MOS transistors Qn21, Qn22, Qn23 and p-channel M are provided.
A flip-flop FF1 composed of OS transistors Qp9, Qp10, Qp11 and an n-channel MO
S transistors Qn29, Qn30, Qn31 and p-channel MOS transistors Qp16, Qp17, Qp18
Write / read data is latched in the FF2 configured by. These also operate as sense amplifiers.

The flip-flop FF1 latches "whether" 0 "is written, or" 1 "is written or" 2 "is written" as write data information, and the memory cell holds "0" information. Is being carried out, or is it holding "1" information, or is it holding "2" information? "Is sensed and latched as read data information. The flip-flop FF2 latches "whether" 1 "is written or" 2 "is written" as write data information, and the memory cell holds "1" information or "2".
"Have information held?" Is sensed and latched as read data information.

The data input / output lines IOA and IOB and the flip-flop FF1 are connected to the n-channel MOS transistor Q.
It is connected via n28 and Qn27. The data input / output lines IOC, IOD and the flip-flop FF2 are connected via n-channel MOS transistors Qn35, Qn36. Data input / output lines IOA, IOB, IOC, I
The OD is also connected to the data input / output buffer 5 in FIG.

N-channel MOS transistor Qn27,
The gates of Qn28, Qn35 and Qn36 are connected to the output of the column address decoder composed of the NAND logic circuit G2 and the inverter I4. The n-channel MOS transistors Qn26 and Qn34 equalize the flip-flops FF1 and FF2 with the signals ECH1 and ECH2 being "H". The n-channel MOS transistors Qn24 and Qn32 are flip-flops F
The connection between F1 and FF2 and the MOS capacitor Qd1 is controlled. N-channel MOS transistors Qn25, Qn33
Controls the connection between the flip-flops FF1 and FF2 and the MOS capacitor Qd2.

P-channel MOS transistor Qp12,
The circuit composed of Qp13 has an activation signal VRFYBA.
Changes the gate voltage of the MOS capacitor Qd1 according to the data of the flip-flop FF1.
The circuit composed of p-channel MOS transistors Qp14 and Qp15 changes the gate voltage of the MOS capacitor Qd2 according to the data of the flip-flop FF1 by the activation signal VRFYBB. n-channel MO
The circuit composed of the S transistors Qn1 and Qn2 changes the gate voltage of the MOS capacitor Qd1 according to the data of the flip-flop FF2 by the activation signal VRFYBA1. n channel MOS transistor Q
The circuit composed of n3 and Qn4 has an activation signal VRFY.
The gate voltage of the MOS capacitor Qd2 is changed by BB1 according to the data of the flip-flop FF2.

The MOS capacitors Qd1 and Qd2 are composed of depletion type n-channel MOS transistors and are sufficiently smaller than the bit line capacitance. n channel M
The OS transistor Qn37 is set to M by the signal PREA.
The OS capacitor Qd1 is charged to the voltage VA. The n-channel MOS transistor Qn38 charges the MOS capacitor Qd2 to the voltage VB by the signal PREB. The n-channel MOS transistors Qn39 and Qn40 control the connection between the data circuit 3 and the bit lines BLa and BLb by the signals BLCA and BLCB, respectively. The circuit composed of the n-channel MOS transistors Qn37 and Qn38 also serves as the bit line voltage control circuit. p-channel MOS
A circuit composed of transistors Qp12 and Qp13, p
A circuit composed of channel MOS transistors Qp14 and Qp15, n-channel MOS transistors Qn1 and Qn
The circuit composed of 2 and the circuit composed of n-channel MOS transistors Qn3 and Qn4 are also bit line voltage control circuits.

Next, the EEPROM configured as described above
The operation of will be described with reference to an operation waveform diagram. Hereinafter, a case where the control gate CG2A is selected will be described.

<Read Operation> FIG. 6 is an operation waveform diagram showing a read operation.

As shown in FIG. 6, first, at time t1R, the selected control gate CG2A of the block selected by the control gate / select gate drive circuit is 2V, the non-selected control gates CG1A, CG3A, CG4A and the selection gate. S
G1A and SG2A are set to 6V. The source potential of the memory cell is set to 6V. When the memory cell is "0", the bit line BLa is 3.5 V or more, when it is "1", the bit line BLa is 1.5 V or more and 2.5 V or less, and when it is "2", it is 0. It becomes 5V or less. The dummy bit line BLb is V
Charged from B to 3V. When the voltage drop corresponding to the threshold value of the n-channel MOS transistor Qn40 becomes a problem, the signal BLCA may be boosted.

At time t2R, the nodes N1 and N2 of the capacitors Qd1 and Qd2 are set to 1.5V and then made floating. At time t3R, BLCA and BLCB become VCC (for example, 5V), and the potentials of the bit lines BLa and BLb become N.
1 is transferred to N2. After that, the signal BLCA,
BLCB becomes "L", and the bit line BLa and the MOS capacitor Qd1, the bit line BLb and the MOS capacitor Q.
d2 is separated. The signals SAN1 and SAP1 become "L" and "H", respectively, and the flip-flop FF1 is inactivated, and the signal ECH1 becomes "H" and is equalized. After that, the signals RV1A and RV1B become "H". n-channel MOS transistors Qn24, Qn2
When the voltage drop corresponding to the threshold value of 5 becomes a problem, the signals RV1A and RV1B may be boosted. At time t4R, the signals SAN1 and SAP1 are again "H" and "L", respectively.
As a result, the voltages at the nodes N1 and N2 are sensed and latched. Then, "whether the data of the memory cell is" 0 "," 1 "or" 2 "" is the flip-flop F.
Sensed by F1, the information is latched.

Next, it is sensed whether the memory cell is "1" or "2".

At time t5R, dummy bit line BLb is charged from VB to 1V. Capacitors Qd1 and Q at time t6R
The nodes N1 and N2 of d2 are made to be floating after being set to 1.5V. The signals BLCA and BLCB are again set to "L", and the bit line BLa and the MOS capacitor Q
The d1, bit line BLb and the MOS capacitor Qd2 are separated. The signals SAN2 and SAP2 are "L",
The signal becomes "H", the flip-flop FF2 is inactivated, and the signal ECH2 becomes "H" and is equalized.
After that, the signals RV2A and RV2B become "H". At time t7R, the signals SAN2 and SAP2 again become "H" and "L", respectively, so that the voltage of the node N1 is sensed and latched. The flip-flop F determines whether the data in the memory cell is "1" or "2".
Sensed by F2, that information is latched.

FIG. 7 shows flip-flops FF1 and FF.
FIG. 3 is a diagram showing read data which 2 senses and latches.

Flip-flops FF1 and FF at this time
The data of 2 is as shown in FIG. 7, and the data input / output line IO
Read data is output to A, IOB, IOC, and IOD.

Output data to the outside of the chip is input / output buffer 5 to data input lines IOA, IOB, IOC, IO.
It may be converted based on the signal output to D.

<Write Operation> Before the write operation, the input 2-bit data is the data input / output buffer 4
Is converted by and input to the data circuit 6 ^** .

FIG. 8 is a diagram showing write data input to the data circuit 6 ^** and latched by the flip-flops FF1 and FF2. 4-level data and data input / output line IO
The relationship among A, IOB, IOC, and IOD is as shown in FIG.

The converted ternary data is transferred to the data circuit at the column address designated by the address signal when the column activation signal CENB is "H".

FIG. 9 is an operation waveform diagram showing a write operation.

At time t1w, the voltage VA becomes the bit line write control voltage 1V and the bit line BLa becomes 1V.
When the voltage drop corresponding to the threshold value of the n-channel MOS transistor Qn39 becomes a problem, the signal BLCA may be boosted. Then, the signal PRE becomes "L" and the bit line is floated. Next, at time t2w, the signal R
V2A is set to 1.5V. By this, data “2”
In the column in which is held, the bit line control voltage 0V is applied to the bit line. n channel MOS transistor Q
If the threshold value of n32 is 1 V, it is "0" or "1".
During writing, n-channel MOS transistor Qn32
Is "OFF", and is "ON" when writing "2".
After that, VRFYBA becomes 0V at time t3w, and the bit line write control voltage VCC (for example, 5V) is output to the bit line from the data circuit holding the data "0".

As a result, the bit line for writing "0" becomes VCC, the bit line for writing "1" becomes 1V, and the bit line for writing "2" becomes 0V.

At time t1w, the select gate SG1 of the block selected by the control gate / select gate driving circuit is selected.
A, the control gates CG1A to CG4A become VCC. The selection gate SG2A is at 0V. Next, the selected control gate CG2A becomes the high voltage VPP (for example, 20V), and the non-selected control gates CG1A, CG3A, and CG4A become VM (for example, 10V). In the memory cell corresponding to the data circuit in which the data “2” is held, electrons are injected into the floating gate due to the potential difference between the channel potential of 0 V and VPP of the control gate, and the threshold value rises. In the memory cell corresponding to the data circuit holding the data “1”,
Due to the potential difference between the channel potential of 1 V and the VPP of the control gate, electrons are injected into the floating gate and the threshold value rises. The channel potential is set to 1V because the electron injection amount may be smaller than that in writing "2" data. In the memory cell corresponding to the data circuit in which the data “0” is held, since the potential difference between the channel potential and VPP of the control gate is small, electrons are not effectively injected into the floating gate. Therefore, the threshold value of the memory cell does not change.
During write operation, signals SAN1, SAN2, VRFYB
B, PREB, BLCB are “H”, signals SAP1, SA
P2, RV1A, RV1B, RV2B, ECH1, EC
H2 is "L" and the voltage VB is 0V.

<Verify Read Operation> FIG. 10 is an operation waveform diagram showing the verify read operation.

First, at time t1RV, the selected control gate CG2A of the block selected by the control gate / selection gate drive circuit is 2V, and the non-selection control gate CG1.
A, CG3A, CG4A and select gates SG1A, SG2
A is set to 6V. The source potential of the memory cell is set to 6V. In the case of writing "0", the bit line BLa is 3.
5V or more. When "1" writing is sufficient, the bit line BLa becomes 2.5 V or less, and when "1" writing is insufficient, 1.5 V or more. When "2" writing is sufficient, it becomes 0.5 V or less, and when "2" writing is insufficient, it becomes 0.5 V or more. The dummy bit line BLb is charged from VB to 2.5V. The potential of the dummy bit line BLb is reduced by 0.5V from 3V at the time of reading "1" in order to sufficiently write the memory cell. When the voltage drop corresponding to the threshold value of the n-channel MOS transistor Qn40 becomes a problem, the signal BLCA may be boosted.

At time t2RV, the nodes N1 and N2 of the capacitors Qd1 and Qd2 are set to 1.5V and then made floating. Then, VRFYBB1 becomes "H" at time t3RV. At this time, as can be seen from FIG. 7, the node N6 is "H" only when "2" is written.
Therefore, the dummy bit line BLb for writing "2" is Vre
It becomes 0.5V from f. The potential of the dummy bit line BLb for writing "2" is 0.5 than 1 V for reading "2".
The reason why V is reduced is to sufficiently write the memory cell. In the case of writing "0" or "1", N6 is "L", so n-channel MOS transistor Qn4
Is turned off and the dummy bit line BLb is kept at 2.5V.

At time t4RV, BLCA and BLCB are VC
It becomes C (for example, 5V), and the potentials of the bit lines BLa and BLb are transferred to N1 and N2. After that, signal BL again
CA and BLCB become "L", and bit lines BLa and M
The OS capacitor Qd1, the bit line BLb and the MOS capacitor Qd2 are separated.

At time t5RV, RV1A becomes 1.5V.
As a result, in the column where the data “0” is written, N
1 is grounded. n-channel MOS transistor Qn2
When the threshold value of 4 is 1 V, the n-channel MOS transistor Qn24 is "OFF" when writing "1" or "2", and is "ON" when writing "0".

The signals SAN1 and SAP1 are set to "L" and "H", respectively, to inactivate the flip-flop FF1, and the signal ECH1 is set to "H" and equalized. After that, the signals RV1A and RV1B become "H". N-channel MOS transistors Qn24, Qn25
When the voltage drop corresponding to the threshold value of
It is sufficient to boost V1A and RV1B. Again at time t4R,
When the signals SAN1 and SAP1 are set to "H" and "L", respectively, the voltages of the nodes N1 and N2 are sensed and latched.

As described above, the data circuit holding the "1" write data detects whether or not the data in the corresponding memory cell is sufficiently in the "1" write state. If the data in the memory cell is "1", the write data is changed to "1" by sensing and latching the voltage of the node N1 by the flip-flop FF1. If the data in the memory cell is not "1", the write data is held at "1" by sensing and latching the voltage of the node N1 by the flip-flop FF1. Also, "2"
The data circuit holding the write data detects whether or not the data in the corresponding memory cell is sufficiently in the "2" write state. If the data in the memory cell is "2", the write data is changed to "0" by sensing and latching the voltage of the node N1 by the flip-flop FF1. If the data of the memory cell is not “2”, the write data is held at “2” by sensing and latching the voltage of the node N1 with the flip-flop FF1. The write data of the data circuit holding the "0" write data is not changed.

During the write verify, the signal VRFYBB
Is "H" and the voltage Vs is 0V.

If all the selected memory cells for "1" write or "2" write have reached the desired threshold value, all the nodes N4 of the data circuit become "L". In other words, when all the selected memory cells for writing "1" or "2" are sufficiently written,
All of the data circuit ^{6 ** -0,6 ** -1, ...,} 6 ** -m-1,6
^**- m node N3 becomes "H" and N4 becomes "L". When this is detected, it is possible to know whether or not all the selected memory cells for "2" write or "3" write have reached the desired threshold value. For detecting the end of "2" write and "3" write, for example, as shown in FIG. 5, the "2" and "3" write end batch detection transistors Qn5 may be used. After the verify read, VRT is precharged to VCC, for example. If there is even one memory cell for which "1" or "2" writing is insufficient, the node N4 of the data circuit is "H", and therefore the n-channel MOS transistor Qn5
Turns on and VRT is grounded. When all "1" or "2" memory cell to write is written to enough, the data circuit ^{6 ** -0,6 ** -1, ...,} 6 ** -m-1,6 ** -m
Node N4 of "1" becomes "L". As a result, the n-channel MOS transistor Qn5 in all the data circuits is turned off, and VRT maintains the precharge potential.

Multi-valued storage NA according to the first embodiment
In the ND type EEPROM, at the time of writing data, at least one bit line voltage control circuit
The bit line is charged to the desired bit line write control voltage. Such a device has a simple circuit configuration,
It is possible to realize a bit line voltage control circuit that applies a bit line write control voltage according to n (n ≧ 2) value write data to a bit line.

Therefore, the circuit scale of the column system circuit 3 is reduced particularly by reducing the number of sense amplifier circuits, data latch circuits, and verify circuits, and a nonvolatile semiconductor memory device suitable for high integration can be obtained. .

<Second Embodiment> Next, a multi-valued memory NAND type EEPROM according to a second embodiment of the present invention will be described.

The EEPROM according to the first embodiment is
The example in which the number of multi-valued data is three-valued has been described.
After the EEPROM according to the embodiment of the present invention, an example in which the number of multi-valued data is four will be described.

The EEPRO according to the second embodiment
M has the same configuration as that shown in FIGS.

FIG. 11 is a diagram showing the threshold distribution of the memory cell transistor in the case of four-value storage.

When the EEPROM is of a four-value storage type, one memory cell transistor M is provided with four write states. The four write states are distinguished from each other by the threshold voltage of the memory cell transistor M.

As shown in FIG. 11, the power supply voltage VCC is 3
In the EEPROM of V, the state of data “0” is the same as the state after the data is erased, and has a negative threshold value, for example. Further, in the state of data “1”, for example, 0.5
It has a threshold value between V and 0.8V. The state of data "2" has a threshold value between 1.5V and 1.8V, for example. The state of data "3" has a threshold value between 2.5 V and 2.8 V, for example.

When reading data from the memory cell transistor M, three read voltages VCG2R, VCG3R and VCG1R are applied in this order to the control gate CG.

First, the read voltage V is applied to the control gate CG.
Apply CG2R. As a result, depending on whether the memory cell transistor M is “ON” or “OFF”, the stored data is ““ 0 ”,“ 1 ””, “2”,
Whether "3""is detected. Next, read voltage VCG
When 3R is applied, the stored data is "2".
Or "3" is detected, and the read voltage V
When CG1R is applied, whether the data is ““ 0 ””,
Whether "" 1 "" is detected. Read voltage VCG1R,
One example of VCG2R, VCG3R is 0V,
It is 1V and 2V.

Further, the voltages VCG1V and VC shown in FIG.
G2V and VCG3V are called verify read voltages and are read voltages used when checking whether or not data has been sufficiently written (verify operation). The verify read voltage is applied to the control gate CG after writing the data. When the verify read voltage is applied to the control gate CG, the threshold value of the memory cell transistor M is shifted to a range according to the written data depending on whether the memory cell transistor M is “ON” or “OFF”. You can know whether or not. Utilizing this, it is checked whether or not sufficient writing has been performed. One example of the verify read voltages VCG1V, VCG2V, VCG3V is:
They are 0.5V, 1.5V, and 2.5V, respectively.

FIG. 12 is a circuit diagram of a data circuit included in the EEPROM according to the second embodiment of the present invention.
The data circuit shown in FIG. 12 is configured with four-value storage as an example.

As shown in FIG. 12, a flip-flop FF1 composed of n-channel MOS transistors Qn21, Qn22 and Qn23 and p-channel MOS transistors Qp9, Qp10 and Qp11, and an n-channel M.
OS transistors Qn29, Qn30, Qn31 and p-channel MOS transistors Qp16, Qp17, Qp1
Write / read data is latched in the FF2 constituted by 8. These also operate as sense amplifiers.

The flip-flops FF1 and FF2 are
"Whether writing" 0 "or writing" 1 ",
"2" write or "3" write "is latched as write data information, and whether the memory cell holds" 0 "information or" 1 "information, "Whether information" 2 "is held or information" 3 "is held" is sensed and latched as read data information.

The data input / output lines IOA and IOB and the flip-flop FF1 are connected to the n-channel MOS transistor Q.
It is connected via n28 and Qn27. The data input / output lines IOC, IOD and the flip-flop FF2 are connected via n-channel MOS transistors Qn35, Qn36. Data input / output lines IOA, IOB, IOC, I
The OD is also connected to the data input / output buffer 5 shown in FIG.

N-channel MOS transistor Qn27,
The gates of Qn28, Qn35 and Qn36 are connected to the output of the column address decoder composed of the NAND logic circuit G2 and the inverter I4. The n-channel MOS transistors Qn26 and Qn34 equalize the flip-flops FF1 and FF2 with the signals ECH1 and ECH2 being "H". The n-channel MOS transistors Qn24 and Qn32 are flip-flops F
The connection between F1 and FF2 and the MOS capacitor Qd1 is controlled. N-channel MOS transistors Qn25, Qn33
Controls the connection between the flip-flops FF1 and FF2 and the MOS capacitor Qd2.

P channel MOS transistor Qp12,
The circuit composed of Qp13 has an activation signal VRFYBA.
Changes the gate voltage of the MOS capacitor Qd1 according to the data of the flip-flop FF1.
The circuit composed of p-channel MOS transistors Qp14 and Qp15 changes the gate voltage of the MOS capacitor Qd2 according to the data of the flip-flop FF1 by the activation signal VRFYBB. n-channel MO
The circuit composed of the S transistors Qn1 and Qn2 changes the gate voltage of the MOS capacitor Qd1 according to the data of the flip-flop FF2 by the activation signal VRFYBA1. n channel MOS transistor Q
The circuit composed of n3 and Qn4 has an activation signal VRFY.
The gate voltage of the MOS capacitor Qd2 is changed by BB1 according to the data of the flip-flop FF2.

The MOS capacitors Qd1 and Qd2 are composed of depletion type n-channel MOS transistors and are sufficiently smaller than the bit line capacitance. n channel M
The OS transistor Qn37 is set to M by the signal PREA.
The OS capacitor Qd1 is charged to the voltage VA. The n-channel MOS transistor Qn38 charges the MOS capacitor Qd2 to the voltage VB by the signal PREB. The n-channel MOS transistors Qn39 and Qn40 control the connection between the data circuit 3 and the bit lines BLa and BLb by the signals BLCA and BLCB, respectively. The circuit composed of the n-channel MOS transistors Qn37 and Qn38 also serves as the bit line voltage control circuit. p-channel MOS
A circuit composed of transistors Qp12 and Qp13, p
A circuit composed of channel MOS transistors Qp14 and Qp15, n-channel MOS transistors Qn1 and Qn
The circuit composed of 2 and the circuit composed of n-channel MOS transistors Qn3 and Qn4 are also bit line voltage control circuits. Further, the circuit composed of the flip-flop FF2 and the n-channel MOS transistors Qn32 and Qn33 also serves as the bit line voltage control circuit.

Next, the EEPROM configured as described above
The operation of will be described with reference to an operation waveform diagram. Hereinafter, a case where the control gate CG2A is selected will be described.

<Read Operation> FIG. 13 is an operation waveform diagram showing a read operation.

As shown in FIG. 13, first, at time t1R,
The voltages VA and VB are 1.8 V and 1.5 V, respectively, and the bit lines BLa and BLb are 1.8 V and 1.
It becomes 5V. The signals BLCA and BLCB become "L", the bit line BLa is disconnected from the MOS capacitor Qd1, the bit line BLb is disconnected from the MOS capacitor Qd2, and the bit lines BLa and BLb are floated. Signal PR
EA and PREB become "L", and MOS capacitor Q
The nodes N1 and N2 which are the gate electrodes of d1 and Qd2 are in a floating state. Subsequently, at time t2R, the selected control gate CG2A of the block selected by the control gate / selection gate drive circuit is 1V, the non-selection control gates CG1A, CG3A, CG4A and the selection gate SG1.
A and SG2A are set to VCC. If the threshold value of the selected memory cell is 1 V or less, the bit line voltage will be lower than 1.5 V. If the threshold value of the selected memory cell is 1 V or more, the bit line voltage remains at 1.8 V. After that, at time t3R, the signals BLCA and BLCB change to "H", and the data on the bit line is transferred to the MOS capacitors Qd1 and Qd2. After that, the signals BLCA and BLCB are again set to "L", and the bit line BLa and the MOS capacitor Q
The d1, bit line BLb and the MOS capacitor Qd2 are separated. Signals SAN1 and SAP1 are "L",
The signal becomes "H", the flip-flop FF1 is inactivated, and the signal ECH1 becomes "H" and equalized.
After that, the signals RV1A and RV1B become "H". At time t4R, the signals SAN1 and SAP1 again become "H" and "L", respectively, so that the voltages at the nodes N1 and N2 are sensed and latched. Thus, "whether the data in the memory cell is" 0 "or" 1 "or" 2 "or" 3 "" is sensed by the flip-flop FF1 and the information is latched.

Next, the selected control gate is set to 2V. At time t5R, the signals PREA and PREB become "H", and the nodes N1 and N2 which are the gate electrodes of the MOS capacitors Qd1 and Qd2 become 1.8V and 1.5V, respectively. The signals PREA and PREB become "L", and the MOS
Node N, which is the gate electrode of capacitors Qd1 and Qd2
1 and N2 are in a floating state. If the threshold voltage of the selected memory cell is 2V or less, the bit line voltage is 1.
It becomes lower than 5V. If the threshold voltage of the selected memory cell is 2V or higher, the bit line voltage remains 1.8V.
After that, the signals BLCA and BLCB are set to "H" at time t6R. The signals BLCA and BLCB are again set to "L" to disconnect the bit line BLa from the MOS capacitor Qd1 and the bit line BLb from the MOS capacitor Qd2. The signals SAN2 and SAP2 are set to "L" and "H", respectively, and the flip-flop FF2 is deactivated, and the signal EC
H2 becomes "H" and is equalized. After that, the signals RV2A and RV2B become "H". Again at time t7R,
When the signals SAN2 and SAP2 become "H" and "L", respectively, the voltage of the node N1 is sensed and latched. Thus, whether or not the data in the memory cell is "3" is sensed by the flip-flop FF2, and the information is latched.

FIG. 14 is a diagram showing read data sensed and latched by the flip-flops FF1 and FF2 at time t7R.

Finally, "whether or not the data written in the memory cell is" 0 "" is sensed. First, at time t8R, the bit lines BLa and BLb are charged to 1.8V and 1.5V, respectively, and then become floating. Further, the node N which is the gate electrode of the MOS capacitors Qd1 and Qd2.
1 and N2 are also in a floating state. Then, time t
The selected control gate CG2A of the block selected by the control gate / select gate drive circuit for 9R is set to 0V, and the non-selected control gates CG1A, CG3A, CG4A and the selection gates SG1A, SG2A are set to VCC. If the threshold value of the selected memory cell is 0V or less, the bit line voltage will be lower than 1.5V. If the threshold value of the selected memory cell is 0 V or more, the bit line voltage remains at 1.8 V. After this, at time t10R, the signals BLCA and BLCB change to "H", and the data on the bit line changes to the MOS capacitor Qd.
1, Qd2. Then, again, the signal BLC
A, BLCB become “L”, and the bit lines BLa and MO
The S capacitor Qd1, the bit line BLb and the MOS capacitor Qd2 are disconnected. Before sensing the data of the MOS capacitor, VRFYBA1 becomes VC at time t11R.
Become C. As can be seen from FIG. 14, the node N5 is "h".
Only the case of "3" data is "high level." Therefore, only in the case of "3" data, the n-channel MOS transistor Qn2 is turned on and the node N1 is grounded.
Then, the signals SAN2 and SAP2 are "L",
The signal becomes "H", the flip-flop FF2 is inactivated, and the signal ECH2 becomes "H" and is equalized.
After that, the signals RV2A and RV2B become "H". At time t12R, the signals SAN2 and SAP2 again become "H" and "L", respectively, so that the voltage of the node N1 is sensed and latched. Then, "whether the data in the memory cell is" 0 "" is sensed by the flip-flop FF2, and the information is latched.

FIG. 15 shows flip-flops FF1 and F.
FIG. 9 is a diagram showing read data which F2 senses and latches.

As a result of the above read operation, 4-level data is latched in the flip-flops FF1 and FF2 as shown in FIG.

The threshold distribution of each data in the figure is as follows.

Data “0” ・ ・ ・ Threshold value: 0V or less Data “1” ・ ・ ・ Threshold value 0.5V or more and 0.8V or less Data “2” ・ ・ ・ Threshold value 1.5V or more and 1.8V or less Data “ 3 "... threshold 2.5V or more and 2.8V or less During reading, signals VRFYBA and VRFYBB are" H "
It is. The voltage Vs (Vsa, Vsb) is 0V.

When the column activation signal CENB input to the column address decoder becomes "H", the data held in the data circuit selected by the address signal is output to the data input / output lines IOA, IOB, IOC, IOD. Via the data input / output buffer 5 to the EEPROM
Output to the outside.

Data stored in memory cells, threshold values, data input / output lines IOA, IOB, IOC, IOD
The relationship of the levels output after the reading is as shown in FIG.

The output data to the outside of the chip is transferred to the data input / output buffer 5 through the data input lines IOA, IOB, IOC,
It may be converted based on the signal output to the IOD.

<Write Operation> FIG. 16 is a schematic view showing the outline of the write operation.

As shown in FIG. 16, first, write data is loaded into the flip-flops FF1 and FF2.
Then, in the first cycle of the program, "2" data and "3" data are written almost simultaneously. And "2"
The verify read first cycle is performed to check whether the data and "3" data have been sufficiently written, and if there is a memory cell in which writing is insufficient, rewriting is performed.
When all the memory cells to be "2" written and "3" written are sufficiently written, the memory cells to be "1" written next are written almost simultaneously (second program cycle). Then, a second verify read cycle is performed to check whether "1" has been sufficiently written. Rewriting is performed on the memory cells in which "1" is not sufficiently written, and when all the memory cells are sufficiently written, the writing is completed.

The first program cycle, the first verify read cycle, the second program cycle, and the second verify read cycle will be described in detail below.

(1) First Program Cycle Before the write operation, the input 2-bit data is
The data circuit 6 ^** is converted by the data input / output buffer 4.
Is input to

FIG. 17 is a diagram showing write data input to the data circuit 6 ^** and latched by the flip-flops FF1 and FF2. 4-level data and data input / output line I
The relationship between OA, IOB, IOC, and IOD is as shown in FIG.

The converted 4-value data is transferred to the data circuit at the column address designated by the address signal when the column activation signal CENB is "H".

FIG. 18 shows the write operation (program first
FIG. 6 is an operation waveform diagram showing a cycle).

At time t1w, the voltage VA becomes the bit line write control voltage 1V and the bit line BLa becomes 1V.
When the voltage drop corresponding to the threshold value of the n-channel MOS transistor Qn39 becomes a problem, the signal BLCA may be boosted. Then, the signal PRE becomes "L" and the bit line is floated. Next, at time t2w, the signal R
V2A is set to 1.5V. By this, data “1”
Alternatively, in the column in which "3" is held, the bit line control voltage 0V is applied to the bit line. If the threshold value of the n-channel MOS transistor Qn32 is set to 1V, "0"
Alternatively, the n-channel MOS transistor Qn32 is "OFF" when writing "2", and is "ON" when writing "1" or "3". After that, at time t3w, VRFY
The bit line write control voltage VCC is output to the bit line from the data circuit in which BA becomes 0V and data "0" or data "1" is held.

As a result, the bit line for writing "0" or "1" becomes VCC, the bit line for writing "2" becomes 1V, and the bit line for writing "3" becomes 0V.

At time t1w, the select gate SG1 of the block selected by the control gate / select gate drive circuit is selected.
A, the control gates CG1A to CG4A become VCC. The selection gate SG2A is at 0V. Next, the selected control gate CG2A becomes the high voltage VPP (for example, 20V), and the non-selected control gates CG1A, CG3A, and CG4A become VM (for example, 10V). In the memory cell corresponding to the data circuit holding the data “3”, electrons are injected into the floating gate due to the potential difference between the channel potential of 0 V and VPP of the control gate, and the threshold value rises. In the memory cell corresponding to the data circuit holding the data “2”,
Due to the potential difference between the channel potential of 1 V and the VPP of the control gate, electrons are injected into the floating gate and the threshold value rises. The channel potential is set to 1V because the injection amount of electrons may be smaller than that in writing "3" data. In the memory cell corresponding to the data circuit holding the data “0” or the data “1”, the potential difference between the channel potential and VPP of the control gate is small, so that electrons are not effectively injected into the floating gate. Therefore, the threshold value of the memory cell does not change. During the write operation, the signals SAN1 and S
AN2, VRFYBB, PREB, BLCB are "H",
Signals SAP1, SAP2, RV1A, RV1B, RV2
B, ECH1, and ECH2 are "L", and the voltage VB is 0V.

(2) Verify Read First Cycle After the write operation, the threshold values of the memory cells for "2" write and the memory cells for "3" write are detected (write verify). If the desired threshold value is reached, the data in the data circuit is changed to "0". If the desired threshold value has not been reached, the data in the data circuit is held and the write operation is performed again. The first write cycle and the first write verify cycle are repeated until all the memory cells for "2" writing and the memory cells for "3" writing reach the desired threshold values.

FIG. 19 is an operation waveform diagram showing a verify read operation (verify read first cycle).

First, at time t1v, the voltages VA and VB become 1.8 V and 1.5 V, respectively, and the bit lines BLa and B are
Lb becomes 1.8V and 1.5V, respectively. Signal BLC
A, BLCB become “L”, and the bit lines BLa and MO
The S capacitor Qd1 and the bit line BLb are disconnected from the MOS capacitor Qd2, and the bit lines BLa and BLb become floating. The signals PREA and PREB become "L", and the nodes N1 and N2 which are the gate electrodes of the MOS capacitors Qd1 and Qd2 are brought into a floating state.
Subsequently, at time t2v, the selected control gate CG of the block selected by the control gate / select gate driving circuit is selected.
2A is 1.5V, unselected control gates CG1A, CG3
A, CG4A and select gates SG1A, SG2A are VCC
To be. The threshold of the selected memory cell is 1.5V
Below, the bit line voltage will be lower than 1.5V. If the threshold value of the selected memory cell is 1.5 V or more, the bit line voltage remains at 1.8 V. At time t3v, signal B
LCA and BLCB are set to "H", and the potential of the bit line is N
1 is transferred to N2. After that, the signals BLCA, BLC
When B becomes "L", the bit line BLa is disconnected from the MOS capacitor Qd1, and the bit line BLb is disconnected from the MOS capacitor Qd2. After that, at time t4v, the signal RV2A is set to 1.5 V which is lower than VCC, for example. When the threshold value of the n-channel MOS transistor Qn32 is 1V, the n-channel MOS transistor Qn32 is "ON" in the data circuit holding the "3" write data, and the node N
1 becomes 0V. In the data circuit holding the "2" write data, when the memory cell is sufficiently written with "2", the n-channel MOS transistor Qn 3
2 is "OFF", and the node N1 is kept at 1.5 V or higher. When the "2" write is insufficient, the voltage at the node N1 is 1.5 V or less. When the signal VRFYBA becomes "L" at time t5v, in the data circuit in which "0" or "1" write data is held, the p-channel MOS transistor Qp13 is "ON" and the node N1 is at VCC.
Becomes Signals SAN1 and SAP1 are "L",
The signal becomes "H", the flip-flop FF1 is inactivated, and the signal ECH1 becomes "H" and equalized.
After that, the signals RV1A and RV1B become "H". Again, the signals SAN1 and SAP1 are "H" and "L", respectively.
As a result, the voltage of the node N1 is sensed and latched at time t6v. With this, only the data circuit holding the "2" write data detects whether or not the data of the corresponding memory cell is sufficiently in the "2" write state.
If the data in the memory cell is "2", the write data is changed to "0" by sensing and latching the voltage of the node N1 by the flip-flop FF1. If the data in the memory cell is not "2", flip-flop FF
The write data is held at "2" by sensing and latching the voltage of the node N1 at "1". "0" or "1"
Alternatively, the write data of the data circuit holding the “3” write data is not changed.

Next, the selected control gate is brought to 2.5V. If the threshold of the selected memory cell is less than 2.5V, the bit line voltage will be less than 1.5V. If the threshold value of the selected memory cell is 2.5 V or more, the bit line voltage remains at 1.8 V. After this, at time t7v, the signals BLCA and BLCB are set to "H", and the potentials of the bit lines are transferred to N1 and N2. Again, the signals BLCA, BL
CB becomes "L", and the bit line BLa and the MOS capacitor Qd1 and the bit line BLb and the MOS capacitor Qd2.
Is cut off. After that, when the signal VRFYBC becomes "L", in the data circuit in which the "0" or "1" write data is held and the data circuit in which the "2" write is sufficiently performed, the p-channel MOS transistor Q
Since p12C is "ON", the node N1 becomes VCC. The signals SAN1 and SAP1 become "L" and "H", respectively, and the flip-flop FF1 is deactivated, and the signal EC
H1 becomes "H" and is equalized. After that, the signals RV1A and RV1B become "H". After that, time t8v
The signals SAN1 and SAP1 are "H" and "L", respectively.
As a result, the voltage of the node N1 is sensed and latched.

Thereafter, as shown in FIG. 19, conversion of write data is further performed. At time t9v, signal BL
CA and BLCB are set to "H" and the potential of the bit line is N
1 is transferred to N2. Again, the signals BLCA, BLCB
Becomes "L", and the bit line BLa is disconnected from the MOS capacitor Qd1, and the bit line BLb is disconnected from the MOS capacitor Qd2. After this, at time t10v, the signal VRFYBA1
Becomes "H", the n-channel MOS transistor Qn2 is "ON" in the data circuit holding the "0" or "2" write data, and the node N1 is at VCC.
Becomes The signals SAN2 and SAP2 are "L",
The signal becomes "H", the flip-flop FF2 is inactivated, and the signal ECH2 becomes "H" and is equalized.
After that, the signals RV2A and RV2B become "H". After that, at time t11v, the signals SAN2 and SAP2 become "H" and "L", respectively, so that the voltage of the node N1 is sensed and latched.

In the second embodiment, by setting VRFYBA1 to VCC at time t10v, the MOS capacitor Q for writing "0" and "2" is written.
The node N1 of d1 is charged to be higher than the potential (1.5V) of the node N2. For example, RV2B may be set to 1.5V at t10v. In this case, in the case of "0" write or "2" write, the node N6 is 0V.
Therefore, the n-channel MOS transistor Qn33 turns on and N
2 becomes 0V. On the other hand, in the case of writing "1" or "3", since the node N6 is at VCC and N2 is at 1.5V, the n-channel MOS transistor Qn33 is turned off and N2 is kept at 1.5V. VRFYBA1 is V at time t10v
Since the charge to N1 for writing "0" and "2" in CC is larger than the potential (0V) of N2, N1 may be charged at a low voltage of about 0.5V, for example.

As described above, only in the data circuit holding the "3" write data, it is detected whether or not the data in the corresponding memory cell is sufficiently in the "3" write state. If the data in the memory cell is "3", the write data is changed to "0" by sensing and latching the voltage of the node N1 by the flip-flops FF1 and FF2. If the data in the memory cell is not "3", the write data is held at "3" by sensing and latching the voltage of the node N1 by the flip-flops FF1 and FF2. The write data of the data circuit holding the "0" or "1" or "2" write data is not changed.

During write verify, signal VRFYBB
Is "H" and the voltage Vs is 0V.

In FIG. 20, the flip-flops FF1 and FF2 are written after "2" or "3" has been sufficiently written.
FIG. 6 is a diagram showing latched data.

If all the selected memory cells for "2" write or "3" write have reached the desired threshold value, the data of the data circuit becomes as shown in FIG. That "2" writing or "3" When all the memory cells selected for writing is written to enough, all of the data circuit ^{6 ** -0,6 ** -1, ...,} 6 ** -m-1 , 6 ^**- m node N3 becomes "H" and N4 becomes "L". When this is detected, it is possible to know whether or not all the selected memory cells for "2" write or "3" write have reached the desired threshold value.

FIG. 21 is a circuit diagram of a data circuit having a write completion batch detection transistor.

The detection of "2" write and "3" write end is performed by detecting "2" as shown in FIG.
The "3" write completion batch detection transistor Qn5 may be used. VRT is precharged to VCC, for example, after the first cycle of verify read. If there is even one memory cell for which "2" or "3" writing is insufficient, the node N4 of the data circuit is "H", the n-channel MOS transistor Qn5 is turned on, and VRT is grounded. When all the memory cells to be written “2” or “3” are sufficiently written, the data circuits 6 ^** -0, 6
^** -1, ..., node N4 of 6 ^** -m-1,6 ^** -m becomes "L". As a result, the n-channel MOS transistors Qn5 in all the data circuits are turned off and VRT maintains the precharge potential.

(3) Second cycle of program After the writing of "2" and "3" is completed,
"1" write (program second cycle) is performed. The node potential of the flip-flop at the time of writing "1" is shown in FIG. That is, in the case of "1" write, the node N5 becomes "L" and the write potential is applied to the bit line, and except for the "1" write, the node N5 becomes "H" and the write non-select potential is set in the bit line. Is applied.

FIG. 22 shows the write operation (program second
FIG. 6 is an operation waveform diagram showing a cycle).

At time t1p, the voltage VRFYBA1 is "H".
Then, the bit line BLa for writing "0", "2" or "3" is charged to the write non-select voltage VCC. When the voltage drop corresponding to the threshold value of the n-channel MOS transistor Qn39 becomes a problem, the signal BLCA may be boosted. Then, the signal RV2A is set to VCC. As a result, the write non-selection voltage VCC is applied to the bit line BLa from the data circuit holding the data "0", "2" or "3". From the data circuit holding the data "1", the bit line BL
The write bit line potential 0V is applied to a.

By the control gate / select gate driving circuit, the select gate SG1A and the control gates CG1A to CG4A of the selected block become VCC. Select gate S
G2A is 0V. Next, the control gate CG2A selected at time t2p becomes the high voltage VPP (for example, 20V), and the non-selection control gates CG1A, CG3A, and CG4A become VM (for example, 10V). In the memory cell corresponding to the data circuit holding the data “1”, electrons are injected into the floating gate due to the potential difference between the channel potential of 0 V and VPP of the control gate, and the threshold value rises. In the memory cell corresponding to the data circuit holding the data "0" or "2" or "3", the potential difference between the channel potential and VPP of the control gate is small, so that electrons are not effectively injected into the floating gate. . Therefore, the threshold value of the memory cell does not change. During the write operation, signals SAN1 and SAN
2, VRFYBB, PREB, BLCB are “H”, signals SAP1, SAP2, RV1A, RV1B, ECH1,
ECH2 is "L" and the voltage VB is 0V.

(4) Verify Read Second Cycle After completion of the write second cycle, the threshold value of the memory cell in which "1" is written is detected (write verify second
cycle). If the desired threshold value is reached, the data in the data circuit is changed to "0". If the desired threshold value has not been reached, the data in the data circuit is held and the write operation is performed again. The write operation and the write verify are repeated until all the "1" write memory cells reach the desired threshold value.

FIG. 24 is an operation waveform diagram showing a verify read operation (verify read second cycle).

First, at time t1y, the voltages VA and VB become 1.8 V and 1.5 V, respectively, and the bit lines BLa and B are
Lb becomes 1.8V and 1.5V, respectively. Signal BLC
A, BLCB become “L”, and the bit lines BLa and MO
The S capacitor Qd1 and the bit line BLb are disconnected from the MOS capacitor Qd2, and the bit lines BLa and BLb become floating. The signals PREA and PREB become "L", and the nodes N1 and N2 which are the gate electrodes of the MOS capacitors Qd1 and Qd2 are brought into a floating state.
Then, at time t2y, the selected control gate CG of the block selected by the control gate / select gate drive circuit is selected.
2A is 0.5V, non-selection control gates CG1A, CG3
A, CG4A and select gates SG1A, SG2A are VCC
To be. The threshold value of the selected memory cell is 0.5 V
Below, the bit line voltage will be lower than 1.5V. If the threshold value of the selected memory cell is 0.5 V or more, the bit line voltage remains at 1.8 V. At time t3y, signal B
LCA and BLCB are set to "H", and the potential of the bit line is N
1 is transferred to N2. After that, the signals BLCA, BLC
When B becomes "L", the bit line BLa is disconnected from the MOS capacitor Qd1, and the bit line BLb is disconnected from the MOS capacitor Qd2. After that, when the signal VRFYBA1 becomes "H" at time t4y, in the data circuit holding the write data "0", "2" or "3", the n-channel MOS transistor Qn2 is "ON" and the node N
1 becomes VCC.

The signals SAN2 and SAP2 are set to "L" and "H", respectively, to inactivate the flip-flop FF2, and the signal ECH2 is set to "H" and equalized. After that, the signals RV2A and RV2B become "H". Again, the signals SAN2 and SAP2 are "H",
When it becomes "L", the voltage of the node N1 is sensed and latched at time t5y. Thus, only the data circuit holding the "1" write data detects whether or not the data of the corresponding memory cell is sufficiently in the "1" write state. If the data in the memory cell is "1", the write data is changed to "0" by sensing and latching the voltage of the node N1 by the flip-flop FF2. If the data in the memory cell is not "1", the write data is held at "1" by sensing and latching the voltage of the node N2 by the flip-flop FF1. The write data of the data circuit holding the "0", "2" or "3" write data is not changed.

FIG. 24 is a diagram showing data latched by the flip-flops FF1 and FF2 after "3" has been sufficiently written.

If all the selected memory cells for writing "1" have reached the desired threshold value, the data of the data circuit becomes as shown in FIG. That "1" when all of the memory cell write is written to enough, all of the data circuit 6 ^** -0,6 ^** -1, ..., of 6 ^** -m-1, 6 ^** -m node N5 becomes "H" and N6 becomes "L". When this is detected, it is known whether all the selected memory cells have reached the desired threshold value.

To detect the end of writing in the program cycle 2, for example, the write end collective detection transistor Qn6 as shown in FIG. 21 may be used. VRED is
After the second cycle of the verify read, it is precharged to VCC, for example. If there is even one memory cell in which "1" writing is insufficient, the node N6 of the data circuit is "H", the n-channel MOS transistor Qn6 is turned on, and VRED is grounded. When all the memory cells have been sufficiently written, the data circuits 6 ^**- 0, 6 ^** -1, ..., 6
^** node N6 of -m-1,6 ^** -m becomes "L". As a result, the n-channel MOS transistors Qn6 in all the data circuits are turned off and VRED maintains the precharge potential.

As described above, the EEPRO according to the second embodiment
Although M has been described, other operations such as verify read, write, and normal read are possible.

FIG. 25 is an operation waveform diagram showing another verify read operation (verify read first cycle).

For example, the verify read first cycle may be operated as shown in the operation waveform diagram of FIG.

In the verify read first cycle shown in FIG. 25, the operation until time t7v is the same as the verify read first cycle shown in FIG. 19, but the operation after time t7v is different.

At time t7v, the signals BLCA and BLCB are set to "H", and the potentials of the bit lines are transferred to N1 and N2. When the threshold voltage of the memory cell is 2.5 V or more, the bit line BLa is 1.5 V or more, and when it is 2.5 V or less, the bit line BLb is 1.5 V or less. After that, the signals BLCA and BLCB become "L", and the bit line BLa and the MOS capacitor Qd1 are separated from the bit line BLb and the MOS capacitor Qd2. After that, when the signal VRFYBA1 becomes “H” at time t8z, in the data circuit holding the “0” or “2” write data, the n-channel MOS transistor Qn2 is “ON” and the node N1 is 1. It becomes 5V or more. Signal SAN
2, SAP2 becomes "L" and "H", respectively, and the flip-flop FF2 is inactivated, and the signal ECH2 becomes "H" and is equalized. After this, the signal RV2
A and RV2B become "H". After that, at time t9z, the signals SAN2 and SAP2 become "H" and "L", respectively, so that the voltage of the node N1 is sensed and latched.

Thereafter, as shown in FIG. 25, conversion of write data is further performed. At time t10z, signal B
LCA and BLCB are set to "H", and the potential of the bit line is N
1 is transferred to N2. Again, the signals BLCA, BLCB
Becomes "L", and the bit line BLa is disconnected from the MOS capacitor Qd1, and the bit line BLb is disconnected from the MOS capacitor Qd2. After that, when the signal VRFYBA becomes "L" at time t11z, in the data circuit in which "0" or "1" write data is held and in the data circuit in which "2" write is sufficiently performed, The transistor Qp13 is "ON" and the node N1 is VC.
C. Signals SAN1 and SAP1 are "L",
The signal becomes "H", the flip-flop FF1 is inactivated, and the signal ECH1 becomes "H" and equalized.
After that, the signals RV1A and RV1B become "H". After that, at time t12z, the signals SAN1 and SAP1 become "H" and "L", respectively, so that the voltage of the node N1 is sensed and latched.

As described above, only the data circuit holding the "3" write data can detect whether or not the data in the corresponding memory cell is sufficiently in the "3" write state. If the data in the memory cell is "3", flip
The write data is changed to "0" by sensing and latching the voltage of the node N1 by the flops FF1 and FF2. If the data in the memory cell is not "3", the write data is held at "3" by sensing and latching the voltage of the node N1 by the flip-flops FF1 and FF2. The write data of the data circuit holding the "0" or "1" or "2" write data is not changed. If all the selected memory cells for "2" write or "3" write have reached the desired threshold value,
The data of the data circuit is as shown in FIG. That is,
"2" writing or "3" When all the memory cells selected for writing is written to enough, all of the data circuit ^{6 ** -0,6 ** -1, ...,} 6 ** -m-1, The node N3 of 6 ^**- m becomes "H" and N4 becomes "L". By detecting this, it is possible to know whether or not all the selected memory cells for "2" write or "3" write have reached the desired threshold value.

The circuit configuration of the data circuit is also shown in FIG.
The circuit configuration is not limited to that shown in FIG. 21, and other circuit configurations may be used.

26 and 27 are other circuit diagrams of the data circuit, respectively.

VRFYBA of the data circuit shown in FIG.
1, VRFYBB1 operation timing is shown in FIG.
When the same operation timing as that of the data circuit of No. 1 is used (operation waveform chart; FIG. 13, FIG. 18, FIG. 19, FIG. 22, FIG.
3, FIG. 25), VCC may be 0V and 0V may be VCC. The operation timings of VRFYBA and VRFYBB are the same as those when the data circuits of FIGS. 12 and 21 are used.

The VRF of the data circuit shown in FIG.
The operation timings of YBA and VRFYBB are the same as those of the data circuits of FIGS. 12 and 21 (operation waveform diagrams; FIGS. 13, 18, 19, 22, and 2).
3, FIG. 25), VCC may be 0V and 0V may be VCC. The operation timings of VRFYBA1 and VRFYBB1 are the same as when the data circuits of FIGS. 12 and 21 are used.

In the second embodiment, first, "2",
The "3" data was written at the same time, and then the "1" data was written. However, the writing order is highly arbitrary. For example, "1" and "2" may be written and then "3" may be written next, or "1" and "3" may be written and then "2" may be written.

<Third Embodiment> Next, a multi-valued memory NAND type EEPROM according to a third embodiment of the present invention will be described.

In the second embodiment, first, "2" is set.
After writing state and "3" state almost simultaneously,
Although the one in which the "1" state is written has been exemplified, in the third embodiment, the "1" state, the "2" state, and the "3" state.
The state is written almost at the same time.

The EEPRO according to the third embodiment
M is the same as the EEPROM according to the second embodiment,
It has the same configuration as that shown in FIGS.

FIG. 28 is a circuit diagram of a data circuit included in the EEPROM according to the third embodiment of the present invention.
The data circuit shown in FIG. 28 is configured with four-value storage as an example.

As shown in FIG. 28, memory cells M1 to M
4 are connected in series to form a NAND cell.
Both ends thereof are connected to the bit line BL and the source line Vs via the selection transistors S1 and S2, respectively. The memory cells M group sharing the control gate CG form a unit called "page", and data is written / read at the same time. Further, a block is formed by the memory cell group connected to the four control gates CG1 to CG4. "page",
The "block" is selected by the control gate / select gate driving circuit. Each bit line BL0 ～BLm, data circuits ^{6 ** -0,6 ** -1, ...,} 6 ** -m-1,6 ** -m are connected, data to be written into the corresponding memory cell To temporarily remember.

The relationship between the write state of the memory cell and the threshold value is the same as that of the first embodiment. For example, FIG.
As shown in FIG.

As shown in FIG. 28, a flip-flop FF1 composed of n-channel MOS transistors Qn21, Qn22 and Qn23 and p-channel MOS transistors Qp9, Qp10 and Qp11, and an n-channel M.
OS transistors Qn29, Qn30, Qn31 and p-channel MOS transistors Qp16, Qp17, Qp1
Write / read data is latched in the FF2 constituted by 8. These also operate as sense amplifiers.

The flip-flops FF1 and FF2 are
"Whether writing" 0 "or writing" 1 ",
"2" write or "3" write "is latched as write data information, and whether the memory cell holds" 0 "information or" 1 "information, "Whether information" 2 "is held or information" 3 "is held" is sensed and latched as read data information.

The data input / output lines IOA and IOB and the flip-flop FF1 are connected to the n-channel MOS transistor Q.
It is connected via n28 and Qn27. The data input / output lines IOC, IOD and the flip-flop FF2 are connected via n-channel MOS transistors Qn35, Qn36. Data input / output lines IOA, IOB, IOC, I
The OD is also connected to the data input / output buffer 4 in FIG.

N-channel MOS transistor Qn27,
The gates of Qn28, Qn35 and Qn36 are connected to the output of the column address decoder composed of the NAND logic circuit G2 and the inverter I4. The n-channel MOS transistors Qn26 and Qn34 equalize the flip-flops FF1 and FF2 with the signals ECH1 and ECH2 being "H". The n-channel MOS transistors Qn24 and Qn32 are flip-flops F
The connection between F1 and FF2 and the MOS capacitor Qd1 is controlled. N-channel MOS transistors Qn25, Qn33
Controls the connection between the flip-flops FF1 and FF2 and the MOS capacitor Qd2.

P-channel MOS transistor Qp12
The circuit composed of C and Qp13C has an activation signal VRF.
The YBAC changes the gate voltage of the MOS capacitor Qd1 according to the data of the flip-flop FF1. p-channel MOS transistors Qp14C, Qp
The circuit composed of 15C has an activation signal VRFYBBC.
Thus, the gate voltage of the MOS capacitor Qd2 is changed according to the data of the flip-flop FF1.
p-channel MOS transistors Qp12C, Qp19
The circuit composed of C and Qp20C has an activation signal VRF.
The YBA2C changes the gate voltage of the MOS capacitor Qd1 according to the data of the flip-flops FF1 and FF2. p channel MOS transistor Q
The circuit composed of p14C, Qp21C, and Qp22C is flipped by the activation signal VRFYBB2C.
Depending on the data of the flops FF1 and FF2, the MOS
The gate voltage of the capacitor Qd2 is changed. The circuit including the n-channel MOS transistors Qn1C and Qn2C changes the gate voltage of the MOS capacitor Qd1 according to the data of the flip-flop FF2 by the activation signal VRFYBA1C. The circuit composed of n-channel MOS transistors Qn3C and Qn4C changes the gate voltage of the MOS capacitor Qd2 according to the data of the flip-flop FF2 by the activation signal VRFYBB1C.

MOS capacitors Qd1 and Qd2 are formed of depletion type n-channel MOS transistors, and are sufficiently smaller than the bit line capacitance. n channel M
The OS transistor Qn37 is set to M by the signal PREA.
The OS capacitor Qd1 is charged to the voltage VA. The n-channel MOS transistor Qn38 charges the MOS capacitor Qd2 to the voltage VB by the signal PREB. The n-channel MOS transistors Qn39 and Qn40 control the connection between the data circuit 3 and the bit lines BLa and BLb by the signals BLCA and BLCB, respectively. The circuit composed of the n-channel MOS transistors Qn37 and Qn38 also serves as the bit line voltage control circuit.

Next, the EEPROM configured as described above
The operation of will be described with reference to an operation waveform diagram. Hereinafter, a case where the control gate CG2A is selected will be described.

<Read Operation> FIG. 29 is an operation waveform diagram showing a read operation.

As shown in FIG. 29, first, the voltages VA and V
B becomes 1.8V and 1.5V respectively, and bit line B
La and BLb are 1.8V and 1.5V, respectively. At time t1RC, the signals BLCA and BLCB become "L",
Bit line BLa, MOS capacitor Qd1, bit line B
The Lb and the MOS capacitor Qd2 are separated, and the bit lines BLa and BLb become floating. Signal PRE
A and PREB become "L", and MOS capacitor Qd
Nodes N1 and N2, which are gate electrodes of 1 and Qd2, are in a floating state. Subsequently, at time t2RC, the selected control gate CG2A of the block selected by the control gate / selection gate drive circuit is 0V, the non-selection control gates CG1A, CG3A, CG4A and the selection gate SG1.
A and SG2A are set to VCC. If the threshold value of the selected memory cell is 0V or less, the bit line voltage will be lower than 1.5V. If the threshold value of the selected memory cell is 0 V or more, the bit line voltage remains at 1.8 V. After that, at time t3RC, the signals BLCA and BLCB change to "H", and the data on the bit line is transferred to the MOS capacitors Qd1 and Qd2. After that, the signals BLCA and BLCB are again set to "L", and the bit line BLa and the MOS capacitor Q
The d1, bit line BLb and the MOS capacitor Qd2 are separated. Signals SAN1 and SAP1 are "L",
The signal becomes "H", the flip-flop FF1 is inactivated, and the signal ECH1 becomes "H" and equalized.
After that, the signals RV1A and RV1B become "H". At time t4RC, the signals SAN1 and SAP1 again become "H" and "L", respectively, so that the voltage of the node N1 is sensed and latched. With this, "whether the data of the memory cell is" 0 ", or" 1 "or" 2 "or" 3 ""
Is sensed by flip-flop FF1 and that information is latched.

Next, the selected control gate is set to 1V. If the threshold of the selected memory cell is less than 1V,
The bit line voltage will be lower than 1.5V. If the threshold voltage of the selected memory cell is 1 V or higher, the bit line voltage is 1.
It remains at 8V. Signals PREA, PRE at time t5RC
B becomes "H", and MOS capacitors Qd1 and Qd2
The gate electrodes of the nodes N1 and N2 are 1.8
It becomes V and 1.5V. Signals PREA and PREB are "L"
Then, the nodes N1 and N2, which are the gate electrodes of the MOS capacitors Qd1 and Qd2, are brought into a floating state. After that, the signals BLCA and BLCB are set to "H" at time t6RC. The signals BLCA and BLCB are again set to "L", and the bit line BLa and the MOS capacitor Q
The d1, bit line BLb and the MOS capacitor Qd2 are separated. The signals SAN2 and SAP2 are "L",
The signal becomes "H", the flip-flop FF2 is inactivated, and the signal ECH2 becomes "H" and is equalized.
After that, the signals RV2A and RV2B become "H". At time t7RC, the signals SAN2 and SAP2 again become "H" and "L", respectively, so that the voltage of the node N1 is sensed and latched. With this, "whether the data of the memory cell is" 0 "or" 1 ", or" 2 "or" 3 ""
Is sensed by flip-flop FF2 and that information is latched.

FIG. 30 shows a flip-flop at time t7RC.
FIG. 6 is a diagram showing read data sensed and latched by flops FF1 and FF2. At this time, the potentials of the nodes N3C and N5C of the flip-flops FF1 and FF2 are as shown in FIG.
It will be like 0.

Lastly, whether the data written in the memory cell is "2" or "3" is sensed. The selected control gate is brought to 2V. If the threshold of the selected memory cell is less than 2V, the bit line voltage will be less than 1.5V. If the threshold voltage of the selected memory cell is 2V or higher, the bit line voltage remains 1.8V. Time t8RC
The signals PREA and PREB are set to "H", and the node N which is the gate electrode of the MOS capacitors Qd1 and Qd2.
1 and N2 are 1.8V and 1.5V, respectively. Signal P
REA and PREB are set to "L", and the nodes N1 and N2 which are the gate electrodes of the MOS capacitors Qd1 and Qd2 are brought into a floating state. After that, the signals BLCA and BLCB are set to "H" at time t10RC. Then again
The signals BLCA and BLCB become "L", and the bit line B
La and MOS capacitor Qd1, bit line BLb and MO
The S capacitor Qd2 is disconnected. Before sensing the data of MOS capacitor, VRFYB at time t11RC
A2C becomes 0V. As can be seen from FIG. 22, the node N5C is "Low level" and the node N3C is "Highle".
vel ”(that is, the node N4C becomes“ Low level ”) only in the case of“ 1 ”data. Therefore, only in the case of“ 1 ”data, the p-channel MOS transistor Qp12C,
Qp19C and Qp20C are turned on, and node N1 is at VCC
become. After that, the signals SAN1 and SAP1 become "L" and "H", respectively, and the flip-flop FF1 is deactivated, and the signal ECH1 becomes "H" and is equalized. After that, the signals RV1A and RV1B become "H". At time t12RC, the signals SAN1 and SAP1 again become "H" and "L", respectively, so that the voltage of the node N1 is sensed and latched. Thus, "whether the data in the memory cell is" 2 "or" 3 "" is sensed by the flip-flop FF1 and the information is latched.

FIG. 31 shows flip-flops FF1 and F.
FIG. 9 is a diagram showing read data which F2 senses and latches.

As a result of the above read operation, 4-level data is latched in the flip-flops FF1 and FF2 as shown in FIG. The threshold distribution of each data in the figure is as follows.

Data “0” ... Threshold value: 0V or less Data “1” ... Threshold value 0.5V or more and 0.8V or less Data “2” ... Threshold value 1.5V or more and 1.8V or less Data “ 3 "... Threshold value 2.5V or more and 2.8V or less During reading, the signals VRFYBAC and VRFYBBC are" H ", and the signals VRFYBA1C and VRFYBB1C are" L ". The voltage Vs is 0V.

When the column activation signal CENB input to the column address decoder becomes "H", the data held in the data circuit selected by the address signal is output to the data input / output lines IOA, IOB, IOC, IOD. Via the data input / output buffer 4 to the EEPROM
Output to the outside.

Data stored in memory cells, threshold values, data input / output lines IOA, IOB, IOC, IOD
The relationship of the levels output after the reading is shown in FIG.

The output data to the outside of the chip is transferred to the data input / output buffer 5 through the data input lines IOA, IOB, IOC,
It may be converted based on the signal output to the IOD.

<Write Operation> First, write data is loaded into the flip-flops FF1 and FF2. After that, "1" data, "2" data and "3" data are written almost simultaneously. And "1" data, "2"
Verify read is performed to check whether the data and "3" data have been sufficiently written, and if there is an insufficiently written memory cell, rewriting is performed. Writing is completed when the write completion detection circuit detects that all memory cells are sufficiently programmed.

In the following, the program will be described first, and then the verify read will be described.

(1) Program The 2-bit data inputted before the write operation is
The data circuit 6 ^** is converted by the data input / output buffer 5.
Is input to

FIG. 32 is a diagram showing write data input to the data circuit 6 ^** and latched by the flip-flops FF1 and FF2. 4-level data and data input / output line I
The relationship between OA, IOB, IOC, and IOD is as shown in FIG.

The converted 4-value data is transferred to the data circuit at the column address designated by the address signal when the column activation signal CENB is "H".

FIG. 33 is an operation waveform diagram showing a write operation.

First, at time t1s, the voltage VA becomes the bit line write control voltage 1V and the bit line BLa becomes 1V. When the voltage drop corresponding to the threshold value of the n-channel MOS transistor Qn39 becomes a problem, the signal BLCA may be boosted. Then, the signal PRE becomes "L" and the bit line is floated. Next, at time t2s, the signal RV2A is set to 1.5V. As a result, since the data "1" or "3" is held, the bit line control voltage 0V is applied to the bit line. n-channel MOS
If the threshold value of the transistor Qn32 is 1 V,
When writing "0" or "2", the n-channel MOS transistor Qn32 is "OFF", "1" or "3".
It becomes "ON" at the time of writing. After that, at time t3s, V
RFYBAC becomes 0V, and the bit line write control voltage VCC is output to the bit line from the data circuit that holds the data “0” or the data “1”.

Then, at time t4s, VRFYBA2C becomes 0.
The voltage V becomes V, and the data line holding the data “1” outputs the bit line “1” write potential 2V to the bit line via V1.

As a result, the bit line for writing "0" becomes VCC, the bit line for writing "1" becomes 2V, the bit line for writing "2" becomes 1V, and the bit line for writing "3" becomes 0V.

At time t1s, the select gate SG1 of the block selected by the control gate / select gate driving circuit is selected.
A, the control gates CG1A to CG4A become VCC. The selection gate SG2A is at 0V. Next, the selected control gate CG2A becomes the high voltage VPP (for example, 20V), and the non-selected control gates CG1A, CG3A, and CG4A become VM (for example, 10V). In the memory cell corresponding to the data circuit holding the data “3”, electrons are injected into the floating gate due to the potential difference between the channel potential of 0 V and VPP of the control gate, and the threshold value rises. In the memory cell corresponding to the data circuit holding the data “2”,
Due to the potential difference between the channel potential of 1 V and the VPP of the control gate, electrons are injected into the floating gate and the threshold value rises. In the memory cell corresponding to the data circuit holding the data “1”, electrons are injected into the floating gate and the threshold value rises due to the potential difference between the channel potential of 2V and VPP of the control gate. The channel potential in the case of writing "2" is set to 1 V, and the channel potential in the case of writing "1" is set to 2 V because the injection amount of electrons is "3" when writing data, when "2" writing is set to "2". This is to reduce the number in the order of 1 ”writing. In the memory cell corresponding to the data circuit in which the data “0” is held, since the potential difference between the channel potential and VPP of the control gate is small, electrons are not effectively injected into the floating gate. Therefore, the threshold value of the memory cell does not change. During writing operation, signal S
AN1, SAN2, PREB, BLCB are "H", signals SAP1, SAP2, VRFYBA1C, RV1A, R
V1B, RV2B, ECH1 and ECH2 are "L", and the voltage VB is 0V.

(2) Verify Read After the write operation, it is detected whether or not the write is sufficiently performed (write verify). If the desired threshold value is reached, the data in the data circuit is changed to "0".
If the desired threshold value has not been reached, the data in the data circuit is held and the write operation is performed again. The write operation and the write verify are repeated until all the memory cells for "1" write, the memory cells for "2" write and the memory cells for "3" write reach the desired threshold value.

34 and 35 are operation waveform diagrams showing the verify read operation, respectively.

The write verify operation will be described below with reference to FIGS. 34 and 35.

First, it is detected whether or not the memory cell for writing "1" has reached a predetermined threshold value.

First, as shown in FIG. 34, time t1yc
And the voltages VA and VB are 1.8V and 1.5V, respectively, and the bit lines BLa and BLb are 1.8V and respectively.
1.5V. The signals BLCA and BLCB become "L", the bit line BLa is disconnected from the MOS capacitor Qd1, the bit line BLb is disconnected from the MOS capacitor Qd2, and the bit lines BLa and BLb are floated. Signal P
REA and PREB are set to "L", and the nodes N1 and N2 which are the gate electrodes of the MOS capacitors Qd1 and Qd2 are brought into a floating state. Then, at time t2yc, the selected control gate CG2A of the block selected by the control gate / selection gate drive circuit is set to 0.5V, and the non-selected control gates CG1A, CG3A, CG4A and the selection gates SG1A, SG2A are set to VCC. . If the threshold value of the selected memory cell is 0.5V or less, the bit line voltage will be lower than 1.5V. If the threshold value of the selected memory cell is 0.5 V or more, the bit line voltage remains at 1.8 V. At time t3yc, the signals BLCA and BLCB are set to "H", and the potentials of the bit lines are transferred to N1 and N2. After that, the signals BLCA and BLCB become "L", and the bit line BLa and the MOS capacitor Qd1 are separated from the bit line BLb and the MOS capacitor Qd2. After that, RV1A becomes 1.5V at time t4yc, and the node N1 is discharged to 0V in the case of "2" write and "3" write. Signal VRFYB at time t5yc
When A1C becomes “H”, in the data circuit holding the “0” or “2” write data, the n-channel M
The OS transistor Qn2 is "ON", and the node N1 becomes VCC. As a result, the node N1 becomes VCC when writing "0" or "2", and becomes 0 V when writing "3".

The signals SAN2 and SAP2 are set to "L" and "H", respectively, to inactivate the flip-flop FF2, and the signal ECH2 is set to "H" and equalized. After that, the signals RV2A and RV2B become "H". Again, the signals SAN2 and SAP2 are "H",
When it becomes "L", the voltage of the node N1 is sensed and latched at time t6yc. Thus, only the data circuit holding the "1" write data detects whether or not the data of the corresponding memory cell is sufficiently in the "1" write state. If the data in the memory cell is "1", the write data is changed to "0" by sensing and latching the voltage of the node N1 by the flip-flop FF2. If the data in the memory cell is not "1", the write data is held at "1" by sensing and latching the voltage of the node N2 by the flip-flop FF1. The write data of the data circuit holding the "0", "2" or "3" write data is not changed.

Next, the selected control gate is set to 1.5V. If the threshold of the selected memory cell is less than 1.5V, the bit line voltage will be less than 1.5V. If the threshold value of the selected memory cell is 1.5 V or more, the bit line voltage remains at 1.8 V. PRE at time t7yc
A and PREB are set to VCC, and the nodes N1 and N2 are 1.8.
After V and 1.5V, it becomes floating. Thereafter, at time t8yc, the signals BLCA and BLCB are set to "H", and the potentials of the bit lines are transferred to N1 and N2. After that, the signals BLCA and BLCB become "L", and the bit line BLa and the MOS capacitor Qd1 are separated from the bit line BLb and the MOS capacitor Qd2. After that, at time t9yc, the signal RV2A is, for example, 1.5 V below VCC.
It is said. When the threshold value of the n-channel MOS transistor Qn32 is 1 V, the n-channel MOS transistor Qn is used in the data circuit holding the "3" write data.
n 32 is “ON”, and the node N1 becomes 0V. "2"
In the data circuit holding the write data, when the memory cell is sufficiently written with "2", the n-channel MOS transistor Qn32 is "OFF" and the node N1 is kept at 1.5 V or more. When the "2" write is insufficient, the voltage at the node N1 is 1.5 V or less. When the signal VRFYBAC becomes "L" at time t10yc, "0"
Alternatively, in the data circuit in which the "1" write data is held, the p-channel MOS transistor Qp13 is "O".
N ″, and the node N1 becomes VCC.

The signals SAN1 and SAP1 are set to "L" and "H", respectively, to inactivate the flip-flop FF1, and the signal ECH1 is set to "H" to be equalized. After that, the signals RV1A and RV1B become "H". Again, the signals SAN1 and SAP1 are "H",
When it becomes "L", the voltage of the node N1 is sensed and latched at time t11yc. With this, only the data circuit holding the "2" write data detects whether or not the data of the corresponding memory cell is sufficiently in the "2" write state. If the data in the memory cell is "2", the write data is changed to "0" by sensing and latching the voltage of the node N1 by the flip-flop FF1. If the data of the memory cell is not “2”, the write data is held at “2” by sensing and latching the voltage of the node N1 with the flip-flop FF1. The write data of the data circuit holding the "0", "1" or "3" write data is not changed.

Next, the selected control gate is brought to 2.5V. If the threshold of the selected memory cell is less than 2.5V, the bit line voltage will be less than 1.5V. If the threshold value of the selected memory cell is 2.5 V or more, the bit line voltage remains at 1.8 V. After this, time t12yc
Then, the signals BLCA and BLCB are set to "H", and the potentials of the bit lines are transferred to N1 and N2. Again, the signal BLC
A, BLCB become “L”, and the bit lines BLa and MO
The S capacitor Qd1, the bit line BLb and the MOS capacitor Qd2 are disconnected. After this, at time t13yc, the signal V
When RFYBAC becomes "L", a data circuit holding "0" or "1" write data, and
In the data circuit in which "2" has been sufficiently written, the p-channel MOS transistor Qp13c is "ON" and the node N1 is at VCC. The signals SAN1 and SAP1 become "L" and "H", respectively, and the flip-flop FF.
1 is inactivated, the signal ECH1 becomes "H" and is equalized. After that, the signals RV1A and RV1B become "H". After that, at time t14yc, the signals SAN1 and S
When AP1 becomes "H" and "L", respectively, the voltage of the node N1 is sensed and latched.

After this, as shown in FIG. 35, write data conversion is further performed. At time t15yc, signal BLC
A and BLCB are set to "H", the potential of the bit line is N1,
It is transferred to N2. The signals BLCA and BLCB are again set to "L", and the bit line BLa and the MOS capacitor Q
The d1, bit line BLb and the MOS capacitor Qd2 are separated. After this, at time t16yc, the signal VRFYBA1C
Becomes "H", in the data circuit in which "0" or "2" write data is held and the data circuit in which "1" write is sufficient, n-channel MOS transistor Qn2
Since C is "ON", the node N1 becomes VCC. The signals SAN2 and SAP2 are set to "L" and "H", respectively, and the flip-flop FF2 is deactivated, and the signal ECH.
2 becomes "H" and is equalized. After this, the signal R
V2A and RV2B become "H". After that, time t17yc
The signals SAN2 and SAP2 are "H" and "L", respectively.
As a result, the voltage of the node N1 is sensed and latched.

In the above embodiment, VRFY is set at time t16yc.
By setting BA1C to VCC, the node N1 of the MOS capacitor Qd1 for "0" write and "2" write is charged to be higher than the potential (1.5V) of the node N2. For example, RV2B may be set to 1.5V at t16yc. In this case, in the case of "0" write or "2" write, since the node N6C is 0V, the n-channel MOS transistor Qn33 is turned on and N2 becomes 0V. On the other hand, in the case of writing "1" or "3", the node N6C is VCC and the node N2 is 1.5V.
The channel MOS transistor Qn33 is turned off and N2 is kept at 1.5V. At the time t16yc, VRFYBA1C is set to VCC. When writing "0" and "2", the charge to N1 may be larger than the potential (0V) of N2. Therefore, the charge of N1 is, for example, about 0.5V. Low voltage is enough.

As described above, only the data circuit holding the "3" write data detects whether or not the data of the corresponding memory cell is sufficiently in the "3" write state. If the data in the memory cell is "3", the write data is changed to "0" by sensing and latching the voltage of the node N1 by the flip-flops FF1 and FF2. If the data in the memory cell is not "3", the write data is held at "3" by sensing and latching the voltage of the node N1 by the flip-flops FF1 and FF2. The write data of the data circuit holding the "0" or "1" or "2" write data is not changed.

During the write verify, the signal VRFYBB
C is "H", signal VRFYBB1C is "L", voltage Vs
Is 0V.

When all the selected memory cells have reached the desired threshold value, the data in the data circuit becomes "0" data. That is, when the writing is completed, the node N4
C and N6C become "L". By detecting this, it is possible to know whether or not all the selected memory cells have reached the desired threshold value.

FIG. 28 is a circuit diagram of a data circuit having a write completion batch detection transistor.

The end of writing is detected by, for example, the write end collective detection transistor Qn5C as shown in FIG.
And Qn6C may be used. After the verify read, VRTC is first precharged to VCC, for example. If there is even one memory cell for which writing is insufficient,
Since at least one of the nodes N4C and N6C of the data circuit is "H", the n-channel MOS transistor Qn
At least one of 5C and Qn6C is turned on, and VRTC drops from the precharge potential. When all the memory cells are sufficiently written, the data circuits 6 ^**- 0, 6 ^** -1,
..., the nodes N4C and N6C of 6 ^** -m-1 become "L".
As a result, since the n-channel MOS transistors Qn5C and Qn6C in all the data circuits are turned off, VRT
C maintains the precharge potential.

As mentioned above, the EEPRO according to the third embodiment
Although M has been described, other operations such as verify read, write, and normal read are possible.

FIG. 36 is an operation waveform diagram showing another verify read operation.

For example, the verify read may be operated as shown in the operation waveform diagram of FIG.

In the verify read shown in FIG. 36, the operation up to time t12yc is the same as the verify read shown in FIG. 35, but the operation after time t12yc is different.

At time t12yc, the signals BLCA and BLCB are set to "H", and the potentials of the bit lines are transferred to N1 and N2. When the threshold voltage of the memory cell is 2.5 V or more, the bit line BLa is 1.5 V or more, and when it is 2.5 V or less, the bit line BLb is 1.5 V or less. After that, the signals BLCA and BLCB become "L", and the bit line BLa and the MOS capacitor Qd1 are separated from the bit line BLb and the MOS capacitor Qd2. After this, when the signal VRFYBA1C becomes "H" at time t13zc,
In a data circuit that holds “0” or “2” write data and a data circuit that is sufficient for writing “1”, n
The channel MOS transistor Qn2 is "ON", and the node N1 becomes 1.5V or higher. Signal SAN2, SAP
2 becomes "L" and "H", respectively, and the flip-flop FF2 is deactivated, and the signal ECH2 becomes "H" and is equalized. After this, the signals RV2A and RV2B
Becomes "H". After that, at time t14zc, the signal SAN2,
When the SAP2 becomes "H" and "L", respectively, the voltage of the node N1 is sensed and latched.

After this, as shown in FIG. 36, conversion of write data is further performed. At time t15zc, signal B
LCA and BLCB are set to "H", and the potential of the bit line is N
1 is transferred to N2. Again, the signals BLCA, BLCB
Becomes "L", and the bit line BLa is disconnected from the MOS capacitor Qd1, and the bit line BLb is disconnected from the MOS capacitor Qd2. After this, at time t16zc, the signal VRFYBAC
Becomes "L", in the data circuit in which "0" or "1" write data is held and in the data circuit in which "2" write is sufficiently performed, p channel MOS
The transistor Qp13 is "ON" and the node N1 is at V
CC. The signals SAN1 and SAP1 become "L" and "H", respectively, and the flip-flop FF1 is inactivated, and the signal ECH1 becomes "H" and is equalized. After that, the signals RV1A and RV1B become "H". After that, at time t17zc, the signals SAN1 and SAP1 become "H" and "L", respectively, so that the voltage of the node N1 is sensed and latched. Moreover, the circuit configuration of the data circuit is not limited to the circuit configuration shown in FIG. 20, and may be another circuit configuration.

37, 38, 39 and 40 are other circuit diagrams of the data circuit, respectively.

VRFYBA of the data circuit shown in FIG.
As for the operation timing of 1C and VRFYBB1C, when the same operation timing as that of the data circuit of FIG. 28 is used (operation waveform diagram; FIGS. 29, 33, 34, 35, 36),
It is sufficient to set VCC to 0V and 0V to VCC. Note that VR
FYBAC, VRFYBBC, VRFYBA2C, VR
The timing of FYBB2C is the same as that when the data circuit of FIG. 28 is used.

Further, VRF of the data circuit shown in FIG.
YBAC, VRFYBBC, VRFYBA2C, VRF
Regarding the operation timing of YBB2C, when the data circuit of FIG. 28 is used (operation waveform diagram; FIG. 29, FIG. 33, FIG. 34, FIG. 35, FIG. 36), VCC may be 0V and 0V may be VCC. The operation timing of VRFYBA1C and VRFYBB1C is the same as that when the data circuit of FIG. 28 is used.

The VRF of the data circuit shown in FIG.
The operation timings of YBAC and VRFYBBC are shown in FIG.
When the data circuit of is used (operation waveform diagram; FIGS. 29 and 3
3, FIG. 34, FIG. 35, FIG. 36), VCC may be 0V, and 0V may be VCC. In addition, VRFYBA1C, VRF
The operation timing of YBB1C, VRFYBA2C, VRFYBB2C is the same as that when the data circuit of FIG. 28 is used.

The VRF of the data circuit shown in FIG.
The operation timings of YBA2C and VRFYBB2C are when the data circuit of FIG. 28 is used (operation waveform diagram; FIG. 29,
33, 34, 35, 36), VCC is 0V, 0
V may be set to VCC. In addition, VRFYBA1C, V
The operation timing of RFYBB1C, VRFYBAC, VRFYBBC is the same as that when the data circuit of FIG. 28 is used. Furthermore, VRFYBA2C, VRFYBB2
When C, VRFYBA1C and VRFYBB1C are set to VCC, instead of VCC, VCC + Vth (Vth
May be (threshold voltage of n-channel MOS transistor) or VCC + 2Vth. In this case, the n-channel MOS transistor can transfer the potential without causing substantial "threshold drop".

Further, in the third embodiment, at the time of read and verify read, after precharging the bit line, the non-selected control gates CG1A, CG are set.
By setting 3A and CG4A to VCC, CG1A,
The memory cells having CG3A and CG4A as gate electrodes are turned on.

For example, the non-selection control gates CG1A, CG3A, and CG4A may be set to VCC, then set to floating, and then the bit lines may be precharged. Alternatively, after precharging the bit line, the non-selected control gate may be set to VCC, and then the non-selected control gate may be floated. In this case, the non-selected control gate is in a floating state while the read current flows from the bit line to the source line through the memory cell. While the read current is flowing, the channel of the memory cell having the non-selected control gate as a gate electrode is increased from 0 V, and as a result, the potential of the non-selected control gate is higher than VCC due to capacitive coupling between the channel and the non-selected control gate. growing. When the potential of the non-selected control gate becomes higher than VCC as described above, the resistance of the memory cell having the non-selected control gate as a gate electrode becomes small, and as a result, the read current becomes large and the read speed is increased.

<Fourth Embodiment> Next, a multi-value storage NAND type EEPROM according to a fourth embodiment of the present invention will be described.

The EEPRO according to the fourth embodiment
The M has a configuration similar to that shown in FIGS. 1 and 2, like the EEPROM according to the second embodiment.

FIG. 41 is a circuit diagram of a data circuit included in the EEPROM according to the fourth embodiment of the present invention.
The data circuit shown in FIG. 41 is configured with four-value storage as an example.

The data circuit shown in FIG. 41 includes two latch circuits (first latch circuit and second latch circuit). At the time of writing, 2-bit write data is stored in these two latch circuits. When reading
The read four-valued data is stored in these two latch circuits and then output to the outside of the chip via IOA to IOD.

As shown in FIG. 41, a flip-flop FF1 and an n-channel MO formed by n-channel MOS transistors Qn21, Qn22, Qn23 and p-channel MOS transistors Qp9, Qp10, Qp11.
S transistors Qn29, Qn30, Qn31 and p-channel MOS transistors Qp16, Qp17, Qp18
The write / read data is latched in the FF2 configured by. These also operate as sense amplifiers.

The flip-flops FF1 and FF2 are
"Whether writing" 0 "or writing" 1 ",
"2" write or "3" write "is latched as write data information, and whether the memory cell holds" 0 "information or" 1 "information, "Whether information" 2 "is held or information" 3 "is held" is sensed and latched as read data information.

The data input / output lines IOA and IOB and the flip-flop FF1 are connected to the n-channel MOS transistor Q.
It is connected via n28 and Qn27. The data input / output lines IOC, IOD and the flip-flop FF2 are connected via n-channel MOS transistors Qn35, Qn36. Data input / output lines IOA, IOB, IOC, I
The OD is also connected to the data input / output buffer 5 shown in FIG. n-channel MOS transistors Qn27, Q
The gate of n28 is connected to the output of the column address decoder composed of the NAND logic circuit G3 and the inverter I5.

N-channel MOS transistor Qn26,
Qn34 is a flip-flop FF1 and FF, respectively.
The signals ECH1 and ECH2 are equalized to "H". n-channel MOS transistors Qn24, Qn
32 controls the connection between the flip-flops FF1 and FF2 and the MOS capacitor Qd1. The n-channel MOS transistors Qn25 and Qn33 control the connection between the flip-flops FF1 and FF2 and the MOS capacitor Qd2.

N-channel MOS transistor Qn50
The circuit composed of C and Qn51C has an activation signal VRF.
The YBAC changes the gate voltage of the MOS capacitor Qd1 according to the data of the flip-flop FF1. n-channel MOS transistors Qn52C, Qn
The circuit composed of 53D has an activation signal VRFYBBC.
Thus, the gate voltage of the MOS capacitor Qd2 is changed according to the data of the flip-flop FF1.
n-channel MOS transistors Qn53C, Qn54
The circuit composed of C and Qn55C has an activation signal VRF.
The YBA2C changes the gate voltage of the MOS capacitor Qd1 according to the data of the flip-flops FF1 and FF2. n channel MOS transistor Q
The circuit composed of n56C, Qn57C and Qn58C is flipped by the activation signal VRFYBB2C.
Depending on the data of the flops FF1 and FF2, the MOS
The gate voltage of the capacitor Qd2 is changed. The circuit including the n-channel MOS transistors Qn1C and Qn2C changes the gate voltage of the MOS capacitor Qd1 according to the data of the flip-flop FF2 by the activation signal VRFYBA1C. The circuit composed of the n-channel MOS transistors Qn3C and Qn4C changes the gate voltage of the MOS capacitor Qd2 according to the data of the flip-flop FF2 by the activation signal VRFYBB1C.

MOS capacitors Qd1 and Qd2 are formed of depletion type n-channel MOS transistors, and are sufficiently smaller than the bit line capacitance. n channel M
The OS transistor Qn37 is set to M by the signal PREA.
The OS capacitor Qd1 is charged to the voltage VA. The n-channel MOS transistor Qn38 charges the MOS capacitor Qd2 to the voltage VB by the signal PREB. The n-channel MOS transistors Qn39 and Qn40 control the connection between the data circuit 3 and the bit lines BLa and BLb by the signals BLCA and BLCB, respectively. The circuit composed of the n-channel MOS transistors Qn37 and Qn38 also serves as the bit line voltage control circuit.

Next, the EEPROM configured as described above
The operation of will be described with reference to an operation waveform diagram. Hereinafter, a case where the control gate CG2A is selected will be described.

<Read Operation> FIG. 42 is an operation waveform diagram showing a read operation.

As shown in FIG. 42, first, at time tw1, the voltages VA and VB are 1.8 V and 1.5 V, respectively,
Bit lines BLa and BLb are 1.8V and 1.5V, respectively
become. Next, the signals PREA and PREB become "L", and the bit lines BLa and BLb become floating.
Then, at time tw2, the selected control gate C of the block selected by the control gate / select gate drive circuit is selected.
G2A is 1V, non-selection control gates CG1A, CG3A,
CG4A and select gates SG1A and SG2A are set to VCC. If the threshold value of the selected memory cell is 1 V or less, the bit line voltage will be lower than 1.5 V. If the threshold value of the selected memory cell is 1 V or more, the bit line voltage remains at 1.8 V. After that, the signals SAN1, SAP
1 becomes "L" and "H", respectively, and the flip-flop FF1 is inactivated, and the signal ECH1 becomes "H" and is equalized. After this, at time t3w, the signal RV1
A and RV1B become "H". At time tw4, the signals SAN1 and SAP1 again become “H” and “L”, respectively, so that the voltage of the node N1 is sensed and latched. With this, "If the data of the memory cell is" 0 "or" 1 ",
Or is it "2" or "3"? "
Sensed by F1, the information is latched.

Next, it is judged whether the threshold voltage of the memory cell is 0 V or higher or 0 V or lower. At time tw5, the bit line BLa is set to 1.8V and the dummy bit line BLb is set to 1.5V.
Precharged to V and then floated. After that, the control gate selected at time tw6 is set to 0V. If the threshold value of the selected memory cell is 0V or less, the bit line voltage will be lower than 1.5V. If the threshold value of the selected memory cell is 0 V or more, the bit line voltage remains at 1.8 V. The signals SAN2 and SAP2 become "L" and "H", respectively, and the flip-flop FF2.
Are deactivated, and the signal ECH2 becomes "H" and is equalized. After this, at time tw7, the signals RV2A and RV2
B becomes "H". At time tw8, signals SAN2, SAP
2 becomes "H" and "L", respectively, so that the node N1
Are sensed and latched. Thus, "whether the data in the memory cell is" 0 ", or" 1 "or" 2 "or" 3 "" is sensed by the flip-flop FF2 and the information is latched.

FIG. 43 shows read data sensed and latched by the flip-flops FF1 and FF2 at time tw8. The potentials of the nodes N3C and N5C of the flip-flops FF1 and FF2 at this time are shown in FIG.
become that way.

Finally, it is sensed whether the data written in the memory cell is "0" or "1" or "2" or "3". Bit line BLa at time tw9
Is precharged to 1.8V, the dummy bit line BLb is precharged to 1.5V, and then floated. After that, the control gate selected at time tw10 is set to 2V. If the threshold value of the selected memory cell is 2 V or less,
The bit line voltage will be lower than 1.5V. If the threshold value of the selected memory cell is 2 V or more, the bit line voltage becomes 1.V.
It remains at 8V. VRFYBA2C becomes V at time tw11
Become CC.

As can be seen from FIG. 43, the node N5C is "High level" and the node N3C is "Low level".
(That is, the node N4C becomes "High level") only in the case of "1" data. Therefore, only in the case of "1" data, n-channel MOS transistors Qn54C, Qn
55C and Qn53C are turned on, and the node N1 becomes VCC. After that, the signals SAN2 and SAP2 become "L" and "H", respectively, and the flip-flop FF2 is deactivated, and the signal ECH2 becomes "H" and is equalized. After this, at time tw12, the signals RV2A and RV2
B becomes "H". At time tw13, signal SAN again
2 and SAP2 become "H" and "L" respectively,
The voltage of the node N1 is sensed and latched. with this,
"Whether the data in the memory cell is" 0 "or" 1 "or" 2 "or" 3 "" is sensed by the flip-flop FF2 and the information is latched.

FIG. 44 shows flip-flops FF1 and F
FIG. 9 is a diagram showing read data which F2 senses and latches.

The 2-bit data held in the flip-flops FF1 and FF2 is output to the outside of the chip when CENB is activated at time tw14.

The write operation and the write verify read operation may be performed in substantially the same manner as in the third embodiment.

Further, in the fourth embodiment, the bit line and the dummy bit line are precharged every time before a predetermined read voltage (for example, 0V, 1V, 2V) is applied to the word line.

On the other hand, in the third embodiment, at the time of read and verify read, the bit line and the dummy bit line are first precharged, and thereafter the precharge is not performed, and the read voltage of the word line is changed ( Eg 0
V to 1V, 2V). Also in the third embodiment as described above, the read voltage (for example, 0 V, 1 V
Each time (V, 2V) is applied, the bit line and the dummy bit line may be precharged as in the fourth embodiment.

Although the present invention has been described with reference to the first to fourth embodiments, the following further modifications are possible in these first to fourth embodiments.

FIG. 45 is a block diagram of an EEPROM having a modified column structure.

In the first to fourth embodiments, one data circuit 6 ^** corresponds to one bit line BL on the left and one bit line BL on the right.
One data circuit 6 ^** can be changed to a corresponding form.

As shown in FIG. 45, in an EEPROM having a modified column structure, four bit lines BLai are used.
-1~BLai-4 or for BLbi-1~BLbi-4 (i 0-3), one of the data circuit 6 ^** -0~6 ^** -m is provided.

The memory cell array 1A side will be described below as an example.

When selecting, for example, BLai-1 from the four bit lines BLai-1 to BLai-4, the signal BLC1 of the drive signals BLC1 to BLC4 for driving the transfer gate circuit 7 ^* A on the data circuit side is selected. Is set to the “H” level, and the other signals BLC2 to BLC4 are set to the “L” level.

At the same time, a drive signal B for driving the transfer gate circuit 7 ^** A on the non-selected bit line control circuit side.
Of LC1D to BLC4D, signal BLC1D is set to "L"
And set the other signals BLC2D to 4D,
Set to "H" level. Thus, only the bit lines BLi-1, which is selected is connected to the data circuit 6 ^** -0~6 ^** -m.

Thus, the selected bit line BLai is selected.
Only -1 it is connected to the data circuit 6 ^** -0~6 ^** -m, respectively the bit line BLai-2~BLai-4 that have not been selected, the unselected bit line control circuit 20-0A~20-mA Connected to. Non-selected bit line control circuit 20-0A to 20-mA
Are the unselected bit lines BLai-2 to BLai-4.
Is controlled.

Further, the memory cells integrated in the memory cell arrays 1A and 1B are not limited to the NAND type cells, and the present invention can be implemented by the cells described below.

FIG. 46 shows a memory cell array in which NOR type cells are integrated. The NOR type cell shown in FIG. 46 is connected to the bit line BL via a select gate.

FIG. 47 shows a memory cell array in which other NOR type cells are integrated. NO shown in FIG. 47
The R-type cell is directly connected to the bit line BL.

FIG. 48 shows a memory cell array in which ground array type cells are integrated. As shown in FIG. 48, the ground array type cell has bit lines BL and source lines VS arranged in parallel. The ground array type cell is one of NOR type memories.

FIG. 49 shows a memory cell array in which other ground array type cells are integrated. The ground array type cell shown in FIG. 49 has an erase gate EG used when data is erased. Further, a part of the control gate CG is of a so-called split channel type in which the channel of the memory cell transistor is overlapped.

FIG. 50 shows a memory cell array in which alternating ground array type cells are integrated. As shown in FIG. 50, the alternate ground array type cell coincides with the ground array type cell in that the bit line BL and the source line VS are arranged in parallel, but the bit line BL and the source line V are different from each other.
The difference is that S and S can be switched alternately.

FIG. 51 is a diagram showing a memory cell array in which other alternate ground array type cells are integrated. FIG.
The alternate ground array type cell shown in FIG. 1 has the same configuration as the ground array type cell shown in FIG.

FIG. 52 is a diagram showing a memory cell array in which DINOR (DIvided NOR) type cells are integrated.
As shown in FIG. 52, the DINOR type cell is configured by connecting, for example, four memory cell transistors in parallel between the bit line BL and the source line VS via a bit line side selection transistor.

FIG. 53 shows a memory cell array in which AND type cells are integrated. As shown in FIG.
The AND-type cell is configured by connecting, for example, four memory cell transistors in parallel between the bit line BL and the source line VS via the bit line side selection transistor and the source line side selection transistor.

According to the first to fourth embodiments, at the time of writing data, at least one bit line voltage control circuit charges the bit line to a desired bit line write control voltage. Accordingly, it is possible to realize a bit line voltage control circuit that applies a bit line write control voltage according to n-value write data to a bit line with a simple circuit configuration. Therefore, the scale of the column system circuit can be reduced, the chip size can be reduced, and the n-value storage EEPR at low cost
OM can be obtained.

For example, when the number of multi-valued data for latching the write data to the memory cell and the sense data for the read data from the memory cell is 2 ^m (m is a natural number of 2 or more) = n value, Since the number of flip-flop circuits can be m, the circuit scale of the column system circuit can be reduced. A judgment circuit for judging whether or not to perform writing again during verification is provided. The judgment circuit is updated to the data latch / sense amplifier circuit during the verification in accordance with the verification read result. It is configured to be controlled by the write data being written.

The number n of the multivalued data is 2
Any natural number that satisfies ^(m-1) <n≤2 ^m may be used.

[0258]

As described above, according to the present invention, it is possible to provide a non-volatile semiconductor memory device suitable for high integration because the circuit scale of the column system circuit is reduced.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a configuration of a multi-value storage NAND type EEPROM according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing a configuration of a memory cell array and a column system circuit shown in FIG.

3A and 3B are diagrams showing a case where data is read from the memory cell shown in FIG. 2. FIG. 3A shows a voltage input state, and FIG. 3B shows a voltage input waveform and a bit line. The figure which shows an output waveform.

FIG. 4 is a diagram showing a relationship between an output voltage appearing on a bit line and the number of memory cells.

5 is a circuit diagram of the data circuit shown in FIG.

FIG. 6 is an operation waveform diagram showing a read operation.

FIG. 7 is a diagram showing read data sensed and latched by a flip-flop.

FIG. 8 is a diagram showing write data latched by a flip-flop.

FIG. 9 is an operation waveform diagram showing a write operation.

FIG. 10 is an operation waveform diagram showing a verify read operation.

FIG. 11 is a diagram showing a threshold distribution of a memory cell transistor in the case of four-value storage.

FIG. 12 is a circuit diagram of a data circuit included in the EEPROM according to the second embodiment of the present invention.

FIG. 13 is an operation waveform diagram showing a read operation.

FIG. 14 is a diagram showing read data sensed and latched by a flip-flop.

FIG. 15 is a diagram showing read data sensed and latched by a flip-flop.

FIG. 16 is a schematic diagram showing an outline of a write operation.

FIG. 17 is a diagram showing write data latched by a flip-flop.

FIG. 18 is an operation waveform diagram showing a write operation (first program cycle).

FIG. 19 is an operation waveform diagram showing a verify read operation (verify read first cycle).

FIG. 20 is a diagram showing data latched by a flip-flop.

FIG. 21 is a circuit diagram of a data circuit having a write completion batch detection transistor.

FIG. 22 is an operation waveform diagram showing a write operation (second program cycle).

FIG. 23 is an operation waveform diagram showing a verify read operation (verify read second cycle).

FIG. 24 is a diagram showing data latched by a flip-flop.

FIG. 25 is an operation waveform diagram showing another verify read operation (verify read first cycle).

FIG. 26 is another circuit diagram of the data circuit.

FIG. 27 is another circuit diagram of the data circuit.

FIG. 28 is a circuit diagram of a data circuit included in the EEPROM according to the third embodiment of the present invention.

FIG. 29 is an operation waveform diagram showing a read operation.

FIG. 30 is a diagram showing read data sensed and latched by a flip-flop.

FIG. 31 is a diagram showing read data sensed and latched by a flip-flop.

FIG. 32 is a diagram showing write data latched by a flip-flop.

FIG. 33 is an operation waveform diagram showing a write operation.

FIG. 34 is an operation waveform diagram showing a verify read operation.

FIG. 35 is an operation waveform diagram showing a verify read operation.

FIG. 36 is an operation waveform diagram showing another verify read operation.

FIG. 37 is another circuit diagram of the data circuit.

FIG. 38 is another circuit diagram of the data circuit.

FIG. 39 is another circuit diagram of the data circuit.

FIG. 40 is another circuit diagram of the data circuit.

FIG. 41 is a circuit diagram of a data circuit included in the EEPROM according to the fourth embodiment of the present invention.

FIG. 42 is an operation waveform diagram showing a read operation.

FIG. 43 is a diagram showing read data sensed and latched by a flip-flop.

FIG. 44 is a diagram showing read data sensed and latched by a flip-flop.

FIG. 45 is an EE with a modified column configuration.
The block diagram of PROM.

FIG. 46 is a diagram showing a memory cell array in which NOR type cells are integrated.

FIG. 47 is a diagram showing a memory cell array in which other NOR type cells are integrated.

FIG. 48 is a diagram showing a memory cell array in which ground array type cells are integrated.

FIG. 49 is a diagram showing a memory cell array in which other ground array type cells are integrated.

FIG. 50 is a diagram showing a memory cell array in which alternating ground array type cells are integrated.

FIG. 51 is a diagram showing a memory cell array in which other alternate ground array type cells are integrated.

FIG. 52 is a diagram showing a memory cell array in which DINOR type cells are integrated.

FIG. 53 is a diagram showing a memory cell array in which AND type cells are integrated.

[Explanation of symbols]

1 ... Memory cell array, 2 ... Row related circuit, 3 ... Column related circuit, 4 ... Address buffer, 5 ... Data input / output circuit 6 ^** ... Data circuit, 7 ... Transfer gate circuit, MC ... Memory cell, M ... Memory cell Transistor, S ... Select transistor, SG ... Select gate, CG ... Control gate, BL ... Bit line. FF ... Flip-flop circuit.

Claims (15)

[Claims] 1. A memory cell array in which memory cells for storing multi-valued data are arranged in a matrix, and when writing data to the memory cells, the write data to the memory cells is latched, and the memory When the data is read from the cell, the read data from the memory cell is sensed and latched. When the number of the multi-valued data is 2 ^m (m is a natural number of 2 or more) = n value, the number is m. A bit line control circuit including a data latch / sense amplifier circuit set to the above, the data latch / sense amplifier circuit and the memory cell are connected to each other, and when the data is written to the memory cell, the data latch / sense amplifier When the write data is guided from the circuit to the memory cell and the data is read from the memory cell, the memory cell And a bit line for guiding the read data to the data latch / sense amplifier circuit, and when writing data to the memory cell, the multi-valued data is converted into the multi-valued data according to the write data latched in the data latch / sense amplifier circuit. A write control voltage according to the selected write control voltage is applied to the bit line, and whether or not the written data is in a desired data storage state after writing the data to the memory cell. A non-volatile semiconductor memory device comprising: a verify circuit for confirming whether or not. 2. A memory cell array in which memory cells for storing electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, and bit lines connected to the memory cells are provided in the memory. Threshold value detecting means for charging through the cell and outputting multi-valued data of the memory cell as a multi-valued level potential to the bit line; and a multi-valued level bit line potential charged by the threshold value detecting means And a first and second sense amplifiers for holding data to be written in the memory cells.
..., an m-th data circuit, a write verify unit that uses the threshold value detecting unit to confirm whether or not the state after the write operation of the memory cell is a storage state of desired data, Data circuit contents batch updating means for collectively updating the contents of the data circuit so that the contents of the data circuit and the state after the writing operation of the memory cells are rewritten only to the insufficiently written memory cells. A non-volatile semiconductor memory device, wherein the data update circuit refers to the contents of one data circuit. 3. A memory cell array in which memory cells storing electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, and a bit line connected to the memory cells is provided in the memory. Threshold value detecting means for charging through the cell and outputting multi-valued data of the memory cell as a multi-valued level potential to the bit line; and a multi-valued level bit line potential charged by the threshold value detecting means A sense amplifier for sensing the bit line potential by comparing the reference voltage with the first, second, and
..., an m-th data circuit, a write verify unit that uses the threshold value detecting unit to confirm whether or not the state after the write operation of the memory cell is a storage state of desired data, Data circuit contents batch updating means for collectively updating the contents of the data circuit so that the contents of the data circuit and the state after the writing operation of the memory cells are rewritten only to the insufficiently written memory cells. The data update circuit refers to the content of one data circuit, and the data circuit content batch update means is configured to detect the bit line potential as rewrite data and store the bit line potential after the write operation of the memory cell. The bit line from which the status is output and the reference potential are modified according to the contents of the data circuit. The data storage state of the circuit is held, the data circuit operates as a sense amplifier while the corrected bit line potential is held, the contents of the data circuit are collectively updated, and the write operation and the contents of the data circuit based on the contents of the data circuit are performed. A non-volatile semiconductor memory device characterized in that data is electrically written by repeatedly performing batch update until a memory cell reaches a predetermined write state. 4. The memory cell is a NAND type cell in which a plurality of memory cell transistors are connected in series, and one end of the NAND type cell is connected to a bit line via a first select gate. The other end of the NAND type cell is connected to a source line via a second select gate, and the threshold value detecting means supplies a source line voltage to the NAN.
The bit line is charged by being transferred to the bit line through the D-type cell, and the non-selected control gate voltage and the first and second select gate voltages are determined by the threshold voltage of the selected memory cell. 4. The non-volatile semiconductor memory device according to claim 2, wherein the non-selected memory cell and the first and second selection transistors are controlled so as to sufficiently enhance the voltage transfer capability. . 5. A memory cell array in which memory cells that store electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, and first and second memory cells that hold data to be written to the memory cells. ,
..., the m-th (m is a natural number satisfying 2 ^(m-1) <n≤2 ^m ) data circuit and whether or not the state after the write operation of the memory cell is a desired data storage state. A non-volatile semiconductor memory device comprising: a write verify unit for confirming. 6. A memory cell array in which memory cells for storing electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, and first and second data holding data to be written in the memory cells. ,
..., the m-th (m is a natural number satisfying 2 ^(m-1) <n≤2 ^m ) data circuit and whether or not the state after the write operation of the memory cell is a desired data storage state. A write verify unit for confirming, and a data update circuit for updating the contents of the data circuit so that the contents of the data circuit and the state after the write operation of the memory cell are rewritten only to the insufficiently written memory cells. A non-volatile semiconductor memory device, comprising: a data circuit content batch updating unit configured to refer to the content of one data circuit. 7. A memory cell array in which memory cells storing electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, and a threshold value for detecting a threshold voltage of the memory cells. Detection means and first, second, and
..., the m-th (m is a natural number satisfying 2 ^(m-1) <n≤2 ^m ) data circuit and whether or not the state after the write operation of the memory cell is a desired data storage state. Write verifying means for confirming the threshold voltage is applied to the memory cell by applying a first threshold voltage to the gate electrode of the memory cell to determine whether the memory cell is in the "1" state or It is determined whether the memory cell is in the "2" or "3" or ... "n" state, and further, by applying the second threshold voltage to the gate electrode of the memory cell, the memory cell is set to "1" or " The first, second, ..., (n−) are applied to the gate electrode of the memory cell so as to determine whether it is in the 2 ”state or in the“ 3 ”, ...,“ N ”state.
A non-volatile semiconductor memory device characterized in that the threshold detection voltage of 1) is applied. 8. A memory cell array in which memory cells that store electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, a data circuit that holds data to be written in the memory cells, A write verify unit that confirms whether or not the state after the write operation of the memory cell is a storage state of desired data, and k (k is 2 ≦ 2) at the time of the write operation for writing to n kinds of write states. First writing is performed almost simultaneously on the memory cells to be written in the write states of natural number satisfying k ≦ n, and writing is performed in the nk write states before or after the first write operation. A non-volatile semiconductor memory device characterized by writing data to a memory cell. 9. An electrically rewritable n value (where n is a value) such that the "1" state is the erased state and the "2" state, the "3" state, ..., The "n" state is the written state. A memory cell array in which memory cells for storing a natural number of 3 or more) are arranged in a matrix, a data circuit for holding data to be written in the memory cells, and a state after the write operation of the memory cells becomes a desired data storage state. A write verify means for confirming whether or not the memory cells to be written into the “3” state, ... A non-volatile semiconductor memory device characterized by performing a write operation and performing a write to a "2" state before or after the second write operation. 10. A n-value written state, a "1" state,
10. The nonvolatile semiconductor memory device according to claim 9, wherein the write threshold voltage is higher in the order of the "2" state, the "3", ... "N" state. 11. An electrically rewritable n value such that a "1" state, a "2" state, a "3" state, ..., An "n" state (n is a natural number of 3 or more) are stored states. Memory cell array in which memory cells for storing data are arranged in a matrix, a signal line for exchanging data with the memory cells, and a read data holding circuit for holding information read from the memory cells. The i-th read operation is performed to check whether the value is substantially the same as the "i" state, is equal to or more than the "i" state, or is smaller than the "i" state, holds the read data in the data holding circuit, and thereafter, During the j-th read operation for checking whether the threshold value of the memory cell is substantially the same as the "j" state, is equal to or higher than the "j" state, or is smaller than the "j" state, the data of the memory cell is output. Route potential, the after changing reference to the data held in the data holding circuit, the nonvolatile semiconductor memory device characterized by sensing the potential of the signal line. 12. A memory cell array in which memory cells storing electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, a signal line for exchanging data with the memory cells, and a memory. A data circuit for holding data to be written in the cell, and a write verify means for confirming whether or not the state after the write operation of the memory cell is a desired data storage state are output, and the write data of the memory cell is output. By referring to the potential of the signal line twice or more, the contents of the data circuit can be rewritten only from the contents of the data circuit and from the state after the writing operation of the memory cell to the insufficiently written memory cells. A non-volatile semiconductor memory device comprising: 13. A memory cell array in which memory cells storing electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, and a threshold value for detecting a threshold voltage of the memory cells. A detecting circuit; a data circuit for holding data to be written in the memory cell; and a write verifying means for confirming whether or not the state of the memory cell after the write operation is a desired data storage state. The threshold detection is performed by applying a first threshold detection voltage to the gate electrode of the memory cell so that the memory cell is in the "1" state, or "2" or "3" or ..., "n". It is determined whether the memory cell is in the "1" state or the "2" state by applying the second threshold detection voltage to the gate electrode of the memory cell. ", ...," to determine whether the n "state, first the gate electrode of the memory cell, second, ..., the (n-
By applying the threshold detection voltage of 1) and referring to the potential of the signal line that outputs the write data of the memory cell more than once, the contents of the data circuit and the state after the write operation of the memory cell are changed to the write failure. A nonvolatile semiconductor memory device, characterized in that the contents of a data circuit are updated so that rewriting is performed only for sufficient memory cells. 14. n is 4 or more,
The nonvolatile semiconductor memory device according to claim 1. 15. A memory cell array in which memory cells that store electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, and m data circuits that hold data to be written in the memory cells. And write verify means for confirming whether or not the state of the memory cell after the write operation is a desired data storage state, and the content of the data circuit and the state after the write operation of the memory cell are insufficient for writing. Data circuit content batch updating means for updating the content of the data circuit so as to rewrite only the memory cell of the data circuit, the data updating circuit refers to the content of one data circuit. A non-volatile semiconductor memory device characterized by the above.