JPH09244915A - Microcomputer and debugging supporting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a microcomputer for evaluation capable of verifying the propriety of control to a control register means for stipulating the operation of a nonvolatile memory even in the case of debugging a system by utilizing an alternate memory such as an SRAM or the like instead of the nonvolatile memory such as a flash memory. SOLUTION: This microcomputer 11 utilizable for the evaluation of the microcomputer application system detects the breach of the rules of elimination and write control by a central processing unit 19E based on the state of data set in the control register means 22E. A logic means 23 capable of outputting the detected result of the breach of the rules to the outside is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer that can be used for evaluation of a microcomputer application system, and debugging support for an emulator or the like that is applied to system debugging or program debugging of a microcomputer application system using the microcomputer. The present invention relates to a device, for example, a technique effective when applied to system debug or program debug for an application system of a microcomputer having a flash memory as a nonvolatile semiconductor memory device, and particularly to debug for operation control of a flash memory.

[0002]

2. Description of the Related Art A batch erase type EEPROM (Electrical Erasable and Programmable Read
Only memory), that is, flash memory is EEPR
Information can be rewritten by electrical erasing / writing like OM, and its memory cell can be composed of one transistor like EPROM (erasable and programmable read only memory). , A function of electrically erasing all of the memory cells or a block of memory cells collectively.
Therefore, the flash memory can rewrite the stored information in a state where it is mounted on the system (onboard), and can shorten the rewriting time by its batch erasing function. This flash memory can be used as an on-chip memory of a microcomputer as well as a single memory LSI. Such microcomputers include Hitachi single-chip microcomputers H8 / 3048 series, H8 / 3.
048F-ZTATTM Hardware Manual (1994
Published by Hitachi, Ltd. on June 3, 2014).

Software debugging and system debugging can be performed on a microcomputer application system using an emulator or the like. At this time,
An electrically erasable and writable non-volatile semiconductor memory device such as a flash memory has a limited number of times of erasing and writing. If the microcomputer runs away in system debugging or program debugging and unwanted erasing and writing operations are repeated, the life of the flash memory ends up in a short period of time. Therefore, the flash memory can be replaced with an alternative memory such as SRAM (static random access memory). Therefore, the flash memory may not be built in the evaluation microcomputer for the microcomputer having the flash memory. Also,
Even if it is built-in, the built-in flash memory can be separated from the central processing unit and its allocation address can be assigned to an alternative memory outside the microcomputer.

At this time, the control procedure of erasing and writing to the flash memory is different from the access method to the SRAM. In a flash memory, it is necessary to apply a high voltage for writing and erasing, and erasing prior to writing and prewriting before erasing are also necessary. In prelight, as described below,
A procedure of repeating operations of reading data, inverting read data, and writing inverted data is adopted for an erase target memory cell in which memory cells in an erased state and a written state are mixed. As a result, all the memory cells to be erased are aligned to the written state before the erase. Control data must be set in the control register for designating the erase operation or write operation of the flash memory according to such a rule or procedure. The data setting for the control register is performed by the central processing unit according to its operation program. Further, when performing system debugging or program debugging by substituting the flash memory with the SRAM as described above, if the operation is controlled to the alternative memory such as the SRAM by the same instruction as that for the flash memory, the operation is performed. This is different from the case for flash memory. For example, since memory cells that are erased all at once or in blocks are mixed in erased state and written state, the erased memory cells are set to the written state, and the erase target memory cells are set to the written state in advance. Alignment is done.
This process is called pre-write and is realized by reading the target data from the memory cell and writing the inverted data of the read data to the entire erase area while sequentially updating the read address. . When the inverted data for the read data is written in the flash memory, the data in the memory cells in the erased state is written. As a result, the data in the group of memory cells is unified into the written state, for example, the state of the logical value “0”. When the inverted data is written in the SRAM, the inverted data is simply written, so that S
The state of the RAM is different from that of the actual flash memory.

As described above, in debugging a system using a flash memory, it is necessary to verify whether the description of the operation program of the central processing unit that accesses the flash memory considers the access control procedure peculiar to the flash memory. I won't. In addition, the flash memory
When performing system debugging or program debugging by substituting with RAM or the like, it is necessary to consider the difference between the access control procedure peculiar to the flash memory and the access control procedure of the alternative memory such as SRAM. For example, regarding this point, the Hitachi single-chip microcomputer H8 / 3048 series, H8 / 3048F-ZT
Page 643 of the ATTM hardware manual (published by Hitachi, Ltd. on June 3, 1994) shows the case of emulating a flash memory with RAM (R
In the case of prewriting the AM area), there is a statement prompting to write H'00 (the symbol H'means that the value following this is a hexadecimal number) instead of the inverted data.

[0006]

However, in the conventional evaluation microcomputer and emulator, when the flash memory is replaced by the SRAM or the like for system debugging or program debugging, the control procedure for erasing or writing to the flash memory is The differences from the access method to the SRAM have not been fully considered. Therefore, even if the user-created programming / erasing program is debugged using the evaluation microcomputer, the emulator cannot detect incorrect settings or constraint violations in the control register, and the evaluation reliability is high. It has been found by the inventor of the present invention that in order to improve the above, it is inconvenient because each user is forced to deal with it individually, which imposes a heavy burden on the user of the microcomputer.

It is an object of the present invention to operate the nonvolatile semiconductor memory device even when system debug or program debug is performed by using an alternative memory such as SRAM instead of the nonvolatile semiconductor memory device such as flash memory. It is to provide an evaluation microcomputer equipped with a function of verifying the appropriateness of control for a register for defining the evaluation, and an evaluation support device such as an emulator.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, a control for controlling the erasing and writing of the central processing unit (19E) and the nonvolatile semiconductor memory device (12) such as a flash memory in which data can be electrically erased and written. A control register means (22E) in which data is set, and which can be used for evaluation of a microcomputer application system (42), a microcomputer (11) is based on the state of data set in the control register means. Detecting a violation of the erase and write control rule by the central processing unit,
It has a logic means (23) for outputting the detection result of this rule violation to the outside. The microcomputer corresponding to the evaluation microcomputer, that is, the microcomputer (10) mounted in the actual microcomputer application system, is the nonvolatile semiconductor memory device (1).
2) built-in. Microcomputer for evaluation (1
In 1), it does not matter whether the non-volatile semiconductor memory device is built-in or not, but at least the control register means is built-in. Whether the evaluation microcomputer (11) incorporates the nonvolatile semiconductor memory device or does not include the nonvolatile semiconductor memory device, the evaluation microcomputer is used in the evaluation such as debugging of the microcomputer application system or the operating program therefor. The computer (11)
The alternative volatile memory (14) arranged outside the microcomputer is accessed instead of the nonvolatile semiconductor memory device (12). In this access control, the control data, which is a control peculiar to the nonvolatile semiconductor memory device, is set by the central processing unit incorporated in the evaluation microcomputer by setting the data in the control register means. At this time, the logic means determines the adequacy of the control by the central processing unit for the control register means for defining the operation of the nonvolatile semiconductor memory device.

The content of the rule violation detected by the logic means is, firstly, a rule violation between setting data in the control register means, and secondly, setting of individual setting data set in the control register means. It is a rule violation for order. The control register means, for example, a rewrite mode flag (Fm) indicating a high voltage application state necessary for writing and erasing the nonvolatile semiconductor memory device, and an erasing commanding an erasing operation to the nonvolatile semiconductor memory device. It includes a bit (Be) and a write bit (Bp) for instructing a write operation to the nonvolatile semiconductor memory device.

When the logic means makes a problem of a rule violation between setting data to the control register means, the logic means, when the rewrite mode flag is disabled, enables the erase bit or the write bit. A first logic circuit 24 for detecting This makes it possible to detect a rule violation that a voltage is not applied when a write or erase operation is instructed. Further, the first logic circuit 24 can detect the state in which both the erase bit and the write bit are enabled in the enabled state of the rewrite mode flag. This makes it possible to detect a rule violation in which writing and erasing instructions that cannot be executed at the same time are issued at the same time.

When the logic means makes a problem of a rule violation for the setting order of the individual setting data set in the control register means, the logic means sets new control data in the control register means. At this time, a latch means (28) for latching the control data held by the control register means before the setting and the control data latched by the latch means are newly set in the control register means. An erase flag (29) which is enabled when control data is input and the erase bit of the newly set control data is disabled and the erase bit of the latch means is enabled, and an erase flag (29) newly set. Enable when the write bit of control data is disabled and the write bit of the latch means is enabled. And a write flag (30) which is Le. According to the above-mentioned erase flag, when the operation of disabling the erase bit is performed, if the erase flag is not enabled, it is possible to detect the rule violation that the erase bit setting operation is not performed before that. It will be possible. Further, according to the above-mentioned write flag, when the operation for disabling the write bit is performed, if the write flag is not enabled, the setting operation of the write bit preceding the write flag is not performed. It becomes possible to detect. As described above, according to the erase flag (29) and the write flag (30), it is possible to detect an abnormality in the operation for the erase bit (be) and the write bit (Bp) based on the transition states thereof.

With respect to the detection timing of the erase flag (29) and the write flag (30), the logic means synchronizes with the write flag in synchronization with the update of the address information necessary for the electrical writing or erasing. The control register means includes a second logic circuit (31) for detecting whether or not both of the erase flags are in a disabled state, and the control register means sets a control bit (Bev) for inhibiting the detection operation by the second logic circuit. Further prepare. The control bit (Bev)
Is a control bit for permitting the volatile memory (14) to perform a process corresponding to a pre-write process for preliminarily aligning memory cells in a written state in the erasing of the nonvolatile semiconductor memory device. Pre-write processing for a non-volatile semiconductor memory device is an operation of reading data, inverting read data, and writing inverted data to a memory cell to be erased in which memory cells in an erased state and a written state are mixed. -Modify-write operation) is sequentially repeated for memory addresses in the erase range. Therefore, when the erase operation is instructed, the erase bit (Be) is set to enable and the erase bit (Be) is disabled after the erase operation for each erase operation for one address that specifies the erase range. Although it will be set, before that, while sequentially updating the access address in pre-write,
The above read / modify / write operation must be repeated. As described above, when the erase operation is instructed, the address for pre-write is changed a plurality of times between the time when the erase bit is enabled and the time when the erase bit is disabled. At this time, the control bit (Bev) is enabled so that the pre-write corresponding process to the volatile memory (14) (for example, data write of all bit logical value “1” is performed instead of the inverted data write of the read data) In the period in which the read-modify-write process (which is performed) is permitted, the access address is not updated at the timing of detecting whether both the erase flag (29) and the write flag (30) are disabled. Therefore, the second logic circuit does not erroneously detect the rule violation due to the update of the access address by the pre-write handling process. After the control bit (Bev) is disabled after the prewrite operation, the change in the access address is the timing to detect whether both the erase flag (29) and the write flag (30) are disabled. It is said that Therefore, after the pre-write operation, the erase operation is actually performed and the erase bit is disabled,
When the access address is changed next, the rule violation is detected based on the erase flag. In the write operation, it is a normal control process that the write bit (Bp) is set to be enabled and the write bit (Bp) is set to be disabled after completion of the write for each write operation for one write address. Therefore, every time the access address changes, the rule violation is detected by the second logic circuit 31 based on the write flag.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION

<< Microcomputer >> FIG. 2 shows an example block diagram of a microcomputer 10 having a built-in flash memory 12. The microcomputer 10 is not particularly limited, but is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique, and is represented by a central processing unit (also referred to as a CPU). ) 19, the flash memory 12, the RAM 13, the peripheral circuit 20, and the input / output circuit 21 are commonly connected to the internal bus 18. The peripheral circuit 20 includes, but not particularly limited to, a timer counter, a serial communication interface controller, and the like.

<< Flash Memory >> FIG. 10 shows an overall block diagram of the flash memory 12. FIG.
At 0, FME is a memory enable signal for selecting an operation of the flash memory 12, RD is a read signal instructing a read operation, WR is a write signal instructing a write operation, CRS is a write selection signal of the control register 22 described later. (Simply referred to as register write selection signal). The signals are output by the central processing unit, although not particularly limited. RDY / BSY is a ready / busy signal. Vcc is a positive power supply voltage (for example, 5V) for operating the circuit, Vss is a ground voltage (for example, 0V), and Vpp is
Although not particularly limited, it is a high voltage (for example, 12 V) required for writing to the memory cell and the like. A0-Am
Is an address input terminal coupled to the address bus of the microcomputer. IO is a data input / output terminal coupled to the data bus of the microcomputer.

In the flash memory 12, each operation of data read (read), erase, write, erase verify, and write verify is externally performed by the control register 2.
It is controlled by control data (also referred to as a command) supplied to the No. 2. RWEC decrypts the command,
It is a timing controller that generates various operation control signals according to it. The control register 22 holds the command supplied from the data input / output terminal IO, the write operation of which is selected by the write selection signal CRS, and supplies the command to the timing controller RWEC.

ADB is activated by the selection level of the memory enable signal, and externally supplied address signals A0-Am or timing controller RWE.
The address buffer circuit holds the address signal output from C.

In the figure, M-ARY is a memory array in which a plurality of memory cells are arranged in a matrix.
W0 to Wx are word lines, D0 to Dn are bit lines, S0 to
Sn is a source line. As shown in FIG. 11A, the memory cell is a non-volatile insulated gate field effect transistor having a two-layer gate structure formed in a substrate region 1 such as a P-type silicon substrate or a P-type well region. Memory cell transistor. That is, this non-volatile memory cell transistor (also simply called a memory cell)
Is a floating gate electrode 3 formed on the gate insulating film 2, a control gate electrode 5 formed on the floating gate electrode 3 via an interphase insulating film 4, and separated from each other in the substrate region 1. A source electrode 6 and a drain electrode 7 that are provided and have a portion overlapping the floating gate electrode 3 with the gate insulating film 2 interposed therebetween are provided. The control gate electrode 5 of the memory cell transistor is connected to the corresponding word line, the source electrode 6 is connected to the corresponding source line, and the drain electrode 7 is connected to the corresponding bit line.

Writing to the memory cell is performed by the drain electrode 7
The hot electrons are generated in the vicinity of and are injected into the floating gate electrode 3. For example, the control gate electrode 5 of the memory cell has a high voltage Vpp (for example, 12V).
Is applied to the source electrode 6 and the substrate region 1 and the ground voltage V
ss (for example, 0 V) is applied, the power supply voltage Vcc (for example, 5 V) is applied to the drain electrode 7 of the memory cell in which programming is selected, and the ground voltage Vss (for example, for drain electrode 7 of the memory cell MC in which programming is not selected (for example, 0V) is applied.

Erasing of the memory cell is performed by extracting electrons from the floating gate electrode 3 to the source electrode 6 by a tunnel current. For example, the source electrode 6 of the memory cell has a voltage (for example, 4V) slightly lower than the power supply voltage Vcc,
The drain electrode 7 is set to open (floating), the substrate region 1 is set to the ground voltage Vss (eg, 0V), and the negative voltage Vppn (eg, −10V) is applied to the control gate electrode 5 of the memory cell MC selected for erasing. The same voltage (4V) as that of the source electrode 6 is applied to the control gate electrode 5 of the non-erased memory cell as the erase blocking voltage. As a result, a negative voltage V of −10V is applied to the control gate electrode.
In the memory cell to which ppn is applied and 4 V is applied to the source electrode, electrons accumulated in the floating gate electrode are extracted to the source electrode by an FN (Fowler Nordheim) tunnel.

As shown in FIG. 11B, by the write operation, the threshold voltage seen from the control gate electrode 5 of the memory cell is made higher than that of the erased memory cell in which the write operation is not performed. The threshold voltage of the memory cell is set to a positive voltage level in both the write and erase states. That is, the threshold voltage of the memory cell in the written state is raised and the threshold voltage of the memory cell in the erased state is lowered with respect to the word line selection level given from the word line to the control gate electrode 5. By having such a relationship between both threshold voltages and the word line selection level, it is possible to configure a memory cell with one transistor without employing a selection transistor.

In the data read from the memory cell, the control gate electrode of the memory cell selected for the read operation is set to the power supply voltage Vcc (for example, 5V). Floating gate electrode 3
In the case of the memory cell in the written state in which the negative charge is stored in, the channel current does not flow even if the control gate electrode 5 is set to the power supply voltage Vcc. On the other hand, in the case of an erased memory cell in which no charge is stored, a channel current flows. The sense amplifier detects this difference in current, converts current information into voltage information, and outputs a logical value of read data.

In FIG. 10, SLD is a source line driver circuit for controlling the levels of the source lines S0 to Sn according to the various operations described above, and as described above, the source line S0 is selected depending on the operating states of writing, erasing and reading. ~ Sn
The drive voltages for the two are different, and the instruction is given by the control signal φE from the timing controller RWEC. The control signal φE is activated in response to the erase operation,
When it is activated, the source line driver circuit SLD
Applies 4V to the source lines S0 to Sn. Control signal φE
Source line driver circuit SLD applies ground voltage Vss to source lines S0-Sn. The voltage of 4V can be formed, for example, by lowering the power supply voltage Vdd.

In FIG. 10, NEG is the negative voltage Vpp.
A booster circuit as a voltage conversion circuit that forms n, and uses a known charge pump circuit or the like to supply the power supply voltage Vd.
The voltage d is boosted to the negative voltage Vppn.

In FIG. 10, XDC is a row address decoder, which decodes a row address signal among the address signals output from the address buffer circuit ADB, and outputs 1 designated by the row address signal.
A word line selection signal for selecting one word line is formed.
The word line selection signal is supplied to the word driver WDV. The word driver WDV drives the word line to be selected to a predetermined selection level by the word line selection signal, and sets the non-selected word line to the non-selection level. The selection level and non-selection level at that time are as described above,
The instruction is made different depending on each operation state of erase and read, and the instruction is a control signal φ from the timing controller RWEC.
It is designated by E, φW, and φR. That is, when the control signal φW is activated in response to the write instruction, the word driver WDV drives the word line to be selected by the word line selection signal to the high voltage Vpp and the other word lines to the ground voltage Vss. . When the control signal φE is activated in response to the instruction of the erase operation, the word driver WDV sets the word line whose erase operation is selected by the word line selection signal to the negative voltage Vppn and the other word lines to 4V. Drive to a proper erase blocking voltage. When the control signal φR is activated in response to a read (write verify, erase verify) instruction, the word driver WDV causes the word line to be selected by the word line selection signal to the power supply voltage Vd.
At d, the other word lines are driven to the ground voltage Vss.
The voltage of 4V is not particularly limited, but may be the power supply voltage Vc.
It is generated by stepping down c.

YDC is a column address decoder,
A column address signal of the address signals output from the address latch ADB is decoded to form a bit line selection signal according to the address signal. YG is
A column switch circuit, which receives the bit line selection signal, selects a bit line designated by the column address signal among the plurality of bit lines D0 to Dn in the memory array, and reads the common data line CDR. , Or a large number of column switches (not shown) that conduct to the common data line CDW for writing. Common data line C for writing
The output terminal of the write latch circuit WL is coupled to DW. The read common data line CDR is provided with a sense amplifier circuit SA. The column switch circuit YG
Turns off all the column switches so that all the bit lines D0 to Dx are floated when the control signal φE is activated in response to the instruction of the erase operation.

Although not particularly limited, the write latch circuit WL holds a write data signal from the data input / output buffer or the timing controller RWEC, and at the time of writing, a common bit corresponding to the logical value "0" of the held data. 5 via the signal line of the data line CDW
A write voltage such as V is supplied to the drain electrode of the memory cell, and a voltage such as 0 V is supplied to the drain electrode of the memory cell through the signal line of the common data line CDW corresponding to the bit having the logical value "1". Supply.

The sense amplifier circuit SA amplifies a read signal applied to the common data line CDR in the read operation, erase verify or write verify. The read data amplified by the read operation is output to the outside via the data input / output buffer DIOB. The data amplified by the sense amplifier circuit SA in the verify operation is supplied to the timing controller RWEC, and it is determined whether or not a required memory cell has a prescribed threshold voltage by the erase or write operation.

The control register 22 has a data input / output terminal I.
Hold the command input from O. The held command is supplied to the timing controller RWEC, and the timing controller RWEC reads the flash memory 12 according to the content of the command.
Controls operations such as erase / erase verify or write / write verify. The control signals φE, φW, and φR are activated / deactivated according to the operation instructed by such a command.

The timing controller RWEC is
Although the control information latched in the control register 22 is decoded to control erase and write operations, an address counter ACOUNT as an address generation circuit is provided for erase and erase verify for a desired address range.
The address counter ACOUNT can preset the address signals A0 to Am supplied from the outside. The address thus preset is set as the top address of the address range to be erased. The timing controller RWEC grasps the end of the erase range as the increment number of the address counter ACUNT according to information such as the number of erase words designated via the control register CREG, for example. From the viewpoint of preventing over-erase, etc., the application time of the erase voltage is made relatively short, the read operation for erase verify is performed each time, and the erase and verify are repeated until the specified threshold voltage is reached. Has been adopted. At this time, when advancing the word line to be erased to the next word line, the least significant bit of the bits corresponding to the row dress signal of the address counter ACOUNT is incremented to the next value. When reading the next data in the verification, the least significant bit of the bits corresponding to the column address signal is incremented to the next value. The timing controller RWEC controls the ready / busy signal to a high level during a write or erase operation to notify the bus master such as a microcomputer that the operation is in progress. Bus master is ready / busy signal RDY /
BSY detects a ready state in which it is hibernated, issues a command to the flash memory 12, and performs a read operation.

<< Evaluation Microcomputer >> In debugging a microcomputer application system using the microcomputer 10, the evaluation microcomputer shown in FIG. 1 (also referred to as evaluation chip) is used instead of the microcomputer 10. 11 is used for proxy control of the application system. Evaluation microcomputer 11 corresponding to the microcomputer 10
The central processing unit 19E having at least the same function as that of the central processing unit 19 of the microcomputer 10.
Is mounted. In this example, the evaluation microcomputer 11 includes the peripheral circuit 2 together with the central processing unit 19E.
0E, RAM 13E, and input / output circuit 21E are mounted, and they are coupled to internal bus 18E. The peripheral circuit 20E, the RAM 13E, the input / output circuit 21E, and the internal bus 18E are the peripheral circuit 20, the RAM 13, and the input / output circuit 21 installed in the microcomputer 10.
Has the same function as each of. At this time, since the evaluation microcomputer 11 is not equipped with the flash memory 12, an alternative memory 14 such as an SRAM provided in the emulator is used for system debugging such as emulation or system evaluation.
Will replace the flash memory 12. In FIG. 1, the evaluation microcomputer 11 is not particularly limited, but an emulator interface 15 and a bus switch 17 are added as compared with the microcomputer 10. The emulator interface 15 is a circuit for interfacing the internal state of the evaluation microcomputer 11 with the emulator side. The bus switch 17 connects the RAM 13E to the internal bus 18E according to the operation mode set in the evaluation microcomputer 11.
It is a circuit to disconnect from. For example, such an operation mode is called an evaluation chip mode, and is set from an external terminal of the evaluation microcomputer 11 or by a value of a control register included in the CPU (central processing unit) 19E. When the evaluation chip mode is set, the addresses of the flash memory 12 and the RAM 13 are mapped in the replacement memory 14. As a result, when the CPU 19E accesses the flash memory 12 and the RAM 13 during emulation,
Actually, the alternative memory 14 is accessed. Even in the evaluation chip mode, depending on the setting of the control register included in the central processing unit 19E, the internal bus 18
Bus switch 1 so that the RAM 13 is not separated from
7 can be controlled. Although the evaluation microcomputer 11 does not include the flash memory 12 in FIG. 1, the evaluation microcomputer 11 may also include a flash memory. In that case, between the internal bus 18E and the flash memory,
A bus switch controlled to be turned off in the ever-chip mode is arranged so that the flash memory can be replaced by the external alternative memory 14 during emulation.

Microcomputer 11 for evaluation
Even if the flash memory 12 itself is not built in, the control register 22E corresponding to the control register 22 described in FIG. 10 is provided. When the evaluation microcomputer 11 is set to the evaluation chip mode during emulation, and the CPU 19E executes its operation program (user program to be evaluated) to control access to the flash memory, writing of the command or control data is not possible. This is performed for the control register 22E. That is, the address of the flash memory is mapped in the alternative memory 14, but the control register 2
As in the case of the microcomputer 10, the address of 2E is not changed in the state assigned to the internal address of the microcomputer 11. In short, the address of the storage area of the memory array M-ARY is mapped in the alternative memory 14. Further, the microcomputer 11 for evaluation evaluates whether there is an abnormality in the control procedure such as setting of control data to the control register 22E when access control of the flash memory is performed according to the operation program of the CPU 19E during system debugging or program debugging. Support circuit 23 used to
Have in hardware.

<< Overall Configuration of Emulator >> Before describing the details of the support circuit 23, an example of the emulator will be described with reference to FIG. In FIG. 3, reference numeral 40 denotes an emulator, one end of which is connected to the user side interface (input / output circuit 21E of FIG. 1) of the evaluation microcomputer 11 and the other end of the interface cable 41 is a user system (microcomputer application system). ) 42 is connected to the IC socket of the target microcomputer (corresponding to the microcomputer 10) to be mounted on the device 42. The microcomputer 11 as an emulation microcomputer controls the user system 42 on behalf of the user through the interface cable 41. Also, the evaluation microcomputer 1
1 is connected to the emulation bus 44. The microcomputer 11 connects to the emulation bus 44,
The same control information as the various control information to the user system is output to contribute to the evaluation, and the microcomputer 11 may receive the control information from the emulation bus 44 prior to the emulation.

The emulation bus 44 is not particularly limited, but the alternative memory 14 and the map control circuit 4 are provided.
5, break control circuit 46, PC generation circuit 47, emulation memory 49, trace memory 50, parallel access control circuit 51, and user interface 52
Is connected. The alternative memory 14 is a memory such as an SRAM for substituting the memory built in the user system 42 or the target microcomputer.
For example, when the target microcomputer has a built-in flash memory, the alternative memory 14 replaces the flash memory. The map control circuit 45 is a circuit that sets the address arrangement of the alternative memory 14 in a programmable manner. For example, when the evaluation chip mode is set in the evaluation microcomputer 11 and the alternative memory 14 replaces the flash memory 12, the original address arrangement of the flash memory 12 to be replaced is set in the map control circuit 45, and the user The flash memory access by the program is actually an access to the alternative memory 14. The break control circuit 46 monitors the control state of the evaluation microcomputer 11 or the state of the emulation bus 44, and outputs an emulator-dedicated interrupt when the state reaches a preset state. This is a circuit for stopping the execution of the user program and for making a transition (break) to the execution state of the emulation program (control program for controlling emulation). The PC generation circuit 47 is a circuit for externally reproducing the value of the program counter included in the evaluation microcomputer 11, and the address of the instruction actually executed (program counter The value of the flag) is stored in the coverage memory 48. For example, the coverage memory uses a memory of x1 configuration (the number of data input / output bits is 1 bit). For coverage, all the data in the coverage memory is set to either "1" or "0", and the inverted data is written only at the place where the value of the PC (program counter) that occurred even once exists. . That is, the memory address input becomes PC. If the user wants to see the coverage, he / she can refer to the entire contents of the memory and find that the address (PC) where the data is inverted is the executed program address. The emulation memory 49 is a memory in which predetermined control information necessary for proxy control by the evaluation microcomputer 11 is stored. Trace memory 5
Reference numeral 0 is a circuit for real-time trace that sequentially stores the address and data given to the emulation bus 44 and further control information in synchronization with the bus cycle of the emulation bus 44. Parallel access control circuit 51
Is a circuit for enabling the emulator control microcomputer 53 to access the alternative memory 14 in parallel with the execution of instructions by the evaluation microcomputer 11.
The user interface 52 is the interface cable 4
This is a circuit for interfacing the emulator 40 with the user system 42 using a probe other than 1.

The map control circuit 45, the break control circuit 46, the PC generation circuit 47, the coverage memory 48, the trace memory 50, the parallel access control circuit 51, and the user interface 52 are connected to a control bus 54 and an emulator control microcomputer. 53
The operation is controlled by the emulator control circuit 55, and the contents held in those circuit blocks are referred to. Further, the control bus 54 is connected to a system development device such as a personal computer, that is, a host computer 57 via a host computer interface 56. The emulator 40 configured as described above stores the user program downloaded from the host computer 57 in the alternative memory 14, for example,
When the evaluation microcomputer 11 reads and executes it, the microcomputer 11 controls the user system 42 on behalf of the user. Control information such as an execution start address and a breakpoint of the user program is set by the emulator control microcomputer 53 or the emulator control circuit 55 according to an instruction from the host computer 57. According to this setting, when the microcomputer 11 executes the user program, it monitors instruction addresses, instruction codes, data, various control signals, and the like, and samples necessary information to debug the user system or user program. To help.

<< First Configuration Example Specialized in Evaluation of Control for Flash Memory >> Next, when the access control of the flash memory is performed according to a user program at the time of program debugging using an emulator,
The support circuit 23 specialized for evaluating whether or not a control procedure such as setting of control data for the control register 22E is violated will be described in detail.

FIG. 4 shows an evaluation microcomputer 11 mainly composed of the control register 22E and the support circuit 23.
Is shown. The control register 22E instructs a rewrite mode flag Fm indicating a high voltage Vpp application state necessary for erasing the flash memory, an erase bit Be for instructing the flash memory to perform an erase operation, and a write operation for the flash memory. Write bit Bp to be executed. The rewrite mode flag Fm is set to a set state (enable) when the high voltage Vpp for erasing / writing is supplied. Although the high voltage Vpp is directly supplied to the control register 22 in FIG. 4, the rewrite mode flag Fm is actually received by the detection output of the high voltage detection circuit that detects the application of the high voltage Vpp. Set. The write bit Bp and the erase bit Be are set in the control register 19E by the CPU 1 by the write control signal CRS.
By being selected by 9E, it is set from the CPU 19E via the internal bus 18E.

The rewrite mode flag Fn, the write bit Bp, and the erase bit Be are the flash memory 12
It is also included in the control register 22 of. FIG. 6 shows an example of a rule violation with respect to the set states of the rewrite mode flag Fm, the write bit Bp, and the erase bit Be. That is, when the writing instruction (Bp = 1) or the erasing instruction (Be = 1) is performed in the state (Fm = 0) where the high voltage Vpp for writing / erasing is not applied, Even if the high voltage Vpp is applied (Fm =
1), write instruction (Bp = 1) and erase instruction (Be = 1)
If the flash memory 12 and the flash memory 12 are simultaneously executed, the flash memory cannot operate normally, and such a setting state of the control register 22 is regarded as a rule violation (setting violation) when the flash memory 12 is used.

The support circuit 23 includes a first logic circuit 24 for detecting a setting violation state shown in FIG. 6 and an error flag 25 set to a set state when the first logic circuit 24 detects a setting violation. I have it. The first logic circuit 24, when the rewrite mode flag Fm is in a disabled state, erases the erase bit Be or the write bit B.
In the state where p is enabled and the rewrite mode flag Fm is enabled, the erase bit Be
And write bit Bp are both enabled. When the CPU 19E sets the write bit Bp or the erase bit Be in the control register 22E via the internal bus 18E, the first logic circuit 24 outputs the write bit Bp and the erase bit Be from the internal bus 18E.
Take in.

FIG. 5 shows an example of the first logic circuit 24. The error detection signal ERR1 is a signal that is set to a high level (logical value “1”) when there is a setting violation.
The first logic circuit 24 includes NOR gates NOR1 and NOR2.
And NAND gates NAND1, NAND2, NAND3
And inverters INV1 and INV2. Since the output of the NAND gate NAND3 is fixed to the low level when the register write selection signal CRS is set to the low level (logical value "0") which is the disable level, the error signal ERR1 indicates the rewrite mode flag Fm, erase. It is forced to a low level (error non-detection level) regardless of the states of the bit Be and the write bit Bp. Rewrite mode flag Fm, erase bit Be,
When any of the write bits Bp is at the low level (disabled), the output of the NOR gate NOR1 is fixed at the high level and the output of the NAND gate NAND2 is fixed at the high level. Therefore, the error signal ERR1 is the register write selection signal. Forced to low level regardless of CRS status. When the rewrite mode flag Fm is disabled (logical value “0”), the NAND gate NAND
The output of 2 is fixed to the high level, and in this state, when at least one of the erase bit Be and the write bit Bp is enabled (logical value "1"), the output of the NOR gate NOR1 is set to the low level. At this time, if the register write selection signal CRS is enabled, the error detection signal ERR1 is set to a high level, whereby a setting violation is detected. Further, when the rewrite mode flag Fm is enabled (logical value “1”), the NAND gate N
The output of the AND2 is determined by the output level of the NAND gate NAND1, and in this state, when both the erase bit Be and the write bit Bp are enabled (logical value "1"), the output of the NOR gate NOR1 is low level. , The output of the NAND gate NAND2 is set to the high level. At this time, if the register write selection signal CRS is enabled, the error detection signal ERR1 is set to the high level, whereby the setting violation is detected.

The error flag 25 is assigned to 1 bit of a register accessible by the CPU 19E. The error flag 25 is set by the high level of the error detection signal ERR1. CPU19E
Refers to the error flag 15 at a predetermined timing,
The fact that the setting violation has occurred can be recognized from the fact that it is in the set state. The error flag 25 is referred to, for example, when the execution of the evaluation target user program by the CPU 19E is temporarily interrupted (break) in the system debug or software debug by the emulator, the CPU 19E executes the control program for evaluation control. Refer to.

<< Second Configuration Example Specialized in Evaluation of Control for Flash Memory >> FIG. 7 shows another example of the support circuit 23. In this example, the error signal ERR1
Is provided to the outside of the microcomputer 11 directly. If the error signal ERR1 output from the output terminal 26 is, for example, one of the break conditions, the evaluation microcomputer 1 is synchronized with the timing when the error signal ERR1 is enabled.
It is possible to break 1 and display a setting violation warning on the display of the host computer 57.

<< Third Configuration Example Specialized in Evaluation of Control for Flash Memory >> FIG. 8 shows still another example of the support circuit 23. In this example, the control register 22E
Includes a rewrite mode flag Fm, a write bit Bp,
In addition to the erase bit Be and the erase bit Be, an erase confirmation bit Bev is shown. The erase confirmation bit Bev is a control bit that does not exist in a normal flash memory, is a control bit in consideration of performing prewrite processing on the alternative memory 14, and is set by the CPU 19E. That is, in the pre-write process, the target data is read from the memory cell, the read data is logically inverted, and the inverted data is written to the read address. This is a process for aligning the state of the memory cells in the area to be erased with the written state to prevent the over-erased state. In pre-write verify, read data after pre-write is all bit write state (logical value "0")
If so, it is determined to be normal. Logical value "1" even with 1 bit
Is present, it is determined that the pre-write is abnormal, and in that case, the process branches to error processing specified by the user program, for example. After pre-writing, erasing is performed on the entire surface or in blocks. After erasing, desired data is written in the memory cell in that area. As described above, the pre-write includes read (data read), modify (read data inversion), and write (reverse data write) operations for each erase address. For example, if the byte data read from the flash memory is H'55, the inverted data H'A
By writing A to the same address, the data at that address becomes H'00. When the same read, modify and write operations are performed on the RAM, the contents of the memory are set to H'AA, which is different from the case of the flash memory. Therefore, in the case of performing the pre-write process using the alternative memory 14, it is not consistent unless the data of all bit logical value "1" is written instead of writing the inverted data. Erase confirmation bit Bev
Is a bit that indicates that such data writing of all-bit logical value "1" is permitted for pre-writing in the erase operation, by its enable (logical value "1") state.

The support circuit 23 shown in FIG. 8 includes the first logic circuit 24 and the error flag 25 described in the above embodiment, and further includes the latch circuit 28, the erase flag 29, the write flag 30, and the second logic circuit 31. , And the error flag 32
Is provided. Further, according to the example of FIG. 8, when the evaluation microcomputer 11 accesses the alternative memory 14 as a flash memory, the alternative memory 1 receives the address signal and the data via the emulator interface 15.
4, and an address latch circuit 33 and a data latch circuit 34 for supplying the data to the memory device 4.

The latch circuit 28, when new control data is set in the control register 22E by the register write control signal CRS, writes the write bit Bp and the erase bit held in the control register 22E before the setting. Latch Be. The erase flag 29 is set (enable state) when the newly set erase bit Be is disabled and the erase bit of the latch circuit 28 is enabled. Write flag 30
Are set (enabled) when the newly set write bit Bp is disabled and the write bit of the latch circuit 28 is enabled.
The above operations of the erase flag 29 and the write flag 30 are performed in synchronization with the write instruction of the register write control signal CRS. According to the erase flag 29, when the operation for disabling the erase bit Be is performed, unless the erase flag 29 is enabled, the erase bit setting operation preceding the erase flag 29 is not performed. Can be detected. According to the write flag 30, when the write bit Bp is disabled and the write flag 30 is not enabled, the write bit setting operation prior to the write flag 30 is not performed. Rule violations are made detectable. In this way, the erase flag 29 and the write flag 30 make it possible to detect an abnormality in the operation for the erase flag be and the write bit Bp based on the transition states thereof.

The second logic circuit 31 detects a control violation or a rule violation based on the erase flag 29 and the write flag 30, and the address information or data necessary for the electrical writing or erasing. When the information is updated, it detects that both the erase flag and the write flag are disabled. Erase flag 2
When it is detected that both 9 and the write flag 30 are disabled, the error signal ERR2 is enabled, which causes the error flag 32 to be set. CPU 19E has an error flag 25
Similarly to the above, the status of the error flag 32 is changed to the internal bus 18E
Can be read via. The CPU 1 outputs address information or data information required for the electrical writing or erasing.
The timing of updating by 9E is detected by the state in which the selection signals of the latch circuits 33 and 35 included in the control bus CBUS of the internal bus 18E including the data bus DBUS, the address bus ABUS, and the control bus CBUS are set to the selection level. . Such timing may be detected by decoding the address of the address bus ABUS.

Regarding the detection timing of the erase flag 29 and the write flag 30, the second logic circuit 31 synchronizes with the update of the address information necessary for the electrical writing or erasing, and the write flag 30. It is detected whether both the erase flag 29 and the erase flag 29 are in the disabled state. However, when the erase confirmation bit Bev is enabled, the detection operation is not performed. In other words, the erase confirmation bit Bev is written to the second logic circuit 31 in synchronization with the update of the address information and the data information and the write flag 3
It is regarded as a control bit that suppresses the operation of detecting whether both 0 and the erase flag 29 are in the disabled state by the enable constant. Erase confirmation bit Bev
Is a control bit for permitting the process for the alternative memory 14, which corresponds to the pre-write process for preliminarily aligning the memory cells in the written state in the erase of the flash memory. As described above, the pre-write process for the flash memory is a process in which the read-modify-write operation is sequentially repeated for the memory addresses in the erase range. Therefore, when the erase operation is instructed, the erase bit Be is set to enable and the erase bit Be is set to disabled after the erase is completed for each erase operation for one address designating the erase range. However, before that, the read / write
You must repeat the modify write operation. As described above, when the erase operation is instructed, the address for pre-write is changed a plurality of times between the time when the erase bit Be is enabled and the time when the erase bit Be is disabled. At this time, the pre-write corresponding processing to the alternative memory 14 which is permitted by the erase confirmation bit Bev being enabled (instead of the inverted data write of the read data, for example, all bit logical value "1" is set). During the period when the read-modify-write process (where data is written) is permitted, the update of the access address is not performed at the timing of detecting whether both the erase flag 29 and the write flag 30 are disabled. The second logic circuit 31 does not erroneously detect a rule violation due to the update of the access address by the pre-write handling process. After the control bit Bev is disabled after the pre-write support process, the change in the access address set in the address latch circuit 33 detects whether both the erase flag 29 and the write flag 30 are disabled. It is time to do it. Therefore, after the pre-write operation, the erase operation is actually performed, and the erase bit Be
Is disabled and then the access address is changed, detection of the rule violation based on the erase flag 29 is performed. In the write operation, the write bit Bp is set for each write operation for one write address.
Is set to be enabled and the process of setting the write bit Bp to be disabled after the writing is completed is a normal control process. Therefore, the second logic based on the write flag 30 is set every time the access address changes. The rule violation is detected by the circuit 31.

The write flag 30 and the erase flag 29 are reset after every detection operation by the second logic circuit 31.

Next, an example of the operation of the second logic circuit 31 will be described. When rewriting the data in the flash memory in the debugging using the evaluation microcomputer, the CPU 19E determines the data and the access address to be erased or written when the rewrite mode flag Fm is enabled. Bus DBU
Output to S and address bus ABUS. The bus control information required at that time is sent from the CPU 19E to the control bus CB.
Output to US. At this time, the access data and address are held in the latch circuits 33 and 35. At this time, the CPU 19E executes an instruction to set the write bit Bp, and when the write bit Bp of the control register 22E is enabled by this, for example, the address latch circuit 33 and the data latch circuit 35.
The alternative memory 14 is accessed via the emulator interface 15 based on the contents of

The second logic circuit 31 has an address latch circuit 33 and a data latch circuit 34 when repeatedly erasing or writing to the flash memory.
It is used to determine whether or not the alternative memory 14 is actually accessed using the information held in. For example, as shown in (# 6) of FIG. 9, after the write bit Bp is enabled (logical value “1”) and the write operation is performed, the write bit Bp is disabled (logical value “0”). ”), At this time, referring to the value of the previous write bit held by the latch circuit 28, if it is in the enabled state,
The write flag is enabled (# 7) to indicate that the operation on the control register of the flash memory has been normally performed in order to rewrite the data in the flash memory. The same applies to erasing. As shown in (# 2) of FIG. 9, after the erase bit Be is enabled and the erase operation is performed, the erase bit Be must be disabled. At this time, the latch circuit 28 is If the value of the erase bit just before being held is referenced and it is in the enabled state, it indicates that the operation to the control register 22E of the flash memory has been normally performed to erase the data of the flash memory. The erase flag 29 is enabled (# 3). The timing at which the second logic circuit 31 refers to the erase flag 29 and the write flag 30 is synchronized with the timing at which the CPU 19E updates the address signal for accessing the flash memory. At this timing,
When both the write flag 30 and the erase flag 29 are disabled, it is determined that the information currently held by the address latch circuit and the data latch circuit has not been used for writing or erasing, The error flag 32 is set. If at least one of the write flag and the erase flag is in the enabled state, it means that the information currently held by the address latch circuit 33 and the data latch circuit 34 has been used for writing or erasing.
The error flag 32 is not set. The second logic circuit 31 controls the timing at which the address latch circuit 33 or the data latch circuit 34 is updated on the control bus CB.
The write flag 30 is initialized or reset from the enabled state to the disabled state by detecting it from the US information. The erase flag 29 is initialized by the erase confirmation bit B.
It is suppressed while ev is enabled.

The effects obtained by each of the above embodiments are as follows. [1] The microcomputer 11, which can be used for evaluating the microcomputer application system 42, determines whether the erasing and writing control rule by the central processing unit 19E is violated based on the state of the data set in the control register 22E. It has a support circuit 23 as a logical means for detecting and outputting the detection result of this rule violation to the outside. A microcomputer corresponding to the evaluation microcomputer 11, that is, a microcomputer 10 mounted in an actual microcomputer application system has the flash memory 12 built therein. The evaluation microcomputer 11 may or may not include the flash memory 12,
At least the control register 22E is incorporated. Whether the microcomputer 11 for evaluation includes the flash memory 12 or not, the microcomputer 11 for evaluation, in evaluation such as debugging of a microcomputer application system or an operation program therefor, The substitute memory 14 arranged outside the microcomputer 11 is accessed instead of the non-species memory 12. In this access control, the control data, which is a unique control for the flash memory 12, is set by the central processing unit 19E incorporated in the evaluation microcomputer 11 setting the data in the control register 22E. At this time, the support circuit 23 can judge the adequacy of the control by the central processing unit 19E for the control register 2E for defining the operation of the flash memory 12.

[2] When the write or erase operation is instructed by the first logic circuit 24 which detects the enable state of the erase bit Be or the write bit Bp in the disabled state of the rewrite mode flag Fm,
It becomes possible to detect a rule violation that the high voltage Vpp is not applied. Further, the first logic circuit 24 can detect a state in which both the erase bit Be and the write bit Bp are enabled in the enabled state of the rewrite mode flag Fm. This makes it possible to detect a rule violation in which writing and erasing instructions that cannot be executed at the same time are issued at the same time. As described above, the first logic circuit 24 can detect the rule violation between the setting data for the control register 2E.

[3] According to the erase flag 29, if the erase flag 29 is not enabled when the operation of disabling the erase bit Be is performed, the setting operation of the erase bit Be prior to it is performed. It is possible to detect the violation of the rule that it is not. According to the write flag 30, when the write bit Bp is disabled and the write flag 30 is not enabled, the write bit setting operation prior to the write flag 30 is not performed. Enables detection of rule violations. Thus, referring to the erase flag 29 and the write flag 30, the erase bit be and the write bit Bp
It is possible to detect an operation violation against it based on the transition state of.

[4] At the detection timing of the erase flag 29 and the write flag 30, both the write flag 30 and the erase flag 29 are synchronized with the update of the address information necessary for the electrical writing or erasing. The control register 22E includes a second logic circuit 31 that detects whether the second logic circuit 3 is disabled or not.
A control bit Bev for suppressing the detection operation by 1 is further provided. As a result, during the period in which the pre-write support process for the flash memory 12 is enabled by enabling the control bit Bev,
Since the update of the access address is not performed at the timing of detecting whether both the erase flag 29 and the write flag 30 are disabled, the update of the access address by the pre-write handling process causes the second logic circuit 31 to mistakenly. It does not detect any rule violations. After the control bit Bev is disabled after the prewrite operation, the change of the access address is the timing to detect whether both the erase flag 29 and the write flag 30 are disabled. Therefore, when the erase operation is actually performed after the pre-write operation, the erase bit Be is disabled, and then the access address is changed, the violation of the rule is detected based on the erase flag 29. You can In the write operation, for each write operation for one write address,
Since it is a normal control process to set the write bit Bp to be enabled and to set the write bit Bp to be disabled after the writing is completed, the first control based on the write flag 30 is performed every time the access address changes. It is possible to detect the rule violation by the second logic circuit 31.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the circuit module included in the microcomputer or the emulator is not limited to the above embodiment, and can be changed as appropriate.

[0057]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the microcomputer (11), which can be used for evaluation of the microcomputer application system (42), performs the erasing and writing by the central processing unit based on the state of the data set in the control register means. Since it has the logic means (23) for detecting the violation of the control rule and outputting the detection result of the rule violation to the outside, in the evaluation such as the debugging of the microcomputer application system or the operating program therefor,
When access control is performed on the alternative volatile memory (14) arranged outside the microcomputer in place of the nonvolatile semiconductor memory device (12), control data that is peculiar control to the nonvolatile semiconductor memory device. Is set in the control register means by the central processing unit, and at this time, the logic means judges the adequacy of the control by the central processing unit for the control register means for defining the operation of the nonvolatile semiconductor memory device. You can

When the logic means has a problem of a rule violation between setting data to the control register means, the logic means, when the rewrite mode flag is disabled, enables the erase bit or the write bit. By including the first logic circuit 24 for detecting the above, it becomes possible to detect the rule violation that the voltage is not applied when the write or erase operation is instructed. In addition, the first logic circuit 24 detects the state in which both the erase bit and the write bit are enabled in the rewrite mode flag enabled state, so that the write and erase operations that cannot be executed at the same time are performed. It is possible to detect a rule violation, which means that instructions are given at the same time.

When the logic means makes a problem of a rule violation with respect to a setting order of individual setting data set in the control register means, the logic means includes an erase flag to disable the erase bit. If the erase flag is not enabled when the above-mentioned step is performed, it is possible to detect the rule violation that the erase bit setting operation has not been performed prior to that. Further, by virtue of the provision of the write flag, when the operation for disabling the write bit is performed, unless the write flag is enabled, the setting operation of the write bit preceding it is not performed. Can be detected. As described above, according to the erase flag (29) and the write flag (30), it is possible to detect an abnormality in the operation for the erase bit (be) and the write bit (Bp) based on the transition states thereof.

With respect to the detection timing of the erase flag (29) and the write flag (30), the logic means synchronizes with the write flag in synchronization with the update of the address information necessary for the electrical writing or erasing. The control register means includes a second logic circuit (31) for detecting whether or not both of the erase flags are in a disabled state, and the control register means sets a control bit (Bev) for inhibiting the detection operation by the second logic circuit. By further providing, the second logic circuit does not erroneously detect the rule violation due to the update of the access address by the pre-write corresponding process. After the control bit (Bev) is disabled after the prewrite operation, the change of the access address is
Since it is a timing to detect whether both the erase flag (29) and the write flag (30) are disabled, the erase operation is actually performed after the pre-write operation, and the erase bit is disabled. When the access address is changed next, the rule violation can be detected based on the erase flag. In the write operation, it is a normal control process that the write bit (Bp) is set to be enabled and the write bit (Bp) is set to be disabled after completion of the write for each write operation for one write address. Therefore, the second logic circuit 23 can detect the rule violation based on the write flag every time the access address changes.

[Brief description of drawings]

FIG. 1 is an overall block diagram of an evaluation microcomputer according to an embodiment of the present invention.

2 is a block diagram of an example of a microcomputer having a built-in flash memory, which corresponds to the evaluation microcomputer of FIG.

FIG. 3 is a block diagram of an example of an emulator that uses a microcomputer for evaluation.

FIG. 4 is a block diagram of an evaluation microcomputer mainly including a control register and a support circuit.

FIG. 5 is a logic circuit diagram showing an example of a first logic circuit.

FIG. 6 is a rewrite mode flag Fn and a write bit B.
FIG. 6 is an explanatory diagram showing an example of a violation of a convention with respect to a setting state of p and an erase bit Be.

FIG. 7 is a block diagram of an evaluation microcomputer equipped with another support circuit.

FIG. 8 is a block diagram of an evaluation microcomputer equipped with still another support circuit.

FIG. 9 is an explanatory diagram showing set timings of an erase flag and a write flag.

FIG. 10 is an overall block diagram showing an example of a flash memory.

FIG. 11: 2 as nonvolatile memory cell transistor
It is an explanatory view of an example of an insulated gate field effect transistor of a layer gate structure.

[Explanation of symbols]

 11 Microcomputer for evaluation 12 Flash memory 13, 13E RAM 14 Alternative memory 15 Emulator interface 19, 19E Central processing unit 22E Control register Fm Rewrite mode flag Bp Write bit Be Erase bit Vpp High voltage 23 Support circuit 24 First logic circuit 25 error flag 26 external terminal CRS register write control signal ERR1 error signal Bev erase confirmation bit 28 latch circuit 29 erase flag 30 write flag 31 second logic circuit 32 error flag 40 emulator

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoko Katase 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Incorporated company Hitachi Ltd. Semiconductor Business Division

Claims (7)

[Claims] 1. A central processing unit, and control register means for setting control data for controlling the erasing and writing of a nonvolatile semiconductor memory device capable of electrically erasing and writing data. In a microcomputer that can be used for evaluation of a microcomputer application system, a rule violation of the erase and write control by the central processing unit is detected based on a state of data set in the control register means. A microcomputer provided with a logic means for outputting a detection result of a rule violation to the outside. 2. The control register means is a rewrite mode flag indicating a high voltage application state required for writing and erasing of the nonvolatile semiconductor memory device, and an erase operation for instructing the nonvolatile semiconductor memory device to perform an erase operation. A first bit and a write bit for instructing a write operation to the nonvolatile semiconductor memory device, wherein the logic means detects an enable state of the erase bit or the write bit in a disable state of a rewrite mode flag. 2. The microcomputer according to claim 1, comprising one logic circuit. 3. The micro-circuit according to claim 2, wherein the first logic circuit further detects a state in which both the erase bit and the write bit are enabled in a rewrite mode flag enabled state. Computer. 4. The logic means further comprises latch means for latching the control data held by the control register means before the setting when new control data is set in the control register means. The control data latched in the latch means and the control data newly set to the control register means are input, and the erase bit of the newly set control data is disabled and the erase bit of the latch means is set. An erase flag that is enabled when is enabled, a write flag that is enabled when the write bit of the newly set control data is disabled and the write bit of the latch means is enabled, 4. The microcomputer according to claim 3, further comprising: 5. The second logic detects whether or not both the write flag and the erase flag are in a disabled state in synchronization with the update of the address information necessary for the electrical writing or erasing. 5. The microcomputer according to claim 4, further comprising a circuit, wherein the control register means further includes a control bit for inhibiting the detection operation by the second logic circuit. 6. The control bit is a control bit which permits a process for a volatile memory, which corresponds to a pre-write process for aligning memory cells in a written state in advance when erasing the nonvolatile semiconductor memory device. 6. The microcomputer according to claim 5, wherein: 7. The microcomputer according to claim 1, further comprising: a random accessible volatile alternative memory that replaces the nonvolatile semiconductor memory device. Debugging support device.