JP2000040386A - Semiconductor memory and data processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique for avoiding data destruction of a normal bit in forced write to a relief address. SOLUTION: This device is provided with an equalizing circuit 630 equalizing complementary common data lines to equal potential each other, and a control means controlling the equalizing circuit after additional write and before forced write to equalize complementary common data lines IO0-7, /IO0-7. Data destruction of a normal bit is evaded by equalizing a pre-charge level of a path from a Y pre-gate to a Y gate in a Y group decoding section to the prescribed pre- charge voltage and preventing affecting to a holding state of a sense latch in forced write-in.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a flash memory, and more particularly to a column circuit including a read data sensing and a write data latch and a column decoder, and an improvement technique of a control system thereof.
For example, it relates to a technology that is effective when applied to a file system.

[0002]

2. Description of the Related Art In a flash memory, a transistor having a floating gate, a control gate, a source and a drain is employed as a memory cell. The flash memory cell retains information depending on the presence or absence of charge in the floating gate. For example, when charge is injected into the floating gate, the threshold voltage of the memory cell increases. That is, by raising the threshold voltage higher than the voltage applied to the control gate for data reading, no current flows through the memory cell. In addition, when no charge is contained in the floating gate, a current flows through the memory cell because the threshold voltage of the memory cell is lower than the voltage applied to the control gate for reading data. Although not particularly limited, an operation of raising the threshold voltage of the memory cell above the word line selection level is referred to as an erasing operation, and an operation of lowering the threshold voltage of the memory cell below the word line selection level is referred to as a writing operation. . Note that erasing and writing may be defined in reverse.

When a voltage is applied to the control gate of the flash memory, a state in which a current flows or does not flow between the source and drain of the flash memory is caused by, for example, a static latch provided corresponding to each bit line. It is sensed by the sense latch. In a verify operation for checking whether a threshold voltage of a memory cell has reached a desired voltage at the time of writing or erasing, a sense operation similar to a read operation is required. In addition, when writing is performed by forming a high potential difference between the control gate and the drain, the selection of writing to the memory cell and the non-selection of writing are distinguished by increasing or decreasing the drain voltage for each memory cell. In this case, the sense latch latches data according to write selection or non-selection.

As an example of a document describing a flash memory, see 1994 Symposium on VSI Circuits Digest of Technical Papers, pp. 61-62 (1994 Sympo
sium on VLSI Circuits Digest of Technical Papers,
pp61-62).

[0005]

For example, a flash memory having an AND type memory cell structure has an additional write mode. The additional write mode is an operation mode for rewriting a word that has been written once.

FIG. 8 shows the logic of additional writing.
Memory data “1” means that the memory cell is in the erased state, and memory data “0” means that the memory cell is in the written state. Whether to perform additional writing or not
It is determined by the state of the memory data and the logical value of the input data. If the memory data is "1" and the input data is "1", no additional writing is performed. In other cases, additional writing is performed. Input data is latched in the sense latch similarly to writing. For example, the input data “1” causes the sense latch on the selected mat side to latch a high level, and the input data “0” causes the sense latch on the selected mat side to latch a low level. Thereafter, by performing the same operation as the program verify, the bit line of the selected mat is high level in the state, the bit line of the selected mat is low level in the state, and the selected mat is The bit line is set to low level, and in the case of the state, the bit line of the selected mat is set to low level. In the write verification, the state in which the bit line level of the selected mat is low (the state in which the sense latch on the selected mat latches the low level) is a write completed state. This state is reversed with respect to the case where additional writing is to be performed. Therefore, if the logic is inverted with respect to the latch state of the sense latch obtained by the same operation as the program verify operation and then the writing is performed, the additional writing shown in the column of the presence or absence of writing in FIG. 8 is realized. be able to.

In a verify operation for checking whether a threshold voltage of a memory cell has reached a desired voltage at the time of writing or erasing, it is determined whether or not all bits have been written. This is referred to as “all determination”. If it is determined in this all determination that even one bit has not been written, the write cycle is started again.

When there is a defective bit in the case where the redundancy relief has been performed, it is necessary to mask the defective bit so as not to interfere with the all judgment. This masking is enabled by forcibly writing low-level data to the corresponding sense latch. In other words, the corresponding sense latch
By forcibly writing low-level data, the above all determination can be passed.

However, if additional writing is performed before forced writing to the rescue address, after this additional writing is performed, a low-level floating state is established by a path from the Y gate to the Y pregate. When the Y gates are simultaneously opened by forced writing, charge sharing occurs between the residual charge (low level) in the path from the Y gate to the Y pre-gate and the high level of the sense latch, thereby causing the sense latch to fail. It has been found by the present inventor that normal data is destroyed.

An object of the present invention is to provide a technique for avoiding data destruction of normal bits in forced writing to a relief address.

[0011]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, it has a pair of input / output terminals, sense latch (640) for latching data transmitted to the input / output terminals, decodes the Y address signal, and based on the decoding result, When a semiconductor memory device is configured to include a Y-system decoding section (610, 620) for coupling an input / output terminal of a sense latch to a complementary common data line, the complementary common data lines are equalized to the same potential. And a control means (81) for operating the equalizing circuit after the additional writing and before the forced writing.

According to the above-mentioned means, the precharge level of the path from the Y pregate to the Y gate in the Y decoding section is made equal to the predetermined precharge voltage, so that the Y gates are simultaneously opened by forced writing. However, since the potential difference applied to the pair of input / output terminals of the sense latch thereby is substantially zero, the holding state of the sense latch is not affected. This avoids data destruction of normal bits in forced writing to the relief address.

At this time, the Y-system decoding section is a Y-dress decoder (611) for decoding a Y address.
And a plurality of Y gate groups (Q0-1 to Q15-1, Q0-2 to Q0) for selecting the input / output terminals of the sense latch.
15-2, Q0-15 to Q15-15) and a Y gate driver (61) for controlling the operation of the plurality of Y gate groups based on the decoding result of the Y address decoder.
2) and a Y pre-gate (QP-0 to QP-1) for selectively coupling the Y gate group to a complementary common data line.
5) and a Y pregate driver (613) for controlling the operation of the Y pregate based on the decoding result of the Y address decoder.

Further, the Y pre-gate driver operates regardless of the decoding result from the Y address decoder.
It can be easily configured by providing control logics NOR0 to NOR15 for selecting all the Y pregates according to the control signal from the control means.

Further, the semiconductor memory device (9
The data processing device can be configured including 6).

[0017]

FIG. 6 shows a file system which is an example of a data processing apparatus according to the present invention. 90
Although not particularly limited, a flash memory card converted into a PC card is indicated by ATA (AT Attac
hment) a type of card. The flash memory card 90 is not particularly limited, but may be an IDE (Integrated
It can be detachably attached to a computer 99 such as a personal computer via a standard bus 91 conforming to Device Electronics) via a connector (not shown).

The flash memory card 90 includes a bus interface unit 92, a write buffer 93, and an ECC circuit 9.
4. Microcomputer 95, flash memory 96
And a management table memory 97, which are commonly connected to an internal bus 98.

The bus interface unit 92 controls the interface with the standard bus 91 so as to conform to the specifications of the ATA card or the like. The write buffer 93 is a data buffer for temporarily storing write data supplied from the standard bus 91, and the data stored in the write buffer 93 is written to the flash memory 96. The ECC circuit 94 is a circuit having an error detection and gill correction function for improving the accuracy of data stored in the flash memory 96. The management table memory 9
Reference numeral 7 denotes an electrically rewritable semiconductor memory such as a flash memory or an EEPROM.
A sector management table and a rewrite frequency management table are formed. A defective address of the flash memory 96 is written in the sector management table. In particular, in the case of a flash memory, it is necessary to hold such an address because the characteristics of the memory cell are deteriorated as writing / erasing is repeatedly performed. The rewrite frequency management table holds information for managing the rewrite frequency of the memory cell in the flash memory 96 for each block of the flash memory, for example. The characteristics of the memory cells of the flash memory are guaranteed within a predetermined number of rewrites. The microcomputer 95 controls the entire inside of the card in accordance with an access request to the flash memory card 90, for example, issues an instruction for an operation to the flash memory and issues the command to control access to the flash memory 96 and control the management table memory 97. I do.

FIG. 7 shows an example of the overall configuration of the flash memory 96.

Although not particularly limited, the flash memory shown in FIG. 1 is formed on a single semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique.

MATU is the first memory mat 1, MATD
Is a second memory mat 2. In order to disperse one word line load capacity in each of the memory mats 1 and 2, the word lines arranged at the same address are divided into two, and a sub-decoder 19 is assigned to each. Although not particularly limited, this flash memory is an effective flash memory when applied to an ATA file memory compatible with a disk device. Word lines arranged at the same address have (2048 + 128) × 2 bit memory cells,
It corresponds to a 521 byte sector and a 16 byte sector management area.

Reference numeral 60 denotes a column circuit.
The column related circuit 60 includes a sense latch and a Y related decoding unit (to be described in detail later). The column selection gates 6 and 7 are each interfaced with eight pairs of common data lines 61, and the column decoder controls conduction between the eight pairs of common data lines 61 and the bit lines BLU and BLD according to column address signals and the like. The common data line 61 includes the non-inverting side common data lines IO0 to IO7 and the inverting side common data line / I
O / O (/ means low active or signal inversion) are coupled to a main amplifier (MA) 63 and an input / output buffer 64 via an input / output switching circuit 62.
The input / output buffer 64 is interfaced with the outside through an external connection electrode (I / O) such as a bonding pad.

The input / output buffer 64 is also used for input / output of memory data, input of address data, and input of command data. The write data to the memory cell is supplied to the common data line 61 via the output switching circuit 62. Read data from the memory mat is supplied to a main amplifier 63 via an input / output switching circuit 62,
There, it is amplified and applied to the input / output buffer 64.

The address data supplied to the input / output buffer 64 is supplied to an address counter 65, and is supplied to an address generator 66 to a main decoder 17, a gate decoder 18, a column decoder and the like. Although not particularly limited, an initial value of the address counter 65 is preset as address data, and is sequentially incremented according to an operation mode instructed to the flash memory by a command. The incremented address is output from the address generator 65. Memory mat 1,
Reference numeral 2 denotes a spare bit realized by a redundant word line (not shown) or the like, and a rescue circuit 68 replaces the address of the defective bit with a redundant address according to a program state of a redundant fuse trimming circuit 67 and supplies the redundant address to an address generator 66. Defective bits are replaced with spare bits. The address generator 66 forms an internal complementary address signal according to the input, and allocates the address signal to the main decoder 17, the gate decoder 18, the column decoder and the like.

The data input / output control circuit 70 to which the serial click SC is supplied from the outside is provided with the main amplifier 6
3. Input / output switching circuit 62 and address counter 65
And the input / output buffer 64 is synchronized with the serial clock SC.

The control signal input buffer 71 is supplied with an external control signal. The external control signals are supplied to a write enable signal WEB for instructing information input to the flash memory, a chip enable signal CEB for instructing operation of the flash memory, an output enable signal OEB for instructing information output of the flash memory, and the flash memory. Signal C indicating whether the information to be commanded is data or data
ED and a reset signal RESB. The internal operation of the flash memory is synchronized with a clock signal output from clock generator 72.

The command supplied from the input / output buffer 64 is supplied to the command decoder 73. The command is a command related to reading (reading), writing (programming), and erasing (erasing) of a memory cell. The contents specified by the program and the erase command include a verify operation. The internal control based on the command is a control method similar to the so-called microprogram control. That is, the ROM holds a series of control codes (state information) for specifying processing according to the command for each command. The decoding result of the command by the command decoder 73 is used as the head address in the ROM 75 of the control code sequence corresponding to the command. By giving the command decoding result to the ROM 75, the head control code of the control code sequence corresponding to the command is read from the ROM 75. The read control code is decoded by the ROM decoder 76 and supplies an operation control signal to the write / erase determination circuit 80, the direct system control circuit 81, and the power supply control circuit 82. The second and subsequent control codes in the control code sequence are designated by the ROM control system circuit 74 based on the ROM address of the head control code. If the execution order of the control code is to be conditionally branched, the control code may have the ROM address of the next control code as in the case of the microprogram.

The power supply control circuit 82 controls the supply of operation power for various circuits necessary for the read, program and erase operations. The operating power supply is, for example, a reference voltage generating circuit 85 that generates a reference voltage based on a silicon band gap or the like, and a charge pump circuit that generates a power supply such as -10 V using the reference voltage generated by the reference voltage generating circuit 85. 84, and a power supply switching circuit 83 for switching the operation power supply of various circuits such as a main decoder in accordance with operations such as read, erase, and program. The write / erase determination circuit 80 is a circuit for determining completion of a write operation or an erase operation. The determination result is supplied to the ROM control system circuit 74, and is reflected in the control contents in the next control step of the series of the writing operation or the erasing operation. The direct system control circuit 81 controls word line selection timing and column selection timing.

Reference numeral 86 denotes a status register and a test system circuit. The status register and the test system circuit 86 can output the internal state of the flash memory to the outside via the input / output buffer 64. , And the ready / busy status is output to the outside via the buffer 87.

FIG. 1 shows a configuration example of the column circuit 60.

The column circuit 60 has a pair of input / output terminals, a plurality of sense latches (SL) 640 for latching data transmitted to the input / output terminals,
Y-system decoding units 610 and 620 for decoding the address signal and coupling the input / output terminals of the sense latch 640 to the complementary common data lines IO0-7 and / IO0-7 based on the decoding result. Each of the plurality of sense latches 640 includes two inverters coupled in a loop.

The complementary common data lines IO0-7, / I
O0-7 correspond to the common data line 61 shown in FIG. 7, and the common data lines IO0-7 are on the non-inverting side, and the common data lines / IO0-7 are on the inverting side. Equalizing circuit 6 for equalizing such complementary common data lines IO0-7 and / IO0-7 to the same potential.
30 are provided.

The detailed configuration of each section will be described.

FIG. 2 shows an example of the configuration of the Y-system decoding unit 610.

A Y address decoder 611 for decoding the input Y address is provided. Due to the layering of the address decode, the lower several bits of the address decode result of the Y address decoder 611 are transmitted to the subsequent Y gate driver 612, and the upper several bits are transmitted to the subsequent Y pregate driver 613. A plurality of Y gates are provided corresponding to one of the pair of input / output terminals in sense latch 640. Of the plurality of Y gates, Q0-1 to Q0-15, Q1-1 to Q1-1
5, Q15-1 to Q15-15 are representatively shown. The Y gate drive signal YG0 is output from the Y gate driver 612.
To YG15 are output. The Y gates Q0-1 to Q0-15 are driven by the Y gate drive signal YG0, and the Y gate Q1-1 is driven by the Y gate drive signal YG1.
To Q1-15 are driven, and the Y gates Q15-1 to Q15-15 are driven by the Y gate drive signal YG15.

Further, the Y coupled to the plurality of Y gates
Pregates QP-0 to QP-15 are provided. One terminal of Y pregates QP-0 to QP-15 is
The common terminal is connected to the gate driver, and the other terminal is commonly connected to the common data line. The above Y pre-gate driver 6
13 outputs Y pre-gate drive signals YPG0 to YPG15, among which Y pre-gate drive signal YPG0 drives Y pre-gate QP-0, Y pre-gate drive signal YPG1 drives Y pre-gate QP-1, and Y pre-gate drive signal YPG15 drives Y pregate QP-15.

Incidentally, the Y-side decoding section 620 on the inversion side is configured similarly to the Y-system decoding section 610.

FIG. 3 shows a configuration example of the Y predecoder 613.

The output signal of the Y address decoder 611,
NOR gate NO for obtaining NOR logic with all selection signal ASEL
R0 to NOR15 are provided, and the NOR gate NOR0 is provided.
After inverters NOR15 to NOR15, inverters INV0 to INV15 for inverting the output signals of the corresponding NOR gates are provided. Output signals of the inverters INV0 to INV15 are Y pregate drive signals YGP0 to YG, respectively.
P15 is set. With such a configuration, the all-selection signal A
When SEL is negated to the high level, all of the Y pre-gate drive signals YGP0 to YGP15 are asserted to the high level regardless of the output signal of the Y address decoder 611 at that time. -0 to QP-15 (see FIG. 2) are driven to the open state.

FIG. 4 shows a configuration example of the equalizing circuit 630.

The equalizing circuit 630 includes an equalizing section 630B for equalizing between complementary common data lines.
And an equalizing power supply 630A for supplying an equalizing voltage to the equalizing section 630B.

The equalizing power supply 630A includes a p-channel MOS transistor Q16 and an n-channel MOS transistor Q17 connected in series. The source electrode of p-channel type MOS transistor Q16 is coupled to high potential side power supply Vcc. The equalizing signal A is applied to the gate electrode of the p-channel type MOS transistor Q16.
Is supplied (negative logic). The bias voltage V1 for generating the equalizing voltage Veq is supplied to the gate electrode of the n-channel MOS transistor Q17. The bias voltage V1 is not particularly limited, but is set to a level higher than the threshold level of the n-channel MOS transistor by about 0.5 V. The equalizing signal A, its negative logic signal, and the bias voltage V1 are formed by the direct system control circuit 81.

The equalizing section 630B has n-channel MOS transistors Q20 and Q21 connected in series so as to bridge the complementary common data lines IO0 and / IO0, and controls the voltage level of the series connection node N1. N-channel type MOS transistors Q18, Q19
Is provided. The equalizing signal A is supplied from the direct system control circuit 81 to the gate electrodes of the n-channel MOS transistors Q20 and Q21. The series connection node N1 is connected to the equalizing power supply 6 via the n-channel MOS transistor Q18.
30A n-channel MOS transistor Q1
7 source electrode. The series connection node N1 is connected to the n-channel MOS transistor Q1.
9 is coupled to the lower potential side power supply Vss. Voltage control signals B and C are supplied to the gate electrodes of the n-channel MOS transistors Q18 and Q19, respectively. The voltage control signals B and C are formed by the direct system control circuit 81.

FIG. 5 shows the timing of the equalizing operation.

According to the prior art, the forced writing is performed after the additional writing is performed. In the above configuration, as shown in FIG. 5, the forced writing is performed after the additional writing is performed. Before the operation is performed, all the Y pre-gates are selected, the common data line is reset and the equalizing power supply is activated, and the common data line is precharged.

All the Y pre-gates are selected by the direct system control circuit 8.
This is made possible by asserting the all-selection signal ASEL from 1 to a high level (high-potential-side power supply Vcc level). That is, when the all-selection signal ASEL is asserted to a high level, the Y pre-gate driver 613 asserts the Y-pregate drive signals YPG0 to YPG15 to a high level, whereby the Y-pregates QP-0 to QP-0
P-15 is opened.

Next, the common data line is reset, and the equalizing power supply is started.

That is, the voltage control signal C is asserted to the high level by the direct system control circuit 81, and the equalize signal A is asserted to the high level, and its negative logic / A is asserted to the low level. When the equalize signal A is asserted to a high level, the n-channel MOS transistors Q20 and Q21 are turned on, and the complementary common data lines IO0 to 7 and / IO0 to 7 are short-circuited. Also, when the voltage control signal C is asserted to a high level, n
The channel type MOS transistor Q19 is turned on, whereby the series connection node N1 of the n-channel type MOS transistors Q20 and Q21 is made equal to the level of the low potential side power supply Vss. As a result, the complementary common data line is reset. Then, the p-channel MOS transistor Q16 in the equalizing power supply 630A is turned on, and an equalizing voltage Veq (about 0.5 V) is formed. However, at this time, since voltage control signal B is at the low level, equalizing voltage Veq is not transmitted to node N1.

Next, the voltage control signal C is negated to a low level, and instead, the voltage control signal B is asserted to a high level. As a result, the n-channel MOS transistor Q18 is turned on, and the equalizing voltage Veq
Is supplied to the node N1, and the equalizing voltage Veq is applied to the n-channel MOS transistors Q20 and Q20.
21 and complementary data lines IO0-7, / IO0
~ 7. Thereby, the complementary common data line I
Equalization of O0-7 and / IO0-7 is performed, and at the same time, pre-charging to equalize voltage Veq.

Next, in the forced write, the direct system control circuit 81 negates the entire selection signal ASEL to a low level, negates the equalization signal A to a low level, and negates the voltage control signal B to a low level. . As a result, the precharge level of the path from the Y pregate to the Y gate in both of the Y decode units 610 and 620 becomes equal to the precharge voltage Veq.
That is, the Y pre-gates QP-0 to Y gates Q0-1 and Q1-
1, a path from Q15-1, etc., a path from Y pregate QP-1 to Y gates Q0-2, Q1-2, Q15-2, etc., a path from Y pregate QP-15 to Y gate Q0-15,
The potential of the path leading to Q1-15, Q15-15, etc. is equal to the precharge voltage Veq.

Here, according to the conventional device, forced writing is performed immediately after additional writing. According to this, the path from the Y gate to the Y pre-gate is in a low-level floating state. When the Y gates are simultaneously opened by forced writing, the above Y
Charge sharing occurs between the residual charge (low level) of the path from the gate to the Y pre-gate and the high level of the sense latch, thereby destroying the normal data of the sense latch.

On the other hand, in the above configuration, the precharge level of the path from the Y pregate to the Y gate in both of the Y decode sections 610 and 620 is made equal to the precharge voltage Veq (for example, 0.5 V). Therefore, even if the Y gates are simultaneously opened in the forced writing, the potential difference between the pair of input / output terminals of the sense latch is substantially zero, so that the holding state of the sense latch is not affected. In other words, it is not necessary to destroy the normal data of the sense latch.

According to the above example, the following functions and effects can be obtained.

(1) The precharge level of the path from the Y pregate to the Y gate in both of the Y-system decode units 610 and 620 is the precharge voltage Veq (for example, 0.
5V), the potential difference applied to the pair of input / output terminals of the sense latch is almost zero even if the Y gates are simultaneously opened by forced writing, so that normal data in the sense latch is not destroyed. I'm done.

(2) Since the reliability of the data read from the flash memory 96 can be improved by the operation and effect of the above (1), the file system including the flash memory 96 can be connected to the outside. The reliability of the exchanged data can be improved.

Although the invention made by the inventor has been specifically described above, the present invention is not limited to this, and it goes without saying that various modifications can be made without departing from the gist of the invention.

In the above description, the case where the invention made by the present inventor is mainly applied to a flash memory for a file memory system, which is the field of application, has been described. It can also be used for memory and other systems. It is also possible to configure as an on-chip memory of a microcomputer. Further, the present invention is not limited to a flash memory, but can be applied to an electrically rewritable nonvolatile semiconductor memory device such as an EEPROM.

The present invention can be applied on the condition that it has at least a pair of input / output terminals and includes a sense latch for latching data transmitted to the input / output terminals.

[0060]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the precharge level of the path from the Y pregate to the Y gate in the Y decode section is made equal to the predetermined precharge voltage. Therefore, even if the Y gates are simultaneously opened by forced writing, the sense latch is not used. Since the potential difference applied between the pair of input / output terminals is substantially zero, the holding state of the sense latch is not affected. For this reason, it is possible to avoid data destruction of normal bits in forced writing to the relief address.
In addition, since the reliability of data read from the semiconductor memory device can be improved thereby, data reliability can be improved in a data processing device including such a semiconductor memory device.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration example of a main part in a flash memory as an example of a semiconductor memory device according to the present invention.

FIG. 2 is a circuit diagram showing a configuration example of a Y-system decoding unit included in a main part of the flash memory shown in FIG. 1;

FIG. 3 is a circuit diagram showing a configuration example of a Y pre-gate driver included in a Y-system decoding unit shown in FIG. 2;

FIG. 4 is a circuit diagram showing a configuration example of an equalizing circuit included in a main part of the flash memory shown in FIG. 1;

FIG. 5 is an operation timing chart of the equalizing circuit.

FIG. 6 is a block diagram illustrating a configuration example of a file system including the flash memory.

FIG. 7 is a block diagram illustrating an overall configuration example of the flash memory.

FIG. 8 is an explanatory diagram of additional write logic in the flash memory.

[Explanation of symbols]

 Reference Signs List 60 column circuit 81 direct system control circuit 95 microcomputer 96 flash memory 98 internal bus 610, 620 Y system decoding unit 611 Y address decoder 612 Y gate driver 613 Y pregate driver 630 equalizing circuit 640 sense latch

Claims (4)

[Claims] A sense latch for latching data transmitted to the input / output terminals; a sense latch for decoding a Y address signal; and a sense latch based on the decode result. And a Y-system decoding unit for coupling an input / output terminal to a complementary common data line, and perform additional writing for rewriting a once written word and forced writing for forcibly writing to the sense latch. A semiconductor memory device that enables the equalizing circuit to equalize the complementary common data lines to the same potential; control means for operating the equalizing circuit after the additional writing and before the forced writing; A semiconductor memory device comprising: 2. The Y-system decoding unit, wherein: a Y-dress decoder for decoding a Y address; a plurality of Y-gate groups for selecting an input / output terminal of the sense latch; A Y gate driver for controlling the operation of the plurality of Y gate groups based on the following: a Y pregate for selectively coupling the plurality of Y gate groups to a complementary common data line; a decoding result of the Y address decoder 2. The semiconductor memory device according to claim 1, further comprising: a Y pre-gate driver that controls the operation of the Y pre-gate based on the following. 3. The control circuit according to claim 2, wherein said Y pre-gate driver includes control logic for selecting all Y pre-gates in accordance with a control signal from said control means, regardless of a decoding result from said Y address decoder. Semiconductor storage device. 4. A data processing device comprising a semiconductor memory device according to claim 1 and a microcomputer for controlling access to said semiconductor memory device, connected by a bus.