JPH09244895A5 - - Google Patents

Info

Publication number
JPH09244895A5
JPH09244895A5 JP1997027423A JP2742397A JPH09244895A5 JP H09244895 A5 JPH09244895 A5 JP H09244895A5 JP 1997027423 A JP1997027423 A JP 1997027423A JP 2742397 A JP2742397 A JP 2742397A JP H09244895 A5 JPH09244895 A5 JP H09244895A5
Authority
JP
Japan
Prior art keywords
instruction
instructions
execution
incorrect
order
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1997027423A
Other languages
English (en)
Japanese (ja)
Other versions
JPH09244895A (ja
JP3715057B2 (ja
Filing date
Publication date
Priority claimed from US08/609,807 external-priority patent/US5838942A/en
Application filed filed Critical
Publication of JPH09244895A publication Critical patent/JPH09244895A/ja
Publication of JPH09244895A5 publication Critical patent/JPH09244895A5/ja
Application granted granted Critical
Publication of JP3715057B2 publication Critical patent/JP3715057B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP02742397A 1996-03-01 1997-02-12 パニック・トラップ・システム Expired - Fee Related JP3715057B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US609,807 1996-03-01
US08/609,807 US5838942A (en) 1996-03-01 1996-03-01 Panic trap system and method

Publications (3)

Publication Number Publication Date
JPH09244895A JPH09244895A (ja) 1997-09-19
JPH09244895A5 true JPH09244895A5 (enExample) 2004-12-24
JP3715057B2 JP3715057B2 (ja) 2005-11-09

Family

ID=24442416

Family Applications (1)

Application Number Title Priority Date Filing Date
JP02742397A Expired - Fee Related JP3715057B2 (ja) 1996-03-01 1997-02-12 パニック・トラップ・システム

Country Status (4)

Country Link
US (1) US5838942A (enExample)
JP (1) JP3715057B2 (enExample)
DE (1) DE19650509C2 (enExample)
GB (1) GB2310742B (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6892294B1 (en) 2000-02-03 2005-05-10 Hewlett-Packard Development Company, L.P. Identifying execution ready instructions and allocating ports associated with execution resources in an out-of-order processor
US11886377B2 (en) * 2019-09-10 2024-01-30 Cornami, Inc. Reconfigurable arithmetic engine circuit

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1990010267A1 (en) * 1989-02-24 1990-09-07 Nexgen Microsystems Distributed pipeline control for a computer
US5280615A (en) * 1990-03-23 1994-01-18 Unisys Corporation Out of order job processing method and apparatus
JP2642529B2 (ja) * 1991-04-30 1997-08-20 株式会社東芝 並列プロセッサーの命令分配処理装置
US5630157A (en) * 1991-06-13 1997-05-13 International Business Machines Corporation Computer organization for multiple and out-of-order execution of condition code testing and setting instructions
US5345569A (en) * 1991-09-20 1994-09-06 Advanced Micro Devices, Inc. Apparatus and method for resolving dependencies among a plurality of instructions within a storage device
JPH0820949B2 (ja) * 1991-11-26 1996-03-04 松下電器産業株式会社 情報処理装置
WO1994008287A1 (en) * 1992-09-29 1994-04-14 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US5467473A (en) * 1993-01-08 1995-11-14 International Business Machines Corporation Out of order instruction load and store comparison
US5420990A (en) * 1993-06-17 1995-05-30 Digital Equipment Corporation Mechanism for enforcing the correct order of instruction execution
GB2284493B (en) * 1993-12-01 1998-04-01 Intel Corp Exception handling in a processor that performs speculative out-of-order instruction execution
US5627985A (en) * 1994-01-04 1997-05-06 Intel Corporation Speculative and committed resource files in an out-of-order processor
US5524263A (en) * 1994-02-25 1996-06-04 Intel Corporation Method and apparatus for partial and full stall handling in allocation
US5546597A (en) * 1994-02-28 1996-08-13 Intel Corporation Ready selection of data dependent instructions using multi-cycle cams in a processor performing out-of-order instruction execution
US5584037A (en) * 1994-03-01 1996-12-10 Intel Corporation Entry allocation in a circular buffer
US5546599A (en) * 1994-03-31 1996-08-13 International Business Machines Corporation Processing system and method of operation for processing dispatched instructions with detected exceptions
US5649225A (en) * 1994-06-01 1997-07-15 Advanced Micro Devices, Inc. Resynchronization of a superscalar processor
US5625789A (en) * 1994-10-24 1997-04-29 International Business Machines Corporation Apparatus for source operand dependendency analyses register renaming and rapid pipeline recovery in a microprocessor that issues and executes multiple instructions out-of-order in a single cycle
US5625835A (en) * 1995-05-10 1997-04-29 International Business Machines Corporation Method and apparatus for reordering memory operations in a superscalar or very long instruction word processor

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